2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
4 * i.MX6UL SOC emulation.
6 * Based on hw/arm/fsl-imx7.c
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #include "hw/arm/fsl-imx6ul.h"
22 #include "hw/misc/unimp.h"
23 #include "hw/usb/imx-usb-phy.h"
24 #include "hw/boards.h"
25 #include "sysemu/sysemu.h"
26 #include "qemu/error-report.h"
27 #include "qemu/module.h"
31 static void fsl_imx6ul_init(Object *obj)
33 FslIMX6ULState *s = FSL_IMX6UL(obj);
37 object_initialize_child(obj, "cpu0", &s->cpu,
38 ARM_CPU_TYPE_NAME("cortex-a7"));
43 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
49 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM);
54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
59 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
64 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
69 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
70 snprintf(name, NAME_SIZE, "gpio%d", i);
71 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
77 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
78 snprintf(name, NAME_SIZE, "gpt%d", i);
79 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
85 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
86 snprintf(name, NAME_SIZE, "epit%d", i + 1);
87 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
93 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
94 snprintf(name, NAME_SIZE, "spi%d", i + 1);
95 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
101 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
102 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
103 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
109 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
110 snprintf(name, NAME_SIZE, "uart%d", i);
111 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
117 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
118 snprintf(name, NAME_SIZE, "eth%d", i);
119 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
125 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
126 snprintf(name, NAME_SIZE, "usbphy%d", i);
127 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
133 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
134 snprintf(name, NAME_SIZE, "usb%d", i);
135 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
141 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
142 snprintf(name, NAME_SIZE, "usdhc%d", i);
143 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
149 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
150 snprintf(name, NAME_SIZE, "wdt%d", i);
151 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
155 static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
157 MachineState *ms = MACHINE(qdev_get_machine());
158 FslIMX6ULState *s = FSL_IMX6UL(dev);
160 char name[NAME_SIZE];
164 if (ms->smp.cpus > 1) {
165 error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
166 TYPE_FSL_IMX6UL, ms->smp.cpus);
170 qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
175 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort);
176 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
177 FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort);
178 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
179 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
181 sbd = SYS_BUS_DEVICE(&s->a7mpcore);
184 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
185 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
186 sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));
187 sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ));
192 create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
193 FSL_IMX6UL_A7MPCORE_DAP_SIZE);
198 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
199 static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
200 FSL_IMX6UL_GPT1_ADDR,
201 FSL_IMX6UL_GPT2_ADDR,
204 static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
209 s->gpt[i].ccm = IMX_CCM(&s->ccm);
210 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
212 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
213 FSL_IMX6UL_GPTn_ADDR[i]);
215 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
216 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
217 FSL_IMX6UL_GPTn_IRQ[i]));
223 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
224 static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
225 FSL_IMX6UL_EPIT1_ADDR,
226 FSL_IMX6UL_EPIT2_ADDR,
229 static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
230 FSL_IMX6UL_EPIT1_IRQ,
231 FSL_IMX6UL_EPIT2_IRQ,
234 s->epit[i].ccm = IMX_CCM(&s->ccm);
235 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort);
237 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
238 FSL_IMX6UL_EPITn_ADDR[i]);
240 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
241 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
242 FSL_IMX6UL_EPITn_IRQ[i]));
248 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
249 static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
250 FSL_IMX6UL_GPIO1_ADDR,
251 FSL_IMX6UL_GPIO2_ADDR,
252 FSL_IMX6UL_GPIO3_ADDR,
253 FSL_IMX6UL_GPIO4_ADDR,
254 FSL_IMX6UL_GPIO5_ADDR,
257 static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
258 FSL_IMX6UL_GPIO1_LOW_IRQ,
259 FSL_IMX6UL_GPIO2_LOW_IRQ,
260 FSL_IMX6UL_GPIO3_LOW_IRQ,
261 FSL_IMX6UL_GPIO4_LOW_IRQ,
262 FSL_IMX6UL_GPIO5_LOW_IRQ,
265 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
266 FSL_IMX6UL_GPIO1_HIGH_IRQ,
267 FSL_IMX6UL_GPIO2_HIGH_IRQ,
268 FSL_IMX6UL_GPIO3_HIGH_IRQ,
269 FSL_IMX6UL_GPIO4_HIGH_IRQ,
270 FSL_IMX6UL_GPIO5_HIGH_IRQ,
273 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
276 FSL_IMX6UL_GPIOn_ADDR[i]);
278 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
279 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
280 FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
282 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
283 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
284 FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
290 create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
291 FSL_IMX6UL_IOMUXC_SIZE);
292 create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
293 FSL_IMX6UL_IOMUXC_GPR_SIZE);
298 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
299 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
304 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
305 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
310 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
311 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
316 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
317 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
318 FSL_IMX6UL_ECSPI1_ADDR,
319 FSL_IMX6UL_ECSPI2_ADDR,
320 FSL_IMX6UL_ECSPI3_ADDR,
321 FSL_IMX6UL_ECSPI4_ADDR,
324 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
325 FSL_IMX6UL_ECSPI1_IRQ,
326 FSL_IMX6UL_ECSPI2_IRQ,
327 FSL_IMX6UL_ECSPI3_IRQ,
328 FSL_IMX6UL_ECSPI4_IRQ,
331 /* Initialize the SPI */
332 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
335 FSL_IMX6UL_SPIn_ADDR[i]);
337 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
338 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
339 FSL_IMX6UL_SPIn_IRQ[i]));
345 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
346 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
347 FSL_IMX6UL_I2C1_ADDR,
348 FSL_IMX6UL_I2C2_ADDR,
349 FSL_IMX6UL_I2C3_ADDR,
350 FSL_IMX6UL_I2C4_ADDR,
353 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
360 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
361 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
363 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
364 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
365 FSL_IMX6UL_I2Cn_IRQ[i]));
371 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
372 static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
373 FSL_IMX6UL_UART1_ADDR,
374 FSL_IMX6UL_UART2_ADDR,
375 FSL_IMX6UL_UART3_ADDR,
376 FSL_IMX6UL_UART4_ADDR,
377 FSL_IMX6UL_UART5_ADDR,
378 FSL_IMX6UL_UART6_ADDR,
379 FSL_IMX6UL_UART7_ADDR,
380 FSL_IMX6UL_UART8_ADDR,
383 static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = {
384 FSL_IMX6UL_UART1_IRQ,
385 FSL_IMX6UL_UART2_IRQ,
386 FSL_IMX6UL_UART3_IRQ,
387 FSL_IMX6UL_UART4_IRQ,
388 FSL_IMX6UL_UART5_IRQ,
389 FSL_IMX6UL_UART6_IRQ,
390 FSL_IMX6UL_UART7_IRQ,
391 FSL_IMX6UL_UART8_IRQ,
394 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
396 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
399 FSL_IMX6UL_UARTn_ADDR[i]);
401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
402 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
403 FSL_IMX6UL_UARTn_IRQ[i]));
409 * We must use two loops since phy_connected affects the other interface
410 * and we have to set all properties before calling sysbus_realize().
412 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
413 object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected",
414 s->phy_connected[i], &error_abort);
416 * If the MDIO bus on this controller is not connected, assume the
417 * other controller provides support for it.
419 if (!s->phy_connected[i]) {
420 object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer",
421 OBJECT(&s->eth[i]), &error_abort);
425 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
426 static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
427 FSL_IMX6UL_ENET1_ADDR,
428 FSL_IMX6UL_ENET2_ADDR,
431 static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = {
432 FSL_IMX6UL_ENET1_IRQ,
433 FSL_IMX6UL_ENET2_IRQ,
436 static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = {
437 FSL_IMX6UL_ENET1_TIMER_IRQ,
438 FSL_IMX6UL_ENET2_TIMER_IRQ,
441 object_property_set_uint(OBJECT(&s->eth[i]), "phy-num",
442 s->phy_num[i], &error_abort);
443 object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num",
444 FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort);
445 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
446 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
448 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
449 FSL_IMX6UL_ENETn_ADDR[i]);
451 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
452 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
453 FSL_IMX6UL_ENETn_IRQ[i]));
455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
456 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
457 FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
463 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
465 FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
466 FSL_IMX6UL_USBPHY1_ADDR,
467 FSL_IMX6UL_USBPHY2_ADDR,
470 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
471 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
472 FSL_IMX6UL_USB_PHYn_ADDR[i]);
478 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
479 static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
480 FSL_IMX6UL_USBO2_USB1_ADDR,
481 FSL_IMX6UL_USBO2_USB2_ADDR,
484 static const int FSL_IMX6UL_USBn_IRQ[] = {
489 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
490 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
491 FSL_IMX6UL_USB02_USBn_ADDR[i]);
492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
493 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
494 FSL_IMX6UL_USBn_IRQ[i]));
500 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
501 static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
502 FSL_IMX6UL_USDHC1_ADDR,
503 FSL_IMX6UL_USDHC2_ADDR,
506 static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
507 FSL_IMX6UL_USDHC1_IRQ,
508 FSL_IMX6UL_USDHC2_IRQ,
511 object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor",
512 SDHCI_VENDOR_IMX, &error_abort);
513 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
515 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
516 FSL_IMX6UL_USDHCn_ADDR[i]);
518 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
519 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
520 FSL_IMX6UL_USDHCn_IRQ[i]));
526 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
527 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
532 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
533 static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
534 FSL_IMX6UL_WDOG1_ADDR,
535 FSL_IMX6UL_WDOG2_ADDR,
536 FSL_IMX6UL_WDOG3_ADDR,
539 static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
540 FSL_IMX6UL_WDOG1_IRQ,
541 FSL_IMX6UL_WDOG2_IRQ,
542 FSL_IMX6UL_WDOG3_IRQ,
545 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
547 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
549 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
550 FSL_IMX6UL_WDOGn_ADDR[i]);
551 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
552 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
553 FSL_IMX6UL_WDOGn_IRQ[i]));
559 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
560 FSL_IMX6UL_SDMA_SIZE);
563 * SAIs (Audio SSI (Synchronous Serial Interface))
565 for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
566 static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
567 FSL_IMX6UL_SAI1_ADDR,
568 FSL_IMX6UL_SAI2_ADDR,
569 FSL_IMX6UL_SAI3_ADDR,
572 snprintf(name, NAME_SIZE, "sai%d", i);
573 create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
574 FSL_IMX6UL_SAIn_SIZE);
580 for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
581 static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
582 FSL_IMX6UL_PWM1_ADDR,
583 FSL_IMX6UL_PWM2_ADDR,
584 FSL_IMX6UL_PWM3_ADDR,
585 FSL_IMX6UL_PWM4_ADDR,
586 FSL_IMX6UL_PWM5_ADDR,
587 FSL_IMX6UL_PWM6_ADDR,
588 FSL_IMX6UL_PWM7_ADDR,
589 FSL_IMX6UL_PWM8_ADDR,
592 snprintf(name, NAME_SIZE, "pwm%d", i);
593 create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
594 FSL_IMX6UL_PWMn_SIZE);
598 * Audio ASRC (asynchronous sample rate converter)
600 create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
601 FSL_IMX6UL_ASRC_SIZE);
606 for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
607 static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
608 FSL_IMX6UL_CAN1_ADDR,
609 FSL_IMX6UL_CAN2_ADDR,
612 snprintf(name, NAME_SIZE, "can%d", i);
613 create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
614 FSL_IMX6UL_CANn_SIZE);
620 create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
621 FSL_IMX6UL_APBH_DMA_SIZE);
626 for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) {
627 static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = {
628 FSL_IMX6UL_ADC1_ADDR,
629 FSL_IMX6UL_ADC2_ADDR,
632 snprintf(name, NAME_SIZE, "adc%d", i);
633 create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
634 FSL_IMX6UL_ADCn_SIZE);
640 create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
641 FSL_IMX6UL_LCDIF_SIZE);
646 create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
647 FSL_IMX6UL_CSU_SIZE);
652 create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
653 FSL_IMX6UL_TZASC_SIZE);
658 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom",
659 FSL_IMX6UL_ROM_SIZE, &error_abort);
660 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
666 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam",
667 FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
668 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
674 memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram",
675 FSL_IMX6UL_OCRAM_MEM_SIZE,
677 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR,
681 * internal OCRAM (128 KB) is aliased over 512 KB
683 memory_region_init_alias(&s->ocram_alias, OBJECT(dev),
684 "imx6ul.ocram_alias", &s->ocram, 0,
685 FSL_IMX6UL_OCRAM_ALIAS_SIZE);
686 memory_region_add_subregion(get_system_memory(),
687 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
690 static Property fsl_imx6ul_properties[] = {
691 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
692 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
693 DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0],
695 DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1],
697 DEFINE_PROP_END_OF_LIST(),
700 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
702 DeviceClass *dc = DEVICE_CLASS(oc);
704 device_class_set_props(dc, fsl_imx6ul_properties);
705 dc->realize = fsl_imx6ul_realize;
706 dc->desc = "i.MX6UL SOC";
707 /* Reason: Uses serial_hds and nd_table in realize() directly */
708 dc->user_creatable = false;
711 static const TypeInfo fsl_imx6ul_type_info = {
712 .name = TYPE_FSL_IMX6UL,
713 .parent = TYPE_DEVICE,
714 .instance_size = sizeof(FslIMX6ULState),
715 .instance_init = fsl_imx6ul_init,
716 .class_init = fsl_imx6ul_class_init,
719 static void fsl_imx6ul_register_types(void)
721 type_register_static(&fsl_imx6ul_type_info);
723 type_init(fsl_imx6ul_register_types)