2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "standard-headers/linux/input.h"
73 #include "hw/arm/smmuv3.h"
74 #include "hw/acpi/acpi.h"
75 #include "target/arm/internals.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "hw/acpi/generic_event_device.h"
79 #include "hw/virtio/virtio-md-pci.h"
80 #include "hw/virtio/virtio-iommu.h"
81 #include "hw/char/pl011.h"
82 #include "qemu/guest-random.h"
84 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
85 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
88 MachineClass *mc = MACHINE_CLASS(oc); \
89 virt_machine_##major##_##minor##_options(mc); \
90 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
95 static const TypeInfo machvirt_##major##_##minor##_info = { \
96 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
97 .parent = TYPE_VIRT_MACHINE, \
98 .class_init = virt_##major##_##minor##_class_init, \
100 static void machvirt_machine_##major##_##minor##_init(void) \
102 type_register_static(&machvirt_##major##_##minor##_info); \
104 type_init(machvirt_machine_##major##_##minor##_init);
106 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
107 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
108 #define DEFINE_VIRT_MACHINE(major, minor) \
109 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
112 /* Number of external interrupt lines to configure the GIC with */
115 #define PLATFORM_BUS_NUM_IRQS 64
117 /* Legacy RAM limit in GB (< version 4.0) */
118 #define LEGACY_RAMLIMIT_GB 255
119 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
121 /* Addresses and sizes of our components.
122 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
123 * 128MB..256MB is used for miscellaneous device I/O.
124 * 256MB..1GB is reserved for possible future PCI support (ie where the
125 * PCI memory window will go if we add a PCI host controller).
126 * 1GB and up is RAM (which may happily spill over into the
127 * high memory region beyond 4GB).
128 * This represents a compromise between how much RAM can be given to
129 * a 32 bit VM and leaving space for expansion and in particular for PCI.
130 * Note that devices should generally be placed at multiples of 0x10000,
131 * to accommodate guests using 64K pages.
133 static const MemMapEntry base_memmap[] = {
134 /* Space up to 0x8000000 is reserved for a boot ROM */
135 [VIRT_FLASH] = { 0, 0x08000000 },
136 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
137 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
138 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
139 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
140 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
141 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
142 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
143 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
144 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
145 /* This redistributor space allows up to 2*64kB*123 CPUs */
146 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
147 [VIRT_UART] = { 0x09000000, 0x00001000 },
148 [VIRT_RTC] = { 0x09010000, 0x00001000 },
149 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
150 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
151 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
152 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
153 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
154 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
155 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
156 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
157 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
158 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
159 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
160 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
161 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
162 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
163 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
164 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
165 /* Actual RAM size depends on initial RAM and device memory settings */
166 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
170 * Highmem IO Regions: This memory map is floating, located after the RAM.
171 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
172 * top of the RAM, so that its base get the same alignment as the size,
173 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
174 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
175 * Note the extended_memmap is sized so that it eventually also includes the
176 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
177 * index of base_memmap).
179 * The memory map for these Highmem IO Regions can be in legacy or compact
180 * layout, depending on 'compact-highmem' property. With legacy layout, the
181 * PA space for one specific region is always reserved, even if the region
182 * has been disabled or doesn't fit into the PA space. However, the PA space
183 * for the region won't be reserved in these circumstances with compact layout.
185 static MemMapEntry extended_memmap[] = {
186 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
187 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
188 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
189 /* Second PCIe window */
190 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
193 static const int a15irqmap[] = {
196 [VIRT_PCIE] = 3, /* ... to 6 */
198 [VIRT_SECURE_UART] = 8,
200 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
201 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
202 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
203 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
206 static const char *valid_cpus[] = {
208 ARM_CPU_TYPE_NAME("cortex-a7"),
209 ARM_CPU_TYPE_NAME("cortex-a15"),
210 ARM_CPU_TYPE_NAME("cortex-a35"),
211 ARM_CPU_TYPE_NAME("cortex-a55"),
212 ARM_CPU_TYPE_NAME("cortex-a72"),
213 ARM_CPU_TYPE_NAME("cortex-a76"),
214 ARM_CPU_TYPE_NAME("cortex-a710"),
215 ARM_CPU_TYPE_NAME("a64fx"),
216 ARM_CPU_TYPE_NAME("neoverse-n1"),
217 ARM_CPU_TYPE_NAME("neoverse-v1"),
219 ARM_CPU_TYPE_NAME("cortex-a53"),
220 ARM_CPU_TYPE_NAME("cortex-a57"),
221 ARM_CPU_TYPE_NAME("host"),
222 ARM_CPU_TYPE_NAME("max"),
225 static bool cpu_type_valid(const char *cpu)
229 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
230 if (strcmp(cpu, valid_cpus[i]) == 0) {
237 static void create_randomness(MachineState *ms, const char *node)
244 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
247 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
248 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
251 static void create_fdt(VirtMachineState *vms)
253 MachineState *ms = MACHINE(vms);
254 int nb_numa_nodes = ms->numa_state->num_nodes;
255 void *fdt = create_device_tree(&vms->fdt_size);
258 error_report("create_device_tree() failed");
265 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
266 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
267 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
268 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
270 /* /chosen must exist for load_dtb to fill in necessary properties later */
271 qemu_fdt_add_subnode(fdt, "/chosen");
272 if (vms->dtb_randomness) {
273 create_randomness(ms, "/chosen");
277 qemu_fdt_add_subnode(fdt, "/secure-chosen");
278 if (vms->dtb_randomness) {
279 create_randomness(ms, "/secure-chosen");
283 /* Clock node, for the benefit of the UART. The kernel device tree
284 * binding documentation claims the PL011 node clock properties are
285 * optional but in practice if you omit them the kernel refuses to
286 * probe for the device.
288 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
289 qemu_fdt_add_subnode(fdt, "/apb-pclk");
290 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
291 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
292 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
293 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
295 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
297 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
298 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
299 uint32_t *matrix = g_malloc0(size);
302 for (i = 0; i < nb_numa_nodes; i++) {
303 for (j = 0; j < nb_numa_nodes; j++) {
304 idx = (i * nb_numa_nodes + j) * 3;
305 matrix[idx + 0] = cpu_to_be32(i);
306 matrix[idx + 1] = cpu_to_be32(j);
308 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
312 qemu_fdt_add_subnode(fdt, "/distance-map");
313 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
314 "numa-distance-map-v1");
315 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
321 static void fdt_add_timer_nodes(const VirtMachineState *vms)
323 /* On real hardware these interrupts are level-triggered.
324 * On KVM they were edge-triggered before host kernel version 4.4,
325 * and level-triggered afterwards.
326 * On emulated QEMU they are level-triggered.
328 * Getting the DTB info about them wrong is awkward for some
330 * pre-4.8 ignore the DT and leave the interrupt configured
331 * with whatever the GIC reset value (or the bootloader) left it at
332 * 4.8 before rc6 honour the incorrect data by programming it back
333 * into the GIC, causing problems
334 * 4.8rc6 and later ignore the DT and always write "level triggered"
337 * For backwards-compatibility, virt-2.8 and earlier will continue
338 * to say these are edge-triggered, but later machines will report
339 * the correct information.
342 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
343 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
344 MachineState *ms = MACHINE(vms);
346 if (vmc->claim_edge_triggered_timers) {
347 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
350 if (vms->gic_version == VIRT_GIC_VERSION_2) {
351 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
352 GIC_FDT_IRQ_PPI_CPU_WIDTH,
353 (1 << MACHINE(vms)->smp.cpus) - 1);
356 qemu_fdt_add_subnode(ms->fdt, "/timer");
358 armcpu = ARM_CPU(qemu_get_cpu(0));
359 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
360 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
361 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
362 compat, sizeof(compat));
364 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
367 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
368 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
369 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
370 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
371 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
372 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
375 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
379 const MachineState *ms = MACHINE(vms);
380 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
381 int smp_cpus = ms->smp.cpus;
384 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
385 * On ARM v8 64-bit systems value should be set to 2,
386 * that corresponds to the MPIDR_EL1 register size.
387 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
388 * in the system, #address-cells can be set to 1, since
389 * MPIDR_EL1[63:32] bits are not used for CPUs
392 * Here we actually don't know whether our system is 32- or 64-bit one.
393 * The simplest way to go is to examine affinity IDs of all our CPUs. If
394 * at least one of them has Aff3 populated, we set #address-cells to 2.
396 for (cpu = 0; cpu < smp_cpus; cpu++) {
397 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
399 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
405 qemu_fdt_add_subnode(ms->fdt, "/cpus");
406 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
407 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
409 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
410 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
411 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
412 CPUState *cs = CPU(armcpu);
414 qemu_fdt_add_subnode(ms->fdt, nodename);
415 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
416 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
417 armcpu->dtb_compatible);
419 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
420 qemu_fdt_setprop_string(ms->fdt, nodename,
421 "enable-method", "psci");
424 if (addr_cells == 2) {
425 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
426 armcpu->mp_affinity);
428 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
429 armcpu->mp_affinity);
432 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
433 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
434 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
437 if (!vmc->no_cpu_topology) {
438 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
439 qemu_fdt_alloc_phandle(ms->fdt));
445 if (!vmc->no_cpu_topology) {
447 * Add vCPU topology description through fdt node cpu-map.
449 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
450 * In a SMP system, the hierarchy of CPUs can be defined through
451 * four entities that are used to describe the layout of CPUs in
452 * the system: socket/cluster/core/thread.
454 * A socket node represents the boundary of system physical package
455 * and its child nodes must be one or more cluster nodes. A system
456 * can contain several layers of clustering within a single physical
457 * package and cluster nodes can be contained in parent cluster nodes.
459 * Note: currently we only support one layer of clustering within
460 * each physical package.
462 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
464 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
465 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
468 if (ms->smp.threads > 1) {
469 map_path = g_strdup_printf(
470 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
471 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
472 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
473 (cpu / ms->smp.threads) % ms->smp.cores,
474 cpu % ms->smp.threads);
476 map_path = g_strdup_printf(
477 "/cpus/cpu-map/socket%d/cluster%d/core%d",
478 cpu / (ms->smp.clusters * ms->smp.cores),
479 (cpu / ms->smp.cores) % ms->smp.clusters,
480 cpu % ms->smp.cores);
482 qemu_fdt_add_path(ms->fdt, map_path);
483 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
491 static void fdt_add_its_gic_node(VirtMachineState *vms)
494 MachineState *ms = MACHINE(vms);
496 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
497 nodename = g_strdup_printf("/intc/its@%" PRIx64,
498 vms->memmap[VIRT_GIC_ITS].base);
499 qemu_fdt_add_subnode(ms->fdt, nodename);
500 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
502 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
503 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
504 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
505 2, vms->memmap[VIRT_GIC_ITS].base,
506 2, vms->memmap[VIRT_GIC_ITS].size);
507 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
511 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
513 MachineState *ms = MACHINE(vms);
516 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
517 vms->memmap[VIRT_GIC_V2M].base);
518 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
519 qemu_fdt_add_subnode(ms->fdt, nodename);
520 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
521 "arm,gic-v2m-frame");
522 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
523 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
524 2, vms->memmap[VIRT_GIC_V2M].base,
525 2, vms->memmap[VIRT_GIC_V2M].size);
526 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
530 static void fdt_add_gic_node(VirtMachineState *vms)
532 MachineState *ms = MACHINE(vms);
535 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
536 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
538 nodename = g_strdup_printf("/intc@%" PRIx64,
539 vms->memmap[VIRT_GIC_DIST].base);
540 qemu_fdt_add_subnode(ms->fdt, nodename);
541 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
542 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
543 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
544 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
545 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
546 if (vms->gic_version != VIRT_GIC_VERSION_2) {
547 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
549 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
552 qemu_fdt_setprop_cell(ms->fdt, nodename,
553 "#redistributor-regions", nb_redist_regions);
555 if (nb_redist_regions == 1) {
556 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
557 2, vms->memmap[VIRT_GIC_DIST].base,
558 2, vms->memmap[VIRT_GIC_DIST].size,
559 2, vms->memmap[VIRT_GIC_REDIST].base,
560 2, vms->memmap[VIRT_GIC_REDIST].size);
562 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
563 2, vms->memmap[VIRT_GIC_DIST].base,
564 2, vms->memmap[VIRT_GIC_DIST].size,
565 2, vms->memmap[VIRT_GIC_REDIST].base,
566 2, vms->memmap[VIRT_GIC_REDIST].size,
567 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
568 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
572 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
573 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
574 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
577 /* 'cortex-a15-gic' means 'GIC v2' */
578 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
579 "arm,cortex-a15-gic");
581 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
582 2, vms->memmap[VIRT_GIC_DIST].base,
583 2, vms->memmap[VIRT_GIC_DIST].size,
584 2, vms->memmap[VIRT_GIC_CPU].base,
585 2, vms->memmap[VIRT_GIC_CPU].size);
587 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
588 2, vms->memmap[VIRT_GIC_DIST].base,
589 2, vms->memmap[VIRT_GIC_DIST].size,
590 2, vms->memmap[VIRT_GIC_CPU].base,
591 2, vms->memmap[VIRT_GIC_CPU].size,
592 2, vms->memmap[VIRT_GIC_HYP].base,
593 2, vms->memmap[VIRT_GIC_HYP].size,
594 2, vms->memmap[VIRT_GIC_VCPU].base,
595 2, vms->memmap[VIRT_GIC_VCPU].size);
596 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
597 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
598 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
602 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
606 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
608 ARMCPU *armcpu = ARM_CPU(first_cpu);
609 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
610 MachineState *ms = MACHINE(vms);
612 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
613 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
617 if (vms->gic_version == VIRT_GIC_VERSION_2) {
618 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
619 GIC_FDT_IRQ_PPI_CPU_WIDTH,
620 (1 << MACHINE(vms)->smp.cpus) - 1);
623 qemu_fdt_add_subnode(ms->fdt, "/pmu");
624 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
625 const char compat[] = "arm,armv8-pmuv3";
626 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
627 compat, sizeof(compat));
628 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
629 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
633 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
636 MachineState *ms = MACHINE(vms);
637 int irq = vms->irqmap[VIRT_ACPI_GED];
638 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
641 event |= ACPI_GED_MEM_HOTPLUG_EVT;
644 if (ms->nvdimms_state->is_enabled) {
645 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
648 dev = qdev_new(TYPE_ACPI_GED);
649 qdev_prop_set_uint32(dev, "ged-event", event);
651 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
652 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
653 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
655 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
660 static void create_its(VirtMachineState *vms)
662 const char *itsclass = its_class_name();
665 if (!strcmp(itsclass, "arm-gicv3-its")) {
672 /* Do nothing if not supported */
676 dev = qdev_new(itsclass);
678 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
680 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
681 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
683 fdt_add_its_gic_node(vms);
684 vms->msi_controller = VIRT_MSI_CTRL_ITS;
687 static void create_v2m(VirtMachineState *vms)
690 int irq = vms->irqmap[VIRT_GIC_V2M];
693 dev = qdev_new("arm-gicv2m");
694 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
695 qdev_prop_set_uint32(dev, "base-spi", irq);
696 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
697 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
699 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
700 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
701 qdev_get_gpio_in(vms->gic, irq + i));
704 fdt_add_v2m_gic_node(vms);
705 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
708 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
710 MachineState *ms = MACHINE(vms);
711 /* We create a standalone GIC */
712 SysBusDevice *gicbusdev;
715 unsigned int smp_cpus = ms->smp.cpus;
716 uint32_t nb_redist_regions = 0;
719 if (vms->gic_version == VIRT_GIC_VERSION_2) {
720 gictype = gic_class_name();
722 gictype = gicv3_class_name();
725 switch (vms->gic_version) {
726 case VIRT_GIC_VERSION_2:
729 case VIRT_GIC_VERSION_3:
732 case VIRT_GIC_VERSION_4:
736 g_assert_not_reached();
738 vms->gic = qdev_new(gictype);
739 qdev_prop_set_uint32(vms->gic, "revision", revision);
740 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
741 /* Note that the num-irq property counts both internal and external
742 * interrupts; there are always 32 of the former (mandated by GIC spec).
744 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
745 if (!kvm_irqchip_in_kernel()) {
746 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
749 if (vms->gic_version != VIRT_GIC_VERSION_2) {
750 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
751 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
753 nb_redist_regions = virt_gicv3_redist_region_count(vms);
755 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
757 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
759 if (!kvm_irqchip_in_kernel()) {
761 object_property_set_link(OBJECT(vms->gic), "sysmem",
762 OBJECT(mem), &error_fatal);
763 qdev_prop_set_bit(vms->gic, "has-lpi", true);
767 if (nb_redist_regions == 2) {
768 uint32_t redist1_capacity =
769 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
771 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
772 MIN(smp_cpus - redist0_count, redist1_capacity));
775 if (!kvm_irqchip_in_kernel()) {
776 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
780 gicbusdev = SYS_BUS_DEVICE(vms->gic);
781 sysbus_realize_and_unref(gicbusdev, &error_fatal);
782 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
783 if (vms->gic_version != VIRT_GIC_VERSION_2) {
784 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
785 if (nb_redist_regions == 2) {
786 sysbus_mmio_map(gicbusdev, 2,
787 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
790 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
792 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
793 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
797 /* Wire the outputs from each CPU's generic timer and the GICv3
798 * maintenance interrupt signal to the appropriate GIC PPI inputs,
799 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
801 for (i = 0; i < smp_cpus; i++) {
802 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
803 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
805 /* Mapping from the output timer irq lines from the CPU to the
806 * GIC PPI inputs we use for the virt board.
808 const int timer_irq[] = {
809 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
810 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
811 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
812 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
815 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
816 qdev_connect_gpio_out(cpudev, irq,
817 qdev_get_gpio_in(vms->gic,
818 ppibase + timer_irq[irq]));
821 if (vms->gic_version != VIRT_GIC_VERSION_2) {
822 qemu_irq irq = qdev_get_gpio_in(vms->gic,
823 ppibase + ARCH_GIC_MAINT_IRQ);
824 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
826 } else if (vms->virt) {
827 qemu_irq irq = qdev_get_gpio_in(vms->gic,
828 ppibase + ARCH_GIC_MAINT_IRQ);
829 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
832 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
833 qdev_get_gpio_in(vms->gic, ppibase
836 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
837 sysbus_connect_irq(gicbusdev, i + smp_cpus,
838 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
839 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
840 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
841 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
842 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
845 fdt_add_gic_node(vms);
847 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
849 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
854 static void create_uart(const VirtMachineState *vms, int uart,
855 MemoryRegion *mem, Chardev *chr)
858 hwaddr base = vms->memmap[uart].base;
859 hwaddr size = vms->memmap[uart].size;
860 int irq = vms->irqmap[uart];
861 const char compat[] = "arm,pl011\0arm,primecell";
862 const char clocknames[] = "uartclk\0apb_pclk";
863 DeviceState *dev = qdev_new(TYPE_PL011);
864 SysBusDevice *s = SYS_BUS_DEVICE(dev);
865 MachineState *ms = MACHINE(vms);
867 qdev_prop_set_chr(dev, "chardev", chr);
868 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
869 memory_region_add_subregion(mem, base,
870 sysbus_mmio_get_region(s, 0));
871 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
873 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
874 qemu_fdt_add_subnode(ms->fdt, nodename);
875 /* Note that we can't use setprop_string because of the embedded NUL */
876 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
877 compat, sizeof(compat));
878 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
880 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
881 GIC_FDT_IRQ_TYPE_SPI, irq,
882 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
883 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
884 vms->clock_phandle, vms->clock_phandle);
885 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
886 clocknames, sizeof(clocknames));
888 if (uart == VIRT_UART) {
889 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
891 /* Mark as not usable by the normal world */
892 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
893 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
895 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
902 static void create_rtc(const VirtMachineState *vms)
905 hwaddr base = vms->memmap[VIRT_RTC].base;
906 hwaddr size = vms->memmap[VIRT_RTC].size;
907 int irq = vms->irqmap[VIRT_RTC];
908 const char compat[] = "arm,pl031\0arm,primecell";
909 MachineState *ms = MACHINE(vms);
911 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
913 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
914 qemu_fdt_add_subnode(ms->fdt, nodename);
915 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
916 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
918 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
919 GIC_FDT_IRQ_TYPE_SPI, irq,
920 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
921 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
922 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
926 static DeviceState *gpio_key_dev;
927 static void virt_powerdown_req(Notifier *n, void *opaque)
929 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
932 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
934 /* use gpio Pin 3 for power button event */
935 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
939 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
942 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
943 qdev_get_gpio_in(pl061_dev, 3));
945 qemu_fdt_add_subnode(fdt, "/gpio-keys");
946 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
948 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
949 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
950 "label", "GPIO Key Poweroff");
951 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
953 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
954 "gpios", phandle, 3, 0);
957 #define SECURE_GPIO_POWEROFF 0
958 #define SECURE_GPIO_RESET 1
960 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
963 DeviceState *gpio_pwr_dev;
966 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
968 /* connect secure pl061 to gpio-pwr */
969 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
970 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
971 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
972 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
974 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
975 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
977 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
978 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
979 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
980 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
983 qemu_fdt_add_subnode(fdt, "/gpio-restart");
984 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
986 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
987 "gpios", phandle, SECURE_GPIO_RESET, 0);
988 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
989 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
993 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
997 DeviceState *pl061_dev;
998 hwaddr base = vms->memmap[gpio].base;
999 hwaddr size = vms->memmap[gpio].size;
1000 int irq = vms->irqmap[gpio];
1001 const char compat[] = "arm,pl061\0arm,primecell";
1003 MachineState *ms = MACHINE(vms);
1005 pl061_dev = qdev_new("pl061");
1006 /* Pull lines down to 0 if not driven by the PL061 */
1007 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
1008 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
1009 s = SYS_BUS_DEVICE(pl061_dev);
1010 sysbus_realize_and_unref(s, &error_fatal);
1011 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1012 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1014 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1015 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1016 qemu_fdt_add_subnode(ms->fdt, nodename);
1017 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1019 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1020 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1021 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1022 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1023 GIC_FDT_IRQ_TYPE_SPI, irq,
1024 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1025 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1026 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1027 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1029 if (gpio != VIRT_GPIO) {
1030 /* Mark as not usable by the normal world */
1031 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1032 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1036 /* Child gpio devices */
1037 if (gpio == VIRT_GPIO) {
1038 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1040 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1044 static void create_virtio_devices(const VirtMachineState *vms)
1047 hwaddr size = vms->memmap[VIRT_MMIO].size;
1048 MachineState *ms = MACHINE(vms);
1050 /* We create the transports in forwards order. Since qbus_realize()
1051 * prepends (not appends) new child buses, the incrementing loop below will
1052 * create a list of virtio-mmio buses with decreasing base addresses.
1054 * When a -device option is processed from the command line,
1055 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1056 * order. The upshot is that -device options in increasing command line
1057 * order are mapped to virtio-mmio buses with decreasing base addresses.
1059 * When this code was originally written, that arrangement ensured that the
1060 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1061 * the first -device on the command line. (The end-to-end order is a
1062 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1063 * guest kernel's name-to-address assignment strategy.)
1065 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1066 * the message, if not necessarily the code, of commit 70161ff336.
1067 * Therefore the loop now establishes the inverse of the original intent.
1069 * Unfortunately, we can't counteract the kernel change by reversing the
1070 * loop; it would break existing command lines.
1072 * In any case, the kernel makes no guarantee about the stability of
1073 * enumeration order of virtio devices (as demonstrated by it changing
1074 * between kernel versions). For reliable and stable identification
1075 * of disks users must use UUIDs or similar mechanisms.
1077 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1078 int irq = vms->irqmap[VIRT_MMIO] + i;
1079 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1081 sysbus_create_simple("virtio-mmio", base,
1082 qdev_get_gpio_in(vms->gic, irq));
1085 /* We add dtb nodes in reverse order so that they appear in the finished
1086 * device tree lowest address first.
1088 * Note that this mapping is independent of the loop above. The previous
1089 * loop influences virtio device to virtio transport assignment, whereas
1090 * this loop controls how virtio transports are laid out in the dtb.
1092 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1094 int irq = vms->irqmap[VIRT_MMIO] + i;
1095 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1097 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1098 qemu_fdt_add_subnode(ms->fdt, nodename);
1099 qemu_fdt_setprop_string(ms->fdt, nodename,
1100 "compatible", "virtio,mmio");
1101 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1103 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1104 GIC_FDT_IRQ_TYPE_SPI, irq,
1105 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1106 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1111 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1113 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1115 const char *alias_prop_name)
1118 * Create a single flash device. We use the same parameters as
1119 * the flash devices on the Versatile Express board.
1121 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1123 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1124 qdev_prop_set_uint8(dev, "width", 4);
1125 qdev_prop_set_uint8(dev, "device-width", 2);
1126 qdev_prop_set_bit(dev, "big-endian", false);
1127 qdev_prop_set_uint16(dev, "id0", 0x89);
1128 qdev_prop_set_uint16(dev, "id1", 0x18);
1129 qdev_prop_set_uint16(dev, "id2", 0x00);
1130 qdev_prop_set_uint16(dev, "id3", 0x00);
1131 qdev_prop_set_string(dev, "name", name);
1132 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1133 object_property_add_alias(OBJECT(vms), alias_prop_name,
1134 OBJECT(dev), "drive");
1135 return PFLASH_CFI01(dev);
1138 static void virt_flash_create(VirtMachineState *vms)
1140 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1141 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1144 static void virt_flash_map1(PFlashCFI01 *flash,
1145 hwaddr base, hwaddr size,
1146 MemoryRegion *sysmem)
1148 DeviceState *dev = DEVICE(flash);
1150 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1151 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1152 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1153 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1155 memory_region_add_subregion(sysmem, base,
1156 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1160 static void virt_flash_map(VirtMachineState *vms,
1161 MemoryRegion *sysmem,
1162 MemoryRegion *secure_sysmem)
1165 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1166 * sysmem is the system memory space. secure_sysmem is the secure view
1167 * of the system, and the first flash device should be made visible only
1168 * there. The second flash device is visible to both secure and nonsecure.
1169 * If sysmem == secure_sysmem this means there is no separate Secure
1170 * address space and both flash devices are generally visible.
1172 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1173 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1175 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1177 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1181 static void virt_flash_fdt(VirtMachineState *vms,
1182 MemoryRegion *sysmem,
1183 MemoryRegion *secure_sysmem)
1185 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1186 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1187 MachineState *ms = MACHINE(vms);
1190 if (sysmem == secure_sysmem) {
1191 /* Report both flash devices as a single node in the DT */
1192 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1193 qemu_fdt_add_subnode(ms->fdt, nodename);
1194 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1195 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1196 2, flashbase, 2, flashsize,
1197 2, flashbase + flashsize, 2, flashsize);
1198 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1202 * Report the devices as separate nodes so we can mark one as
1203 * only visible to the secure world.
1205 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1206 qemu_fdt_add_subnode(ms->fdt, nodename);
1207 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1208 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1209 2, flashbase, 2, flashsize);
1210 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1211 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1212 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1215 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1216 qemu_fdt_add_subnode(ms->fdt, nodename);
1217 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1218 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1219 2, flashbase + flashsize, 2, flashsize);
1220 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1225 static bool virt_firmware_init(VirtMachineState *vms,
1226 MemoryRegion *sysmem,
1227 MemoryRegion *secure_sysmem)
1230 const char *bios_name;
1231 BlockBackend *pflash_blk0;
1233 /* Map legacy -drive if=pflash to machine properties */
1234 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1235 pflash_cfi01_legacy_drive(vms->flash[i],
1236 drive_get(IF_PFLASH, 0, i));
1239 virt_flash_map(vms, sysmem, secure_sysmem);
1241 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1243 bios_name = MACHINE(vms)->firmware;
1250 error_report("The contents of the first flash device may be "
1251 "specified with -bios or with -drive if=pflash... "
1252 "but you cannot use both options at once");
1256 /* Fall back to -bios */
1258 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1260 error_report("Could not find ROM image '%s'", bios_name);
1263 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1264 image_size = load_image_mr(fname, mr);
1266 if (image_size < 0) {
1267 error_report("Could not load ROM image '%s'", bios_name);
1272 return pflash_blk0 || bios_name;
1275 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1277 MachineState *ms = MACHINE(vms);
1278 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1279 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1283 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1284 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1286 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1287 qemu_fdt_add_subnode(ms->fdt, nodename);
1288 qemu_fdt_setprop_string(ms->fdt, nodename,
1289 "compatible", "qemu,fw-cfg-mmio");
1290 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1292 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1297 static void create_pcie_irq_map(const MachineState *ms,
1298 uint32_t gic_phandle,
1299 int first_irq, const char *nodename)
1302 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1303 uint32_t *irq_map = full_irq_map;
1305 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1306 for (pin = 0; pin < 4; pin++) {
1307 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1308 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1309 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1313 devfn << 8, 0, 0, /* devfn */
1314 pin + 1, /* PCI pin */
1315 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1317 /* Convert map to big endian */
1318 for (i = 0; i < 10; i++) {
1319 irq_map[i] = cpu_to_be32(map[i]);
1325 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1326 full_irq_map, sizeof(full_irq_map));
1328 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1329 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1334 static void create_smmu(const VirtMachineState *vms,
1338 const char compat[] = "arm,smmu-v3";
1339 int irq = vms->irqmap[VIRT_SMMU];
1341 hwaddr base = vms->memmap[VIRT_SMMU].base;
1342 hwaddr size = vms->memmap[VIRT_SMMU].size;
1343 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1345 MachineState *ms = MACHINE(vms);
1347 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1351 dev = qdev_new(TYPE_ARM_SMMUV3);
1353 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1355 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1356 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1357 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1358 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1359 qdev_get_gpio_in(vms->gic, irq + i));
1362 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1363 qemu_fdt_add_subnode(ms->fdt, node);
1364 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1365 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1367 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1368 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1369 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1370 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1371 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1373 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1376 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1378 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1380 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1384 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1386 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1387 uint16_t bdf = vms->virtio_iommu_bdf;
1388 MachineState *ms = MACHINE(vms);
1391 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1393 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1394 PCI_SLOT(bdf), PCI_FUNC(bdf));
1395 qemu_fdt_add_subnode(ms->fdt, node);
1396 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1397 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1398 1, bdf << 8, 1, 0, 1, 0,
1401 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1402 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1405 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1406 0x0, vms->iommu_phandle, 0x0, bdf,
1407 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1410 static void create_pcie(VirtMachineState *vms)
1412 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1413 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1414 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1415 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1416 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1417 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1418 hwaddr base_ecam, size_ecam;
1419 hwaddr base = base_mmio;
1421 int irq = vms->irqmap[VIRT_PCIE];
1422 MemoryRegion *mmio_alias;
1423 MemoryRegion *mmio_reg;
1424 MemoryRegion *ecam_alias;
1425 MemoryRegion *ecam_reg;
1430 MachineState *ms = MACHINE(vms);
1431 MachineClass *mc = MACHINE_GET_CLASS(ms);
1433 dev = qdev_new(TYPE_GPEX_HOST);
1434 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1436 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1437 base_ecam = vms->memmap[ecam_id].base;
1438 size_ecam = vms->memmap[ecam_id].size;
1439 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1440 /* Map only the first size_ecam bytes of ECAM space */
1441 ecam_alias = g_new0(MemoryRegion, 1);
1442 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1443 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1444 ecam_reg, 0, size_ecam);
1445 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1447 /* Map the MMIO window into system address space so as to expose
1448 * the section of PCI MMIO space which starts at the same base address
1449 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1452 mmio_alias = g_new0(MemoryRegion, 1);
1453 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1454 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1455 mmio_reg, base_mmio, size_mmio);
1456 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1458 if (vms->highmem_mmio) {
1459 /* Map high MMIO space */
1460 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1462 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1463 mmio_reg, base_mmio_high, size_mmio_high);
1464 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1468 /* Map IO port space */
1469 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1471 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1472 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1473 qdev_get_gpio_in(vms->gic, irq + i));
1474 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1477 pci = PCI_HOST_BRIDGE(dev);
1478 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1479 vms->bus = pci->bus;
1481 for (i = 0; i < nb_nics; i++) {
1482 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL);
1486 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1487 qemu_fdt_add_subnode(ms->fdt, nodename);
1488 qemu_fdt_setprop_string(ms->fdt, nodename,
1489 "compatible", "pci-host-ecam-generic");
1490 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1491 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1492 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1493 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1494 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1496 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1498 if (vms->msi_phandle) {
1499 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1500 0, vms->msi_phandle, 0, 0x10000);
1503 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1504 2, base_ecam, 2, size_ecam);
1506 if (vms->highmem_mmio) {
1507 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1508 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1509 2, base_pio, 2, size_pio,
1510 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1511 2, base_mmio, 2, size_mmio,
1512 1, FDT_PCI_RANGE_MMIO_64BIT,
1514 2, base_mmio_high, 2, size_mmio_high);
1516 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1517 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1518 2, base_pio, 2, size_pio,
1519 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1520 2, base_mmio, 2, size_mmio);
1523 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1524 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1527 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1529 switch (vms->iommu) {
1530 case VIRT_IOMMU_SMMUV3:
1531 create_smmu(vms, vms->bus);
1532 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1533 0x0, vms->iommu_phandle, 0x0, 0x10000);
1536 g_assert_not_reached();
1541 static void create_platform_bus(VirtMachineState *vms)
1546 MemoryRegion *sysmem = get_system_memory();
1548 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1549 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1550 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1551 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1552 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1553 vms->platform_bus_dev = dev;
1555 s = SYS_BUS_DEVICE(dev);
1556 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1557 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1558 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1561 memory_region_add_subregion(sysmem,
1562 vms->memmap[VIRT_PLATFORM_BUS].base,
1563 sysbus_mmio_get_region(s, 0));
1566 static void create_tag_ram(MemoryRegion *tag_sysmem,
1567 hwaddr base, hwaddr size,
1570 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1572 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1573 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1576 static void create_secure_ram(VirtMachineState *vms,
1577 MemoryRegion *secure_sysmem,
1578 MemoryRegion *secure_tag_sysmem)
1580 MemoryRegion *secram = g_new(MemoryRegion, 1);
1582 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1583 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1584 MachineState *ms = MACHINE(vms);
1586 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1588 memory_region_add_subregion(secure_sysmem, base, secram);
1590 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1591 qemu_fdt_add_subnode(ms->fdt, nodename);
1592 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1593 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1594 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1595 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1597 if (secure_tag_sysmem) {
1598 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1604 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1606 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1608 MachineState *ms = MACHINE(board);
1611 *fdt_size = board->fdt_size;
1615 static void virt_build_smbios(VirtMachineState *vms)
1617 MachineClass *mc = MACHINE_GET_CLASS(vms);
1618 MachineState *ms = MACHINE(vms);
1619 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1620 uint8_t *smbios_tables, *smbios_anchor;
1621 size_t smbios_tables_len, smbios_anchor_len;
1622 struct smbios_phys_mem_area mem_array;
1623 const char *product = "QEMU Virtual Machine";
1625 if (kvm_enabled()) {
1626 product = "KVM Virtual Machine";
1629 smbios_set_defaults("QEMU", product,
1630 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1631 true, SMBIOS_ENTRY_POINT_TYPE_64);
1633 /* build the array of physical mem area from base_memmap */
1634 mem_array.address = vms->memmap[VIRT_MEM].base;
1635 mem_array.length = ms->ram_size;
1637 smbios_get_tables(ms, &mem_array, 1,
1638 &smbios_tables, &smbios_tables_len,
1639 &smbios_anchor, &smbios_anchor_len,
1642 if (smbios_anchor) {
1643 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1644 smbios_tables, smbios_tables_len);
1645 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1646 smbios_anchor, smbios_anchor_len);
1651 void virt_machine_done(Notifier *notifier, void *data)
1653 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1655 MachineState *ms = MACHINE(vms);
1656 ARMCPU *cpu = ARM_CPU(first_cpu);
1657 struct arm_boot_info *info = &vms->bootinfo;
1658 AddressSpace *as = arm_boot_address_space(cpu, info);
1661 * If the user provided a dtb, we assume the dynamic sysbus nodes
1662 * already are integrated there. This corresponds to a use case where
1663 * the dynamic sysbus nodes are complex and their generation is not yet
1664 * supported. In that case the user can take charge of the guest dt
1665 * while qemu takes charge of the qom stuff.
1667 if (info->dtb_filename == NULL) {
1668 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1669 vms->memmap[VIRT_PLATFORM_BUS].base,
1670 vms->memmap[VIRT_PLATFORM_BUS].size,
1671 vms->irqmap[VIRT_PLATFORM_BUS]);
1673 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1677 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1679 virt_acpi_setup(vms);
1680 virt_build_smbios(vms);
1683 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1685 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1686 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1688 if (!vmc->disallow_affinity_adjustment) {
1689 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1690 * GIC's target-list limitations. 32-bit KVM hosts currently
1691 * always create clusters of 4 CPUs, but that is expected to
1692 * change when they gain support for gicv3. When KVM is enabled
1693 * it will override the changes we make here, therefore our
1694 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1695 * and to improve SGI efficiency.
1697 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1698 clustersz = GIC_TARGETLIST_BITS;
1700 clustersz = GICV3_TARGETLIST_BITS;
1703 return arm_cpu_mp_affinity(idx, clustersz);
1706 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
1709 bool *enabled_array[] = {
1710 &vms->highmem_redists,
1715 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1716 ARRAY_SIZE(enabled_array));
1717 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1719 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1722 static void virt_set_high_memmap(VirtMachineState *vms,
1723 hwaddr base, int pa_bits)
1725 hwaddr region_base, region_size;
1726 bool *region_enabled, fits;
1729 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1730 region_enabled = virt_get_high_memmap_enabled(vms, i);
1731 region_base = ROUND_UP(base, extended_memmap[i].size);
1732 region_size = extended_memmap[i].size;
1734 vms->memmap[i].base = region_base;
1735 vms->memmap[i].size = region_size;
1738 * Check each device to see if it fits in the PA space,
1739 * moving highest_gpa as we go. For compatibility, move
1740 * highest_gpa for disabled fitting devices as well, if
1741 * the compact layout has been disabled.
1743 * For each device that doesn't fit, disable it.
1745 fits = (region_base + region_size) <= BIT_ULL(pa_bits);
1746 *region_enabled &= fits;
1747 if (vms->highmem_compact && !*region_enabled) {
1751 base = region_base + region_size;
1753 vms->highest_gpa = base - 1;
1758 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1760 MachineState *ms = MACHINE(vms);
1761 hwaddr base, device_memory_base, device_memory_size, memtop;
1764 vms->memmap = extended_memmap;
1766 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1767 vms->memmap[i] = base_memmap[i];
1770 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1771 error_report("unsupported number of memory slots: %"PRIu64,
1777 * !highmem is exactly the same as limiting the PA space to 32bit,
1778 * irrespective of the underlying capabilities of the HW.
1780 if (!vms->highmem) {
1785 * We compute the base of the high IO region depending on the
1786 * amount of initial and device memory. The device memory start/size
1787 * is aligned on 1GiB. We never put the high IO region below 256GiB
1788 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1789 * The device region size assumes 1GiB page max alignment per slot.
1791 device_memory_base =
1792 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1793 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1795 /* Base address of the high IO region */
1796 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1797 if (memtop > BIT_ULL(pa_bits)) {
1798 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1799 pa_bits, memtop - BIT_ULL(pa_bits));
1802 if (base < device_memory_base) {
1803 error_report("maxmem/slots too huge");
1806 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1807 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1810 /* We know for sure that at least the memory fits in the PA space */
1811 vms->highest_gpa = memtop - 1;
1813 virt_set_high_memmap(vms, base, pa_bits);
1815 if (device_memory_size > 0) {
1816 machine_memory_devices_init(ms, device_memory_base, device_memory_size);
1820 static VirtGICType finalize_gic_version_do(const char *accel_name,
1821 VirtGICType gic_version,
1823 unsigned int max_cpus)
1825 /* Convert host/max/nosel to GIC version number */
1826 switch (gic_version) {
1827 case VIRT_GIC_VERSION_HOST:
1828 if (!kvm_enabled()) {
1829 error_report("gic-version=host requires KVM");
1833 /* For KVM, gic-version=host means gic-version=max */
1834 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
1835 gics_supported, max_cpus);
1836 case VIRT_GIC_VERSION_MAX:
1837 if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
1838 gic_version = VIRT_GIC_VERSION_4;
1839 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1840 gic_version = VIRT_GIC_VERSION_3;
1842 gic_version = VIRT_GIC_VERSION_2;
1845 case VIRT_GIC_VERSION_NOSEL:
1846 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
1847 max_cpus <= GIC_NCPU) {
1848 gic_version = VIRT_GIC_VERSION_2;
1849 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1851 * in case the host does not support v2 emulation or
1852 * the end-user requested more than 8 VCPUs we now default
1853 * to v3. In any case defaulting to v2 would be broken.
1855 gic_version = VIRT_GIC_VERSION_3;
1856 } else if (max_cpus > GIC_NCPU) {
1857 error_report("%s only supports GICv2 emulation but more than 8 "
1858 "vcpus are requested", accel_name);
1862 case VIRT_GIC_VERSION_2:
1863 case VIRT_GIC_VERSION_3:
1864 case VIRT_GIC_VERSION_4:
1868 /* Check chosen version is effectively supported */
1869 switch (gic_version) {
1870 case VIRT_GIC_VERSION_2:
1871 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
1872 error_report("%s does not support GICv2 emulation", accel_name);
1876 case VIRT_GIC_VERSION_3:
1877 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
1878 error_report("%s does not support GICv3 emulation", accel_name);
1882 case VIRT_GIC_VERSION_4:
1883 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
1884 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1890 error_report("logic error in finalize_gic_version");
1899 * finalize_gic_version - Determines the final gic_version
1900 * according to the gic-version property
1902 * Default GIC type is v2
1904 static void finalize_gic_version(VirtMachineState *vms)
1906 const char *accel_name = current_accel_name();
1907 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1908 int gics_supported = 0;
1910 /* Determine which GIC versions the current environment supports */
1911 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1912 int probe_bitmap = kvm_arm_vgic_probe();
1914 if (!probe_bitmap) {
1915 error_report("Unable to determine GIC version supported by host");
1919 if (probe_bitmap & KVM_ARM_VGIC_V2) {
1920 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1922 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1923 gics_supported |= VIRT_GIC_VERSION_3_MASK;
1925 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1926 /* KVM w/o kernel irqchip can only deal with GICv2 */
1927 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1928 accel_name = "KVM with kernel-irqchip=off";
1929 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
1930 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1931 if (module_object_class_by_name("arm-gicv3")) {
1932 gics_supported |= VIRT_GIC_VERSION_3_MASK;
1934 /* GICv4 only makes sense if CPU has EL2 */
1935 gics_supported |= VIRT_GIC_VERSION_4_MASK;
1939 error_report("Unsupported accelerator, can not determine GIC support");
1944 * Then convert helpers like host/max to concrete GIC versions and ensure
1945 * the desired version is supported
1947 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
1948 gics_supported, max_cpus);
1952 * virt_cpu_post_init() must be called after the CPUs have
1953 * been realized and the GIC has been created.
1955 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1957 int max_cpus = MACHINE(vms)->smp.max_cpus;
1958 bool aarch64, pmu, steal_time;
1961 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1962 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1963 steal_time = object_property_get_bool(OBJECT(first_cpu),
1964 "kvm-steal-time", NULL);
1966 if (kvm_enabled()) {
1967 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1968 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1971 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1972 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1974 /* The memory region size must be a multiple of host page size. */
1975 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1977 if (pvtime_size > pvtime_reg_size) {
1978 error_report("pvtime requires a %" HWADDR_PRId
1979 " byte memory region for %d CPUs,"
1980 " but only %" HWADDR_PRId " has been reserved",
1981 pvtime_size, max_cpus, pvtime_reg_size);
1985 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1986 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1991 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1992 if (kvm_irqchip_in_kernel()) {
1993 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1995 kvm_arm_pmu_init(cpu);
1998 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1999 cpu->cpu_index * PVTIME_SIZE_PER_CPU);
2003 if (aarch64 && vms->highmem) {
2004 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2005 int pamax = arm_pamax(ARM_CPU(first_cpu));
2007 if (pamax < requested_pa_size) {
2008 error_report("VCPU supports less PA bits (%d) than "
2009 "requested by the memory map (%d)",
2010 pamax, requested_pa_size);
2017 static void machvirt_init(MachineState *machine)
2019 VirtMachineState *vms = VIRT_MACHINE(machine);
2020 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2021 MachineClass *mc = MACHINE_GET_CLASS(machine);
2022 const CPUArchIdList *possible_cpus;
2023 MemoryRegion *sysmem = get_system_memory();
2024 MemoryRegion *secure_sysmem = NULL;
2025 MemoryRegion *tag_sysmem = NULL;
2026 MemoryRegion *secure_tag_sysmem = NULL;
2027 int n, virt_max_cpus;
2028 bool firmware_loaded;
2029 bool aarch64 = true;
2030 bool has_ged = !vmc->no_ged;
2031 unsigned int smp_cpus = machine->smp.cpus;
2032 unsigned int max_cpus = machine->smp.max_cpus;
2034 if (!cpu_type_valid(machine->cpu_type)) {
2035 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
2039 possible_cpus = mc->possible_cpu_arch_ids(machine);
2042 * In accelerated mode, the memory map is computed earlier in kvm_type()
2043 * to create a VM with the right number of IPA bits.
2051 * Instantiate a temporary CPU object to find out about what
2052 * we are about to deal with. Once this is done, get rid of
2055 cpuobj = object_new(possible_cpus->cpus[0].type);
2056 armcpu = ARM_CPU(cpuobj);
2058 pa_bits = arm_pamax(armcpu);
2060 object_unref(cpuobj);
2062 virt_set_memmap(vms, pa_bits);
2065 /* We can probe only here because during property set
2066 * KVM is not available yet
2068 finalize_gic_version(vms);
2072 * The Secure view of the world is the same as the NonSecure,
2073 * but with a few extra devices. Create it as a container region
2074 * containing the system memory at low priority; any secure-only
2075 * devices go in at higher priority and take precedence.
2077 secure_sysmem = g_new(MemoryRegion, 1);
2078 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2080 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2083 firmware_loaded = virt_firmware_init(vms, sysmem,
2084 secure_sysmem ?: sysmem);
2086 /* If we have an EL3 boot ROM then the assumption is that it will
2087 * implement PSCI itself, so disable QEMU's internal implementation
2088 * so it doesn't get in the way. Instead of starting secondary
2089 * CPUs in PSCI powerdown state we will start them all running and
2090 * let the boot ROM sort them out.
2091 * The usual case is that we do use QEMU's PSCI implementation;
2092 * if the guest has EL2 then we will use SMC as the conduit,
2093 * and otherwise we will use HVC (for backwards compatibility and
2094 * because if we're using KVM then we must use HVC).
2096 if (vms->secure && firmware_loaded) {
2097 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2098 } else if (vms->virt) {
2099 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2101 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2105 * The maximum number of CPUs depends on the GIC version, or on how
2106 * many redistributors we can fit into the memory map (which in turn
2107 * depends on whether this is a GICv3 or v4).
2109 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2110 virt_max_cpus = GIC_NCPU;
2112 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2113 if (vms->highmem_redists) {
2114 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2118 if (max_cpus > virt_max_cpus) {
2119 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2120 "supported by machine 'mach-virt' (%d)",
2121 max_cpus, virt_max_cpus);
2122 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2123 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2129 if (vms->secure && (kvm_enabled() || hvf_enabled())) {
2130 error_report("mach-virt: %s does not support providing "
2131 "Security extensions (TrustZone) to the guest CPU",
2132 current_accel_name());
2136 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
2137 error_report("mach-virt: %s does not support providing "
2138 "Virtualization extensions to the guest CPU",
2139 current_accel_name());
2143 if (vms->mte && (kvm_enabled() || hvf_enabled())) {
2144 error_report("mach-virt: %s does not support providing "
2145 "MTE to the guest CPU",
2146 current_accel_name());
2152 assert(possible_cpus->len == max_cpus);
2153 for (n = 0; n < possible_cpus->len; n++) {
2157 if (n >= smp_cpus) {
2161 cpuobj = object_new(possible_cpus->cpus[n].type);
2162 object_property_set_int(cpuobj, "mp-affinity",
2163 possible_cpus->cpus[n].arch_id, NULL);
2168 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2171 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2174 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2177 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2178 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2181 if (vmc->kvm_no_adjvtime &&
2182 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2183 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2186 if (vmc->no_kvm_steal_time &&
2187 object_property_find(cpuobj, "kvm-steal-time")) {
2188 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2191 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2192 object_property_set_bool(cpuobj, "pmu", false, NULL);
2195 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2196 object_property_set_bool(cpuobj, "lpa2", false, NULL);
2199 if (object_property_find(cpuobj, "reset-cbar")) {
2200 object_property_set_int(cpuobj, "reset-cbar",
2201 vms->memmap[VIRT_CPUPERIPHS].base,
2205 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2208 object_property_set_link(cpuobj, "secure-memory",
2209 OBJECT(secure_sysmem), &error_abort);
2213 /* Create the memory region only once, but link to all cpus. */
2216 * The property exists only if MemTag is supported.
2217 * If it is, we must allocate the ram to back that up.
2219 if (!object_property_find(cpuobj, "tag-memory")) {
2220 error_report("MTE requested, but not supported "
2221 "by the guest CPU");
2225 tag_sysmem = g_new(MemoryRegion, 1);
2226 memory_region_init(tag_sysmem, OBJECT(machine),
2227 "tag-memory", UINT64_MAX / 32);
2230 secure_tag_sysmem = g_new(MemoryRegion, 1);
2231 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2232 "secure-tag-memory", UINT64_MAX / 32);
2234 /* As with ram, secure-tag takes precedence over tag. */
2235 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2240 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2243 object_property_set_link(cpuobj, "secure-tag-memory",
2244 OBJECT(secure_tag_sysmem),
2249 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2250 object_unref(cpuobj);
2252 fdt_add_timer_nodes(vms);
2253 fdt_add_cpu_nodes(vms);
2255 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2258 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2260 create_gic(vms, sysmem);
2262 virt_cpu_post_init(vms, sysmem);
2264 fdt_add_pmu_nodes(vms);
2266 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2269 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2270 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2274 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2275 machine->ram_size, "mach-virt.tag");
2278 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2284 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2285 vms->acpi_dev = create_acpi_ged(vms);
2287 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2290 if (vms->secure && !vmc->no_secure_gpio) {
2291 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2294 /* connect powerdown request */
2295 vms->powerdown_notifier.notify = virt_powerdown_req;
2296 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2298 /* Create mmio transports, so the user can create virtio backends
2299 * (which will be automatically plugged in to the transports). If
2300 * no backend is created the transport will just sit harmlessly idle.
2302 create_virtio_devices(vms);
2304 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2305 rom_set_fw(vms->fw_cfg);
2307 create_platform_bus(vms);
2309 if (machine->nvdimms_state->is_enabled) {
2310 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2311 .space_id = AML_AS_SYSTEM_MEMORY,
2312 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2313 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2316 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2317 arm_virt_nvdimm_acpi_dsmio,
2318 vms->fw_cfg, OBJECT(vms));
2321 vms->bootinfo.ram_size = machine->ram_size;
2322 vms->bootinfo.board_id = -1;
2323 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2324 vms->bootinfo.get_dtb = machvirt_dtb;
2325 vms->bootinfo.skip_dtb_autoload = true;
2326 vms->bootinfo.firmware_loaded = firmware_loaded;
2327 vms->bootinfo.psci_conduit = vms->psci_conduit;
2328 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2330 vms->machine_done.notify = virt_machine_done;
2331 qemu_add_machine_init_done_notifier(&vms->machine_done);
2334 static bool virt_get_secure(Object *obj, Error **errp)
2336 VirtMachineState *vms = VIRT_MACHINE(obj);
2341 static void virt_set_secure(Object *obj, bool value, Error **errp)
2343 VirtMachineState *vms = VIRT_MACHINE(obj);
2345 vms->secure = value;
2348 static bool virt_get_virt(Object *obj, Error **errp)
2350 VirtMachineState *vms = VIRT_MACHINE(obj);
2355 static void virt_set_virt(Object *obj, bool value, Error **errp)
2357 VirtMachineState *vms = VIRT_MACHINE(obj);
2362 static bool virt_get_highmem(Object *obj, Error **errp)
2364 VirtMachineState *vms = VIRT_MACHINE(obj);
2366 return vms->highmem;
2369 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2371 VirtMachineState *vms = VIRT_MACHINE(obj);
2373 vms->highmem = value;
2376 static bool virt_get_compact_highmem(Object *obj, Error **errp)
2378 VirtMachineState *vms = VIRT_MACHINE(obj);
2380 return vms->highmem_compact;
2383 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
2385 VirtMachineState *vms = VIRT_MACHINE(obj);
2387 vms->highmem_compact = value;
2390 static bool virt_get_highmem_redists(Object *obj, Error **errp)
2392 VirtMachineState *vms = VIRT_MACHINE(obj);
2394 return vms->highmem_redists;
2397 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
2399 VirtMachineState *vms = VIRT_MACHINE(obj);
2401 vms->highmem_redists = value;
2404 static bool virt_get_highmem_ecam(Object *obj, Error **errp)
2406 VirtMachineState *vms = VIRT_MACHINE(obj);
2408 return vms->highmem_ecam;
2411 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
2413 VirtMachineState *vms = VIRT_MACHINE(obj);
2415 vms->highmem_ecam = value;
2418 static bool virt_get_highmem_mmio(Object *obj, Error **errp)
2420 VirtMachineState *vms = VIRT_MACHINE(obj);
2422 return vms->highmem_mmio;
2425 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
2427 VirtMachineState *vms = VIRT_MACHINE(obj);
2429 vms->highmem_mmio = value;
2433 static bool virt_get_its(Object *obj, Error **errp)
2435 VirtMachineState *vms = VIRT_MACHINE(obj);
2440 static void virt_set_its(Object *obj, bool value, Error **errp)
2442 VirtMachineState *vms = VIRT_MACHINE(obj);
2447 static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2449 VirtMachineState *vms = VIRT_MACHINE(obj);
2451 return vms->dtb_randomness;
2454 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2456 VirtMachineState *vms = VIRT_MACHINE(obj);
2458 vms->dtb_randomness = value;
2461 static char *virt_get_oem_id(Object *obj, Error **errp)
2463 VirtMachineState *vms = VIRT_MACHINE(obj);
2465 return g_strdup(vms->oem_id);
2468 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2470 VirtMachineState *vms = VIRT_MACHINE(obj);
2471 size_t len = strlen(value);
2475 "User specified oem-id value is bigger than 6 bytes in size");
2479 strncpy(vms->oem_id, value, 6);
2482 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2484 VirtMachineState *vms = VIRT_MACHINE(obj);
2486 return g_strdup(vms->oem_table_id);
2489 static void virt_set_oem_table_id(Object *obj, const char *value,
2492 VirtMachineState *vms = VIRT_MACHINE(obj);
2493 size_t len = strlen(value);
2497 "User specified oem-table-id value is bigger than 8 bytes in size");
2500 strncpy(vms->oem_table_id, value, 8);
2504 bool virt_is_acpi_enabled(VirtMachineState *vms)
2506 if (vms->acpi == ON_OFF_AUTO_OFF) {
2512 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2513 void *opaque, Error **errp)
2515 VirtMachineState *vms = VIRT_MACHINE(obj);
2516 OnOffAuto acpi = vms->acpi;
2518 visit_type_OnOffAuto(v, name, &acpi, errp);
2521 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2522 void *opaque, Error **errp)
2524 VirtMachineState *vms = VIRT_MACHINE(obj);
2526 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2529 static bool virt_get_ras(Object *obj, Error **errp)
2531 VirtMachineState *vms = VIRT_MACHINE(obj);
2536 static void virt_set_ras(Object *obj, bool value, Error **errp)
2538 VirtMachineState *vms = VIRT_MACHINE(obj);
2543 static bool virt_get_mte(Object *obj, Error **errp)
2545 VirtMachineState *vms = VIRT_MACHINE(obj);
2550 static void virt_set_mte(Object *obj, bool value, Error **errp)
2552 VirtMachineState *vms = VIRT_MACHINE(obj);
2557 static char *virt_get_gic_version(Object *obj, Error **errp)
2559 VirtMachineState *vms = VIRT_MACHINE(obj);
2562 switch (vms->gic_version) {
2563 case VIRT_GIC_VERSION_4:
2566 case VIRT_GIC_VERSION_3:
2573 return g_strdup(val);
2576 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2578 VirtMachineState *vms = VIRT_MACHINE(obj);
2580 if (!strcmp(value, "4")) {
2581 vms->gic_version = VIRT_GIC_VERSION_4;
2582 } else if (!strcmp(value, "3")) {
2583 vms->gic_version = VIRT_GIC_VERSION_3;
2584 } else if (!strcmp(value, "2")) {
2585 vms->gic_version = VIRT_GIC_VERSION_2;
2586 } else if (!strcmp(value, "host")) {
2587 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2588 } else if (!strcmp(value, "max")) {
2589 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2591 error_setg(errp, "Invalid gic-version value");
2592 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2596 static char *virt_get_iommu(Object *obj, Error **errp)
2598 VirtMachineState *vms = VIRT_MACHINE(obj);
2600 switch (vms->iommu) {
2601 case VIRT_IOMMU_NONE:
2602 return g_strdup("none");
2603 case VIRT_IOMMU_SMMUV3:
2604 return g_strdup("smmuv3");
2606 g_assert_not_reached();
2610 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2612 VirtMachineState *vms = VIRT_MACHINE(obj);
2614 if (!strcmp(value, "smmuv3")) {
2615 vms->iommu = VIRT_IOMMU_SMMUV3;
2616 } else if (!strcmp(value, "none")) {
2617 vms->iommu = VIRT_IOMMU_NONE;
2619 error_setg(errp, "Invalid iommu value");
2620 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2624 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2626 VirtMachineState *vms = VIRT_MACHINE(obj);
2628 return vms->default_bus_bypass_iommu;
2631 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2634 VirtMachineState *vms = VIRT_MACHINE(obj);
2636 vms->default_bus_bypass_iommu = value;
2639 static CpuInstanceProperties
2640 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2642 MachineClass *mc = MACHINE_GET_CLASS(ms);
2643 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2645 assert(cpu_index < possible_cpus->len);
2646 return possible_cpus->cpus[cpu_index].props;
2649 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2651 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2653 return socket_id % ms->numa_state->num_nodes;
2656 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2659 unsigned int max_cpus = ms->smp.max_cpus;
2660 VirtMachineState *vms = VIRT_MACHINE(ms);
2661 MachineClass *mc = MACHINE_GET_CLASS(vms);
2663 if (ms->possible_cpus) {
2664 assert(ms->possible_cpus->len == max_cpus);
2665 return ms->possible_cpus;
2668 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2669 sizeof(CPUArchId) * max_cpus);
2670 ms->possible_cpus->len = max_cpus;
2671 for (n = 0; n < ms->possible_cpus->len; n++) {
2672 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2673 ms->possible_cpus->cpus[n].arch_id =
2674 virt_cpu_mp_affinity(vms, n);
2676 assert(!mc->smp_props.dies_supported);
2677 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2678 ms->possible_cpus->cpus[n].props.socket_id =
2679 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2680 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2681 ms->possible_cpus->cpus[n].props.cluster_id =
2682 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2683 ms->possible_cpus->cpus[n].props.has_core_id = true;
2684 ms->possible_cpus->cpus[n].props.core_id =
2685 (n / ms->smp.threads) % ms->smp.cores;
2686 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2687 ms->possible_cpus->cpus[n].props.thread_id =
2688 n % ms->smp.threads;
2690 return ms->possible_cpus;
2693 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2696 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2697 const MachineState *ms = MACHINE(hotplug_dev);
2698 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2700 if (!vms->acpi_dev) {
2702 "memory hotplug is not enabled: missing acpi-ged device");
2707 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2711 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2712 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2716 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2719 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2720 DeviceState *dev, Error **errp)
2722 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2723 MachineState *ms = MACHINE(hotplug_dev);
2724 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2726 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2729 nvdimm_plug(ms->nvdimms_state);
2732 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2736 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2737 DeviceState *dev, Error **errp)
2739 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2741 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2742 virt_memory_pre_plug(hotplug_dev, dev, errp);
2743 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2744 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2745 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2746 hwaddr db_start = 0, db_end = 0;
2747 char *resv_prop_str;
2749 if (vms->iommu != VIRT_IOMMU_NONE) {
2750 error_setg(errp, "virt machine does not support multiple IOMMUs");
2754 switch (vms->msi_controller) {
2755 case VIRT_MSI_CTRL_NONE:
2757 case VIRT_MSI_CTRL_ITS:
2758 /* GITS_TRANSLATER page */
2759 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2760 db_end = base_memmap[VIRT_GIC_ITS].base +
2761 base_memmap[VIRT_GIC_ITS].size - 1;
2763 case VIRT_MSI_CTRL_GICV2M:
2764 /* MSI_SETSPI_NS page */
2765 db_start = base_memmap[VIRT_GIC_V2M].base;
2766 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2769 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2771 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2773 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
2774 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
2775 resv_prop_str, errp);
2776 g_free(resv_prop_str);
2780 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2781 DeviceState *dev, Error **errp)
2783 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2785 if (vms->platform_bus_dev) {
2786 MachineClass *mc = MACHINE_GET_CLASS(vms);
2788 if (device_is_dynamic_sysbus(mc, dev)) {
2789 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2790 SYS_BUS_DEVICE(dev));
2794 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2795 virt_memory_plug(hotplug_dev, dev, errp);
2796 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2797 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2800 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2801 PCIDevice *pdev = PCI_DEVICE(dev);
2803 vms->iommu = VIRT_IOMMU_VIRTIO;
2804 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2805 create_virtio_iommu_dt_bindings(vms);
2809 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2810 DeviceState *dev, Error **errp)
2812 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2814 if (!vms->acpi_dev) {
2816 "memory hotplug is not enabled: missing acpi-ged device");
2820 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2821 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
2825 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2829 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2830 DeviceState *dev, Error **errp)
2832 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2833 Error *local_err = NULL;
2835 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2840 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2841 qdev_unrealize(dev);
2844 error_propagate(errp, local_err);
2847 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2848 DeviceState *dev, Error **errp)
2850 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2851 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2852 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2853 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
2856 error_setg(errp, "device unplug request for unsupported device"
2857 " type: %s", object_get_typename(OBJECT(dev)));
2861 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2862 DeviceState *dev, Error **errp)
2864 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2865 virt_dimm_unplug(hotplug_dev, dev, errp);
2866 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2867 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2869 error_setg(errp, "virt: device unplug for unsupported device"
2870 " type: %s", object_get_typename(OBJECT(dev)));
2874 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2877 MachineClass *mc = MACHINE_GET_CLASS(machine);
2879 if (device_is_dynamic_sysbus(mc, dev) ||
2880 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2881 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
2882 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2883 return HOTPLUG_HANDLER(machine);
2889 * for arm64 kvm_type [7-0] encodes the requested number of bits
2890 * in the IPA address space
2892 static int virt_kvm_type(MachineState *ms, const char *type_str)
2894 VirtMachineState *vms = VIRT_MACHINE(ms);
2895 int max_vm_pa_size, requested_pa_size;
2898 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2900 /* we freeze the memory map to compute the highest gpa */
2901 virt_set_memmap(vms, max_vm_pa_size);
2903 requested_pa_size = 64 - clz64(vms->highest_gpa);
2906 * KVM requires the IPA size to be at least 32 bits.
2908 if (requested_pa_size < 32) {
2909 requested_pa_size = 32;
2912 if (requested_pa_size > max_vm_pa_size) {
2913 error_report("-m and ,maxmem option values "
2914 "require an IPA range (%d bits) larger than "
2915 "the one supported by the host (%d bits)",
2916 requested_pa_size, max_vm_pa_size);
2920 * We return the requested PA log size, unless KVM only supports
2921 * the implicit legacy 40b IPA setting, in which case the kvm_type
2924 return fixed_ipa ? 0 : requested_pa_size;
2927 static void virt_machine_class_init(ObjectClass *oc, void *data)
2929 MachineClass *mc = MACHINE_CLASS(oc);
2930 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2932 mc->init = machvirt_init;
2933 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2934 * The value may be reduced later when we have more information about the
2935 * configuration of the particular instance.
2938 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2939 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2940 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2941 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2943 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2945 mc->block_default_type = IF_VIRTIO;
2947 mc->pci_allow_0_address = true;
2948 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2949 mc->minimum_page_bits = 12;
2950 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2951 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2953 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2955 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
2957 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2958 mc->kvm_type = virt_kvm_type;
2959 assert(!mc->get_hotplug_handler);
2960 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2961 hc->pre_plug = virt_machine_device_pre_plug_cb;
2962 hc->plug = virt_machine_device_plug_cb;
2963 hc->unplug_request = virt_machine_device_unplug_request_cb;
2964 hc->unplug = virt_machine_device_unplug_cb;
2965 mc->nvdimm_supported = true;
2966 mc->smp_props.clusters_supported = true;
2967 mc->auto_enable_numa_with_memhp = true;
2968 mc->auto_enable_numa_with_memdev = true;
2969 /* platform instead of architectural choice */
2970 mc->cpu_cluster_has_numa_boundary = true;
2971 mc->default_ram_id = "mach-virt.ram";
2972 mc->default_nic = "virtio-net-pci";
2974 object_class_property_add(oc, "acpi", "OnOffAuto",
2975 virt_get_acpi, virt_set_acpi,
2977 object_class_property_set_description(oc, "acpi",
2979 object_class_property_add_bool(oc, "secure", virt_get_secure,
2981 object_class_property_set_description(oc, "secure",
2982 "Set on/off to enable/disable the ARM "
2983 "Security Extensions (TrustZone)");
2985 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2987 object_class_property_set_description(oc, "virtualization",
2988 "Set on/off to enable/disable emulating a "
2989 "guest CPU which implements the ARM "
2990 "Virtualization Extensions");
2992 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2994 object_class_property_set_description(oc, "highmem",
2995 "Set on/off to enable/disable using "
2996 "physical address space above 32 bits");
2998 object_class_property_add_bool(oc, "compact-highmem",
2999 virt_get_compact_highmem,
3000 virt_set_compact_highmem);
3001 object_class_property_set_description(oc, "compact-highmem",
3002 "Set on/off to enable/disable compact "
3003 "layout for high memory regions");
3005 object_class_property_add_bool(oc, "highmem-redists",
3006 virt_get_highmem_redists,
3007 virt_set_highmem_redists);
3008 object_class_property_set_description(oc, "highmem-redists",
3009 "Set on/off to enable/disable high "
3010 "memory region for GICv3 or GICv4 "
3013 object_class_property_add_bool(oc, "highmem-ecam",
3014 virt_get_highmem_ecam,
3015 virt_set_highmem_ecam);
3016 object_class_property_set_description(oc, "highmem-ecam",
3017 "Set on/off to enable/disable high "
3018 "memory region for PCI ECAM");
3020 object_class_property_add_bool(oc, "highmem-mmio",
3021 virt_get_highmem_mmio,
3022 virt_set_highmem_mmio);
3023 object_class_property_set_description(oc, "highmem-mmio",
3024 "Set on/off to enable/disable high "
3025 "memory region for PCI MMIO");
3027 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3028 virt_set_gic_version);
3029 object_class_property_set_description(oc, "gic-version",
3031 "Valid values are 2, 3, 4, host and max");
3033 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
3034 object_class_property_set_description(oc, "iommu",
3035 "Set the IOMMU type. "
3036 "Valid values are none and smmuv3");
3038 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3039 virt_get_default_bus_bypass_iommu,
3040 virt_set_default_bus_bypass_iommu);
3041 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3042 "Set on/off to enable/disable "
3043 "bypass_iommu for default root bus");
3045 object_class_property_add_bool(oc, "ras", virt_get_ras,
3047 object_class_property_set_description(oc, "ras",
3048 "Set on/off to enable/disable reporting host memory errors "
3049 "to a KVM guest using ACPI and guest external abort exceptions");
3051 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
3052 object_class_property_set_description(oc, "mte",
3053 "Set on/off to enable/disable emulating a "
3054 "guest CPU which implements the ARM "
3055 "Memory Tagging Extension");
3057 object_class_property_add_bool(oc, "its", virt_get_its,
3059 object_class_property_set_description(oc, "its",
3060 "Set on/off to enable/disable "
3061 "ITS instantiation");
3063 object_class_property_add_bool(oc, "dtb-randomness",
3064 virt_get_dtb_randomness,
3065 virt_set_dtb_randomness);
3066 object_class_property_set_description(oc, "dtb-randomness",
3067 "Set off to disable passing random or "
3068 "non-deterministic dtb nodes to guest");
3070 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3071 virt_get_dtb_randomness,
3072 virt_set_dtb_randomness);
3073 object_class_property_set_description(oc, "dtb-kaslr-seed",
3074 "Deprecated synonym of dtb-randomness");
3076 object_class_property_add_str(oc, "x-oem-id",
3079 object_class_property_set_description(oc, "x-oem-id",
3080 "Override the default value of field OEMID "
3081 "in ACPI table header."
3082 "The string may be up to 6 bytes in size");
3085 object_class_property_add_str(oc, "x-oem-table-id",
3086 virt_get_oem_table_id,
3087 virt_set_oem_table_id);
3088 object_class_property_set_description(oc, "x-oem-table-id",
3089 "Override the default value of field OEM Table ID "
3090 "in ACPI table header."
3091 "The string may be up to 8 bytes in size");
3095 static void virt_instance_init(Object *obj)
3097 VirtMachineState *vms = VIRT_MACHINE(obj);
3098 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3100 /* EL3 is disabled by default on virt: this makes us consistent
3101 * between KVM and TCG for this board, and it also allows us to
3102 * boot UEFI blobs which assume no TrustZone support.
3104 vms->secure = false;
3106 /* EL2 is also disabled by default, for similar reasons */
3109 /* High memory is enabled by default */
3110 vms->highmem = true;
3111 vms->highmem_compact = !vmc->no_highmem_compact;
3112 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3114 vms->highmem_ecam = !vmc->no_highmem_ecam;
3115 vms->highmem_mmio = true;
3116 vms->highmem_redists = true;
3121 /* Default allows ITS instantiation */
3124 if (vmc->no_tcg_its) {
3125 vms->tcg_its = false;
3127 vms->tcg_its = true;
3131 /* Default disallows iommu instantiation */
3132 vms->iommu = VIRT_IOMMU_NONE;
3134 /* The default root bus is attached to iommu by default */
3135 vms->default_bus_bypass_iommu = false;
3137 /* Default disallows RAS instantiation */
3140 /* MTE is disabled by default. */
3143 /* Supply kaslr-seed and rng-seed by default */
3144 vms->dtb_randomness = true;
3146 vms->irqmap = a15irqmap;
3148 virt_flash_create(vms);
3150 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3151 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3154 static const TypeInfo virt_machine_info = {
3155 .name = TYPE_VIRT_MACHINE,
3156 .parent = TYPE_MACHINE,
3158 .instance_size = sizeof(VirtMachineState),
3159 .class_size = sizeof(VirtMachineClass),
3160 .class_init = virt_machine_class_init,
3161 .instance_init = virt_instance_init,
3162 .interfaces = (InterfaceInfo[]) {
3163 { TYPE_HOTPLUG_HANDLER },
3168 static void machvirt_machine_init(void)
3170 type_register_static(&virt_machine_info);
3172 type_init(machvirt_machine_init);
3174 static void virt_machine_8_2_options(MachineClass *mc)
3177 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2)
3179 static void virt_machine_8_1_options(MachineClass *mc)
3181 virt_machine_8_2_options(mc);
3182 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3184 DEFINE_VIRT_MACHINE(8, 1)
3186 static void virt_machine_8_0_options(MachineClass *mc)
3188 virt_machine_8_1_options(mc);
3189 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3191 DEFINE_VIRT_MACHINE(8, 0)
3193 static void virt_machine_7_2_options(MachineClass *mc)
3195 virt_machine_8_0_options(mc);
3196 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3198 DEFINE_VIRT_MACHINE(7, 2)
3200 static void virt_machine_7_1_options(MachineClass *mc)
3202 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3204 virt_machine_7_2_options(mc);
3205 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3206 /* Compact layout for high memory regions was introduced with 7.2 */
3207 vmc->no_highmem_compact = true;
3209 DEFINE_VIRT_MACHINE(7, 1)
3211 static void virt_machine_7_0_options(MachineClass *mc)
3213 virt_machine_7_1_options(mc);
3214 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3216 DEFINE_VIRT_MACHINE(7, 0)
3218 static void virt_machine_6_2_options(MachineClass *mc)
3220 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3222 virt_machine_7_0_options(mc);
3223 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3224 vmc->no_tcg_lpa2 = true;
3226 DEFINE_VIRT_MACHINE(6, 2)
3228 static void virt_machine_6_1_options(MachineClass *mc)
3230 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3232 virt_machine_6_2_options(mc);
3233 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3234 mc->smp_props.prefer_sockets = true;
3235 vmc->no_cpu_topology = true;
3237 /* qemu ITS was introduced with 6.2 */
3238 vmc->no_tcg_its = true;
3240 DEFINE_VIRT_MACHINE(6, 1)
3242 static void virt_machine_6_0_options(MachineClass *mc)
3244 virt_machine_6_1_options(mc);
3245 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3247 DEFINE_VIRT_MACHINE(6, 0)
3249 static void virt_machine_5_2_options(MachineClass *mc)
3251 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3253 virt_machine_6_0_options(mc);
3254 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3255 vmc->no_secure_gpio = true;
3257 DEFINE_VIRT_MACHINE(5, 2)
3259 static void virt_machine_5_1_options(MachineClass *mc)
3261 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3263 virt_machine_5_2_options(mc);
3264 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3265 vmc->no_kvm_steal_time = true;
3267 DEFINE_VIRT_MACHINE(5, 1)
3269 static void virt_machine_5_0_options(MachineClass *mc)
3271 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3273 virt_machine_5_1_options(mc);
3274 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3275 mc->numa_mem_supported = true;
3276 vmc->acpi_expose_flash = true;
3277 mc->auto_enable_numa_with_memdev = false;
3279 DEFINE_VIRT_MACHINE(5, 0)
3281 static void virt_machine_4_2_options(MachineClass *mc)
3283 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3285 virt_machine_5_0_options(mc);
3286 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3287 vmc->kvm_no_adjvtime = true;
3289 DEFINE_VIRT_MACHINE(4, 2)
3291 static void virt_machine_4_1_options(MachineClass *mc)
3293 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3295 virt_machine_4_2_options(mc);
3296 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3298 mc->auto_enable_numa_with_memhp = false;
3300 DEFINE_VIRT_MACHINE(4, 1)
3302 static void virt_machine_4_0_options(MachineClass *mc)
3304 virt_machine_4_1_options(mc);
3305 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
3307 DEFINE_VIRT_MACHINE(4, 0)
3309 static void virt_machine_3_1_options(MachineClass *mc)
3311 virt_machine_4_0_options(mc);
3312 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
3314 DEFINE_VIRT_MACHINE(3, 1)
3316 static void virt_machine_3_0_options(MachineClass *mc)
3318 virt_machine_3_1_options(mc);
3319 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
3321 DEFINE_VIRT_MACHINE(3, 0)
3323 static void virt_machine_2_12_options(MachineClass *mc)
3325 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3327 virt_machine_3_0_options(mc);
3328 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3329 vmc->no_highmem_ecam = true;
3332 DEFINE_VIRT_MACHINE(2, 12)
3334 static void virt_machine_2_11_options(MachineClass *mc)
3336 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3338 virt_machine_2_12_options(mc);
3339 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3340 vmc->smbios_old_sys_ver = true;
3342 DEFINE_VIRT_MACHINE(2, 11)
3344 static void virt_machine_2_10_options(MachineClass *mc)
3346 virt_machine_2_11_options(mc);
3347 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3348 /* before 2.11 we never faulted accesses to bad addresses */
3349 mc->ignore_memory_transaction_failures = true;
3351 DEFINE_VIRT_MACHINE(2, 10)
3353 static void virt_machine_2_9_options(MachineClass *mc)
3355 virt_machine_2_10_options(mc);
3356 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3358 DEFINE_VIRT_MACHINE(2, 9)
3360 static void virt_machine_2_8_options(MachineClass *mc)
3362 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3364 virt_machine_2_9_options(mc);
3365 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3366 /* For 2.8 and earlier we falsely claimed in the DT that
3367 * our timers were edge-triggered, not level-triggered.
3369 vmc->claim_edge_triggered_timers = true;
3371 DEFINE_VIRT_MACHINE(2, 8)
3373 static void virt_machine_2_7_options(MachineClass *mc)
3375 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3377 virt_machine_2_8_options(mc);
3378 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3379 /* ITS was introduced with 2.8 */
3381 /* Stick with 1K pages for migration compatibility */
3382 mc->minimum_page_bits = 0;
3384 DEFINE_VIRT_MACHINE(2, 7)
3386 static void virt_machine_2_6_options(MachineClass *mc)
3388 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3390 virt_machine_2_7_options(mc);
3391 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3392 vmc->disallow_affinity_adjustment = true;
3393 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3396 DEFINE_VIRT_MACHINE(2, 6)