2 * QEMU SCI/SCIF serial port emulation
4 * Copyright (c) 2007 Magnus Damm
6 * Based on serial.c - QEMU 16450 UART emulation
7 * Copyright (c) 2003-2004 Fabrice Bellard
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
29 #include "hw/sh4/sh.h"
30 #include "chardev/char-fe.h"
31 #include "qapi/error.h"
32 #include "qemu/timer.h"
34 //#define DEBUG_SERIAL
36 #define SH_SERIAL_FLAG_TEND (1 << 0)
37 #define SH_SERIAL_FLAG_TDE (1 << 1)
38 #define SH_SERIAL_FLAG_RDF (1 << 2)
39 #define SH_SERIAL_FLAG_BRK (1 << 3)
40 #define SH_SERIAL_FLAG_DR (1 << 4)
42 #define SH_RX_FIFO_LENGTH (16)
46 MemoryRegion iomem_p4;
47 MemoryRegion iomem_a7;
51 uint8_t dr; /* ftdr / tdr */
52 uint8_t sr; /* fsr / ssr */
56 uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
67 QEMUTimer *fifo_timeout_timer;
68 uint64_t etu; /* Elementary Time Unit (ns) */
77 static void sh_serial_clear_fifo(sh_serial_state * s)
79 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
85 static void sh_serial_write(void *opaque, hwaddr offs,
86 uint64_t val, unsigned size)
88 sh_serial_state *s = opaque;
92 printf("sh_serial: write offs=0x%02x val=0x%02x\n",
97 s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
103 /* TODO : For SH7751, SCIF mask should be 0xfb. */
104 s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
105 if (!(val & (1 << 5)))
106 s->flags |= SH_SERIAL_FLAG_TEND;
107 if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
108 qemu_set_irq(s->txi, val & (1 << 7));
110 if (!(val & (1 << 6))) {
111 qemu_set_irq(s->rxi, 0);
114 case 0x0c: /* FTDR / TDR */
115 if (qemu_chr_fe_backend_connected(&s->chr)) {
117 /* XXX this blocks entire thread. Rewrite to use
118 * qemu_chr_fe_write and background I/O callbacks */
119 qemu_chr_fe_write_all(&s->chr, &ch, 1);
122 s->flags &= ~SH_SERIAL_FLAG_TDE;
125 case 0x14: /* FRDR / RDR */
130 if (s->feat & SH_SERIAL_FEAT_SCIF) {
133 if (!(val & (1 << 6)))
134 s->flags &= ~SH_SERIAL_FLAG_TEND;
135 if (!(val & (1 << 5)))
136 s->flags &= ~SH_SERIAL_FLAG_TDE;
137 if (!(val & (1 << 4)))
138 s->flags &= ~SH_SERIAL_FLAG_BRK;
139 if (!(val & (1 << 1)))
140 s->flags &= ~SH_SERIAL_FLAG_RDF;
141 if (!(val & (1 << 0)))
142 s->flags &= ~SH_SERIAL_FLAG_DR;
144 if (!(val & (1 << 1)) || !(val & (1 << 0))) {
146 qemu_set_irq(s->rxi, 0);
152 switch ((val >> 6) & 3) {
166 if (val & (1 << 1)) {
167 sh_serial_clear_fifo(s);
172 case 0x20: /* SPTR */
173 s->sptr = val & 0xf3;
190 s->sptr = val & 0x8f;
195 fprintf(stderr, "sh_serial: unsupported write to 0x%02"
196 HWADDR_PRIx "\n", offs);
200 static uint64_t sh_serial_read(void *opaque, hwaddr offs,
203 sh_serial_state *s = opaque;
222 if (s->feat & SH_SERIAL_FEAT_SCIF) {
232 if (s->flags & SH_SERIAL_FLAG_TEND)
234 if (s->flags & SH_SERIAL_FLAG_TDE)
236 if (s->flags & SH_SERIAL_FLAG_BRK)
238 if (s->flags & SH_SERIAL_FLAG_RDF)
240 if (s->flags & SH_SERIAL_FLAG_DR)
243 if (s->scr & (1 << 5))
244 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
249 ret = s->rx_fifo[s->rx_tail++];
251 if (s->rx_tail == SH_RX_FIFO_LENGTH)
253 if (s->rx_cnt < s->rtrg)
254 s->flags &= ~SH_SERIAL_FLAG_RDF;
290 printf("sh_serial: read offs=0x%02x val=0x%x\n",
294 if (ret & ~((1 << 16) - 1)) {
295 fprintf(stderr, "sh_serial: unsupported read from 0x%02"
296 HWADDR_PRIx "\n", offs);
303 static int sh_serial_can_receive(sh_serial_state *s)
305 return s->scr & (1 << 4);
308 static void sh_serial_receive_break(sh_serial_state *s)
310 if (s->feat & SH_SERIAL_FEAT_SCIF)
314 static int sh_serial_can_receive1(void *opaque)
316 sh_serial_state *s = opaque;
317 return sh_serial_can_receive(s);
320 static void sh_serial_timeout_int(void *opaque)
322 sh_serial_state *s = opaque;
324 s->flags |= SH_SERIAL_FLAG_RDF;
325 if (s->scr & (1 << 6) && s->rxi) {
326 qemu_set_irq(s->rxi, 1);
330 static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
332 sh_serial_state *s = opaque;
334 if (s->feat & SH_SERIAL_FEAT_SCIF) {
336 for (i = 0; i < size; i++) {
337 if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
338 s->rx_fifo[s->rx_head++] = buf[i];
339 if (s->rx_head == SH_RX_FIFO_LENGTH) {
343 if (s->rx_cnt >= s->rtrg) {
344 s->flags |= SH_SERIAL_FLAG_RDF;
345 if (s->scr & (1 << 6) && s->rxi) {
346 timer_del(s->fifo_timeout_timer);
347 qemu_set_irq(s->rxi, 1);
350 timer_mod(s->fifo_timeout_timer,
351 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
356 s->rx_fifo[0] = buf[0];
360 static void sh_serial_event(void *opaque, int event)
362 sh_serial_state *s = opaque;
363 if (event == CHR_EVENT_BREAK)
364 sh_serial_receive_break(s);
367 static const MemoryRegionOps sh_serial_ops = {
368 .read = sh_serial_read,
369 .write = sh_serial_write,
370 .endianness = DEVICE_NATIVE_ENDIAN,
373 void sh_serial_init(MemoryRegion *sysmem,
374 hwaddr base, int feat,
375 uint32_t freq, Chardev *chr,
384 s = g_malloc0(sizeof(sh_serial_state));
387 s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
392 s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
395 if (feat & SH_SERIAL_FEAT_SCIF) {
402 sh_serial_clear_fifo(s);
404 memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
405 "serial", 0x100000000ULL);
407 memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
409 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
411 memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
413 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
416 qemu_chr_fe_init(&s->chr, chr, &error_abort);
417 qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
419 sh_serial_event, NULL, s, NULL, true);
422 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
423 sh_serial_timeout_int, s);
424 s->etu = NANOSECONDS_PER_SECOND / 9600;