4 * Copyright (C) 2014 Red Hat Inc
7 * Marcel Apfelbaum <marcel.a@redhat.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qemu/option.h"
15 #include "qapi/qmp/qerror.h"
16 #include "sysemu/replay.h"
17 #include "qemu/units.h"
18 #include "hw/boards.h"
19 #include "hw/loader.h"
20 #include "qapi/error.h"
21 #include "qapi/qapi-visit-common.h"
22 #include "qapi/qapi-visit-machine.h"
23 #include "qapi/visitor.h"
24 #include "qom/object_interfaces.h"
25 #include "hw/sysbus.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/numa.h"
31 #include "sysemu/xen.h"
32 #include "qemu/error-report.h"
33 #include "sysemu/qtest.h"
34 #include "hw/pci/pci.h"
35 #include "hw/mem/nvdimm.h"
36 #include "hw/cxl/cxl.h"
37 #include "migration/global_state.h"
38 #include "migration/vmstate.h"
39 #include "exec/confidential-guest-support.h"
40 #include "hw/virtio/virtio.h"
41 #include "hw/virtio/virtio-pci.h"
42 #include "qom/object_interfaces.h"
44 GlobalProperty hw_compat_7_0[] = {
45 { "arm-gicv3-common", "force-8-bit-prio", "on" },
46 { "nvme-ns", "eui64-default", "on"},
48 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0);
50 GlobalProperty hw_compat_6_2[] = {
51 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"},
53 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2);
55 GlobalProperty hw_compat_6_1[] = {
56 { "vhost-user-vsock-device", "seqpacket", "off" },
57 { "nvme-ns", "shared", "off" },
59 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1);
61 GlobalProperty hw_compat_6_0[] = {
62 { "gpex-pcihost", "allow-unmapped-accesses", "false" },
63 { "i8042", "extended-state", "false"},
64 { "nvme-ns", "eui64-default", "off"},
65 { "e1000", "init-vet", "off" },
66 { "e1000e", "init-vet", "off" },
67 { "vhost-vsock-device", "seqpacket", "off" },
69 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
71 GlobalProperty hw_compat_5_2[] = {
72 { "ICH9-LPC", "smm-compat", "on"},
73 { "PIIX4_PM", "smm-compat", "on"},
74 { "virtio-blk-device", "report-discard-granularity", "off" },
75 { "virtio-net-pci-base", "vectors", "3"},
77 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
79 GlobalProperty hw_compat_5_1[] = {
80 { "vhost-scsi", "num_queues", "1"},
81 { "vhost-user-blk", "num-queues", "1"},
82 { "vhost-user-scsi", "num_queues", "1"},
83 { "virtio-blk-device", "num-queues", "1"},
84 { "virtio-scsi-device", "num_queues", "1"},
85 { "nvme", "use-intel-id", "on"},
86 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
87 { "pl011", "migrate-clk", "off" },
88 { "virtio-pci", "x-ats-page-aligned", "off"},
90 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
92 GlobalProperty hw_compat_5_0[] = {
93 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" },
94 { "virtio-balloon-device", "page-poison", "false" },
95 { "vmport", "x-read-set-eax", "off" },
96 { "vmport", "x-signal-unsupported-cmd", "off" },
97 { "vmport", "x-report-vmx-type", "off" },
98 { "vmport", "x-cmds-v2", "off" },
99 { "virtio-device", "x-disable-legacy-check", "true" },
101 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
103 GlobalProperty hw_compat_4_2[] = {
104 { "virtio-blk-device", "queue-size", "128"},
105 { "virtio-scsi-device", "virtqueue_size", "128"},
106 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" },
107 { "virtio-blk-device", "seg-max-adjust", "off"},
108 { "virtio-scsi-device", "seg_max_adjust", "off"},
109 { "vhost-blk-device", "seg_max_adjust", "off"},
110 { "usb-host", "suppress-remote-wake", "off" },
111 { "usb-redir", "suppress-remote-wake", "off" },
112 { "qxl", "revision", "4" },
113 { "qxl-vga", "revision", "4" },
114 { "fw_cfg", "acpi-mr-restore", "false" },
115 { "virtio-device", "use-disabled-flag", "false" },
117 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2);
119 GlobalProperty hw_compat_4_1[] = {
120 { "virtio-pci", "x-pcie-flr-init", "off" },
122 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1);
124 GlobalProperty hw_compat_4_0[] = {
125 { "VGA", "edid", "false" },
126 { "secondary-vga", "edid", "false" },
127 { "bochs-display", "edid", "false" },
128 { "virtio-vga", "edid", "false" },
129 { "virtio-gpu-device", "edid", "false" },
130 { "virtio-device", "use-started", "false" },
131 { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
132 { "pl031", "migrate-tick-offset", "false" },
134 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
136 GlobalProperty hw_compat_3_1[] = {
137 { "pcie-root-port", "x-speed", "2_5" },
138 { "pcie-root-port", "x-width", "1" },
139 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
140 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
141 { "tpm-crb", "ppi", "false" },
142 { "tpm-tis", "ppi", "false" },
143 { "usb-kbd", "serial", "42" },
144 { "usb-mouse", "serial", "42" },
145 { "usb-tablet", "serial", "42" },
146 { "virtio-blk-device", "discard", "false" },
147 { "virtio-blk-device", "write-zeroes", "false" },
148 { "virtio-balloon-device", "qemu-4-0-config-size", "false" },
149 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */
151 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
153 GlobalProperty hw_compat_3_0[] = {};
154 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0);
156 GlobalProperty hw_compat_2_12[] = {
157 { "migration", "decompress-error-check", "off" },
158 { "hda-audio", "use-timer", "false" },
159 { "cirrus-vga", "global-vmstate", "true" },
160 { "VGA", "global-vmstate", "true" },
161 { "vmware-svga", "global-vmstate", "true" },
162 { "qxl-vga", "global-vmstate", "true" },
164 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12);
166 GlobalProperty hw_compat_2_11[] = {
167 { "hpet", "hpet-offset-saved", "false" },
168 { "virtio-blk-pci", "vectors", "2" },
169 { "vhost-user-blk-pci", "vectors", "2" },
170 { "e1000", "migrate_tso_props", "off" },
172 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11);
174 GlobalProperty hw_compat_2_10[] = {
175 { "virtio-mouse-device", "wheel-axis", "false" },
176 { "virtio-tablet-device", "wheel-axis", "false" },
178 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10);
180 GlobalProperty hw_compat_2_9[] = {
181 { "pci-bridge", "shpc", "off" },
182 { "intel-iommu", "pt", "off" },
183 { "virtio-net-device", "x-mtu-bypass-backend", "off" },
184 { "pcie-root-port", "x-migrate-msix", "false" },
186 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9);
188 GlobalProperty hw_compat_2_8[] = {
189 { "fw_cfg_mem", "x-file-slots", "0x10" },
190 { "fw_cfg_io", "x-file-slots", "0x10" },
191 { "pflash_cfi01", "old-multiple-chip-handling", "on" },
192 { "pci-bridge", "shpc", "on" },
193 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" },
194 { "virtio-pci", "x-pcie-deverr-init", "off" },
195 { "virtio-pci", "x-pcie-lnkctl-init", "off" },
196 { "virtio-pci", "x-pcie-pm-init", "off" },
197 { "cirrus-vga", "vgamem_mb", "8" },
198 { "isa-cirrus-vga", "vgamem_mb", "8" },
200 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
202 GlobalProperty hw_compat_2_7[] = {
203 { "virtio-pci", "page-per-vq", "on" },
204 { "virtio-serial-device", "emergency-write", "off" },
205 { "ioapic", "version", "0x11" },
206 { "intel-iommu", "x-buggy-eim", "true" },
207 { "virtio-pci", "x-ignore-backend-features", "on" },
209 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
211 GlobalProperty hw_compat_2_6[] = {
212 { "virtio-mmio", "format_transport_address", "off" },
213 /* Optional because not all virtio-pci devices support legacy mode */
214 { "virtio-pci", "disable-modern", "on", .optional = true },
215 { "virtio-pci", "disable-legacy", "off", .optional = true },
217 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
219 GlobalProperty hw_compat_2_5[] = {
220 { "isa-fdc", "fallback", "144" },
221 { "pvscsi", "x-old-pci-configuration", "on" },
222 { "pvscsi", "x-disable-pcie", "on" },
223 { "vmxnet3", "x-old-msi-offsets", "on" },
224 { "vmxnet3", "x-disable-pcie", "on" },
226 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
228 GlobalProperty hw_compat_2_4[] = {
229 /* Optional because the 'scsi' property is Linux-only */
230 { "virtio-blk-device", "scsi", "true", .optional = true },
231 { "e1000", "extra_mac_registers", "off" },
232 { "virtio-pci", "x-disable-pcie", "on" },
233 { "virtio-pci", "migrate-extra", "off" },
234 { "fw_cfg_mem", "dma_enabled", "off" },
235 { "fw_cfg_io", "dma_enabled", "off" }
237 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
239 GlobalProperty hw_compat_2_3[] = {
240 { "virtio-blk-pci", "any_layout", "off" },
241 { "virtio-balloon-pci", "any_layout", "off" },
242 { "virtio-serial-pci", "any_layout", "off" },
243 { "virtio-9p-pci", "any_layout", "off" },
244 { "virtio-rng-pci", "any_layout", "off" },
245 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" },
246 { "migration", "send-configuration", "off" },
247 { "migration", "send-section-footer", "off" },
248 { "migration", "store-global-state", "off" },
250 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
252 GlobalProperty hw_compat_2_2[] = {};
253 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
255 GlobalProperty hw_compat_2_1[] = {
256 { "intel-hda", "old_msi_addr", "on" },
257 { "VGA", "qemu-extended-regs", "off" },
258 { "secondary-vga", "qemu-extended-regs", "off" },
259 { "virtio-scsi-pci", "any_layout", "off" },
260 { "usb-mouse", "usb_version", "1" },
261 { "usb-kbd", "usb_version", "1" },
262 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" },
264 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
266 MachineState *current_machine;
268 static char *machine_get_kernel(Object *obj, Error **errp)
270 MachineState *ms = MACHINE(obj);
272 return g_strdup(ms->kernel_filename);
275 static void machine_set_kernel(Object *obj, const char *value, Error **errp)
277 MachineState *ms = MACHINE(obj);
279 g_free(ms->kernel_filename);
280 ms->kernel_filename = g_strdup(value);
283 static char *machine_get_initrd(Object *obj, Error **errp)
285 MachineState *ms = MACHINE(obj);
287 return g_strdup(ms->initrd_filename);
290 static void machine_set_initrd(Object *obj, const char *value, Error **errp)
292 MachineState *ms = MACHINE(obj);
294 g_free(ms->initrd_filename);
295 ms->initrd_filename = g_strdup(value);
298 static char *machine_get_append(Object *obj, Error **errp)
300 MachineState *ms = MACHINE(obj);
302 return g_strdup(ms->kernel_cmdline);
305 static void machine_set_append(Object *obj, const char *value, Error **errp)
307 MachineState *ms = MACHINE(obj);
309 g_free(ms->kernel_cmdline);
310 ms->kernel_cmdline = g_strdup(value);
313 static char *machine_get_dtb(Object *obj, Error **errp)
315 MachineState *ms = MACHINE(obj);
317 return g_strdup(ms->dtb);
320 static void machine_set_dtb(Object *obj, const char *value, Error **errp)
322 MachineState *ms = MACHINE(obj);
325 ms->dtb = g_strdup(value);
328 static char *machine_get_dumpdtb(Object *obj, Error **errp)
330 MachineState *ms = MACHINE(obj);
332 return g_strdup(ms->dumpdtb);
335 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp)
337 MachineState *ms = MACHINE(obj);
340 ms->dumpdtb = g_strdup(value);
343 static void machine_get_phandle_start(Object *obj, Visitor *v,
344 const char *name, void *opaque,
347 MachineState *ms = MACHINE(obj);
348 int64_t value = ms->phandle_start;
350 visit_type_int(v, name, &value, errp);
353 static void machine_set_phandle_start(Object *obj, Visitor *v,
354 const char *name, void *opaque,
357 MachineState *ms = MACHINE(obj);
360 if (!visit_type_int(v, name, &value, errp)) {
364 ms->phandle_start = value;
367 static char *machine_get_dt_compatible(Object *obj, Error **errp)
369 MachineState *ms = MACHINE(obj);
371 return g_strdup(ms->dt_compatible);
374 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp)
376 MachineState *ms = MACHINE(obj);
378 g_free(ms->dt_compatible);
379 ms->dt_compatible = g_strdup(value);
382 static bool machine_get_dump_guest_core(Object *obj, Error **errp)
384 MachineState *ms = MACHINE(obj);
386 return ms->dump_guest_core;
389 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp)
391 MachineState *ms = MACHINE(obj);
393 ms->dump_guest_core = value;
396 static bool machine_get_mem_merge(Object *obj, Error **errp)
398 MachineState *ms = MACHINE(obj);
400 return ms->mem_merge;
403 static void machine_set_mem_merge(Object *obj, bool value, Error **errp)
405 MachineState *ms = MACHINE(obj);
407 ms->mem_merge = value;
410 static bool machine_get_usb(Object *obj, Error **errp)
412 MachineState *ms = MACHINE(obj);
417 static void machine_set_usb(Object *obj, bool value, Error **errp)
419 MachineState *ms = MACHINE(obj);
422 ms->usb_disabled = !value;
425 static bool machine_get_graphics(Object *obj, Error **errp)
427 MachineState *ms = MACHINE(obj);
429 return ms->enable_graphics;
432 static void machine_set_graphics(Object *obj, bool value, Error **errp)
434 MachineState *ms = MACHINE(obj);
436 ms->enable_graphics = value;
439 static char *machine_get_firmware(Object *obj, Error **errp)
441 MachineState *ms = MACHINE(obj);
443 return g_strdup(ms->firmware);
446 static void machine_set_firmware(Object *obj, const char *value, Error **errp)
448 MachineState *ms = MACHINE(obj);
450 g_free(ms->firmware);
451 ms->firmware = g_strdup(value);
454 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp)
456 MachineState *ms = MACHINE(obj);
458 ms->suppress_vmdesc = value;
461 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp)
463 MachineState *ms = MACHINE(obj);
465 return ms->suppress_vmdesc;
468 static char *machine_get_memory_encryption(Object *obj, Error **errp)
470 MachineState *ms = MACHINE(obj);
473 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs)));
479 static void machine_set_memory_encryption(Object *obj, const char *value,
483 object_resolve_path_component(object_get_objects_root(), value);
486 error_setg(errp, "No such memory encryption object '%s'", value);
490 object_property_set_link(obj, "confidential-guest-support", cgs, errp);
493 static void machine_check_confidential_guest_support(const Object *obj,
499 * So far the only constraint is that the target has the
500 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked
505 static bool machine_get_nvdimm(Object *obj, Error **errp)
507 MachineState *ms = MACHINE(obj);
509 return ms->nvdimms_state->is_enabled;
512 static void machine_set_nvdimm(Object *obj, bool value, Error **errp)
514 MachineState *ms = MACHINE(obj);
516 ms->nvdimms_state->is_enabled = value;
519 static bool machine_get_hmat(Object *obj, Error **errp)
521 MachineState *ms = MACHINE(obj);
523 return ms->numa_state->hmat_enabled;
526 static void machine_set_hmat(Object *obj, bool value, Error **errp)
528 MachineState *ms = MACHINE(obj);
530 ms->numa_state->hmat_enabled = value;
533 static void machine_get_mem(Object *obj, Visitor *v, const char *name,
534 void *opaque, Error **errp)
536 MachineState *ms = MACHINE(obj);
537 MemorySizeConfiguration mem = {
539 .size = ms->ram_size,
540 .has_max_size = !!ms->ram_slots,
541 .max_size = ms->maxram_size,
542 .has_slots = !!ms->ram_slots,
543 .slots = ms->ram_slots,
545 MemorySizeConfiguration *p_mem = &mem;
547 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort);
550 static void machine_set_mem(Object *obj, Visitor *v, const char *name,
551 void *opaque, Error **errp)
553 MachineState *ms = MACHINE(obj);
554 MachineClass *mc = MACHINE_GET_CLASS(obj);
555 MemorySizeConfiguration *mem;
559 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) {
563 if (!mem->has_size) {
564 mem->has_size = true;
565 mem->size = mc->default_ram_size;
567 mem->size = QEMU_ALIGN_UP(mem->size, 8192);
568 if (mc->fixup_ram_size) {
569 mem->size = mc->fixup_ram_size(mem->size);
571 if ((ram_addr_t)mem->size != mem->size) {
572 error_setg(errp, "ram size too large");
576 if (mem->has_max_size) {
577 if (mem->max_size < mem->size) {
578 error_setg(errp, "invalid value of maxmem: "
579 "maximum memory size (0x%" PRIx64 ") must be at least "
580 "the initial memory size (0x%" PRIx64 ")",
581 mem->max_size, mem->size);
584 if (mem->has_slots && mem->slots && mem->max_size == mem->size) {
585 error_setg(errp, "invalid value of maxmem: "
586 "memory slots were specified but maximum memory size "
587 "(0x%" PRIx64 ") is equal to the initial memory size "
588 "(0x%" PRIx64 ")", mem->max_size, mem->size);
591 ms->maxram_size = mem->max_size;
593 if (mem->has_slots) {
594 error_setg(errp, "slots specified but no max-size");
597 ms->maxram_size = mem->size;
599 ms->ram_size = mem->size;
600 ms->ram_slots = mem->has_slots ? mem->slots : 0;
602 qapi_free_MemorySizeConfiguration(mem);
605 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp)
607 MachineState *ms = MACHINE(obj);
609 return g_strdup(ms->nvdimms_state->persistence_string);
612 static void machine_set_nvdimm_persistence(Object *obj, const char *value,
615 MachineState *ms = MACHINE(obj);
616 NVDIMMState *nvdimms_state = ms->nvdimms_state;
618 if (strcmp(value, "cpu") == 0) {
619 nvdimms_state->persistence = 3;
620 } else if (strcmp(value, "mem-ctrl") == 0) {
621 nvdimms_state->persistence = 2;
623 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
628 g_free(nvdimms_state->persistence_string);
629 nvdimms_state->persistence_string = g_strdup(value);
632 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
634 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
637 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
639 Object *obj = OBJECT(dev);
641 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
645 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj));
648 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type)
650 bool allowed = false;
652 ObjectClass *klass = object_class_by_name(type);
654 for (wl = mc->allowed_dynamic_sysbus_devices;
657 allowed |= !!object_class_dynamic_cast(klass, wl->value);
663 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
666 HotpluggableCPUList *head = NULL;
667 MachineClass *mc = MACHINE_GET_CLASS(machine);
669 /* force board to initialize possible_cpus if it hasn't been done yet */
670 mc->possible_cpu_arch_ids(machine);
672 for (i = 0; i < machine->possible_cpus->len; i++) {
674 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
676 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
677 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
678 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
679 sizeof(*cpu_item->props));
681 cpu = machine->possible_cpus->cpus[i].cpu;
683 cpu_item->has_qom_path = true;
684 cpu_item->qom_path = object_get_canonical_path(cpu);
686 QAPI_LIST_PREPEND(head, cpu_item);
692 * machine_set_cpu_numa_node:
693 * @machine: machine object to modify
694 * @props: specifies which cpu objects to assign to
695 * numa node specified by @props.node_id
696 * @errp: if an error occurs, a pointer to an area to store the error
698 * Associate NUMA node specified by @props.node_id with cpu slots that
699 * match socket/core/thread-ids specified by @props. It's recommended to use
700 * query-hotpluggable-cpus.props values to specify affected cpu slots,
701 * which would lead to exact 1:1 mapping of cpu slots to NUMA node.
703 * However for CLI convenience it's possible to pass in subset of properties,
704 * which would affect all cpu slots that match it.
706 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \
707 * -numa cpu,node-id=0,socket_id=0 \
708 * -numa cpu,node-id=1,socket_id=1
709 * will assign all child cores of socket 0 to node 0 and
710 * of socket 1 to node 1.
712 * On attempt of reassigning (already assigned) cpu slot to another NUMA node,
714 * Empty subset is disallowed and function will return with error in this case.
716 void machine_set_cpu_numa_node(MachineState *machine,
717 const CpuInstanceProperties *props, Error **errp)
719 MachineClass *mc = MACHINE_GET_CLASS(machine);
720 NodeInfo *numa_info = machine->numa_state->nodes;
724 if (!mc->possible_cpu_arch_ids) {
725 error_setg(errp, "mapping of CPUs to NUMA node is not supported");
729 /* disabling node mapping is not supported, forbid it */
730 assert(props->has_node_id);
732 /* force board to initialize possible_cpus if it hasn't been done yet */
733 mc->possible_cpu_arch_ids(machine);
735 for (i = 0; i < machine->possible_cpus->len; i++) {
736 CPUArchId *slot = &machine->possible_cpus->cpus[i];
738 /* reject unsupported by board properties */
739 if (props->has_thread_id && !slot->props.has_thread_id) {
740 error_setg(errp, "thread-id is not supported");
744 if (props->has_core_id && !slot->props.has_core_id) {
745 error_setg(errp, "core-id is not supported");
749 if (props->has_cluster_id && !slot->props.has_cluster_id) {
750 error_setg(errp, "cluster-id is not supported");
754 if (props->has_socket_id && !slot->props.has_socket_id) {
755 error_setg(errp, "socket-id is not supported");
759 if (props->has_die_id && !slot->props.has_die_id) {
760 error_setg(errp, "die-id is not supported");
764 /* skip slots with explicit mismatch */
765 if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
769 if (props->has_core_id && props->core_id != slot->props.core_id) {
773 if (props->has_cluster_id &&
774 props->cluster_id != slot->props.cluster_id) {
778 if (props->has_die_id && props->die_id != slot->props.die_id) {
782 if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
786 /* reject assignment if slot is already assigned, for compatibility
787 * of legacy cpu_index mapping with SPAPR core based mapping do not
788 * error out if cpu thread and matched core have the same node-id */
789 if (slot->props.has_node_id &&
790 slot->props.node_id != props->node_id) {
791 error_setg(errp, "CPU is already assigned to node-id: %" PRId64,
792 slot->props.node_id);
796 /* assign slot to node as it's matched '-numa cpu' key */
798 slot->props.node_id = props->node_id;
799 slot->props.has_node_id = props->has_node_id;
801 if (machine->numa_state->hmat_enabled) {
802 if ((numa_info[props->node_id].initiator < MAX_NODES) &&
803 (props->node_id != numa_info[props->node_id].initiator)) {
804 error_setg(errp, "The initiator of CPU NUMA node %" PRId64
805 " should be itself (got %" PRIu16 ")",
806 props->node_id, numa_info[props->node_id].initiator);
809 numa_info[props->node_id].has_cpu = true;
810 numa_info[props->node_id].initiator = props->node_id;
815 error_setg(errp, "no match found");
819 static void machine_get_smp(Object *obj, Visitor *v, const char *name,
820 void *opaque, Error **errp)
822 MachineState *ms = MACHINE(obj);
823 SMPConfiguration *config = &(SMPConfiguration){
824 .has_cpus = true, .cpus = ms->smp.cpus,
825 .has_sockets = true, .sockets = ms->smp.sockets,
826 .has_dies = true, .dies = ms->smp.dies,
827 .has_clusters = true, .clusters = ms->smp.clusters,
828 .has_cores = true, .cores = ms->smp.cores,
829 .has_threads = true, .threads = ms->smp.threads,
830 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
833 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) {
838 static void machine_set_smp(Object *obj, Visitor *v, const char *name,
839 void *opaque, Error **errp)
841 MachineState *ms = MACHINE(obj);
842 g_autoptr(SMPConfiguration) config = NULL;
844 if (!visit_type_SMPConfiguration(v, name, &config, errp)) {
848 machine_parse_smp_config(ms, config, errp);
851 static void machine_get_boot(Object *obj, Visitor *v, const char *name,
852 void *opaque, Error **errp)
854 MachineState *ms = MACHINE(obj);
855 BootConfiguration *config = &ms->boot_config;
856 visit_type_BootConfiguration(v, name, &config, &error_abort);
859 static void machine_free_boot_config(MachineState *ms)
861 g_free(ms->boot_config.order);
862 g_free(ms->boot_config.once);
863 g_free(ms->boot_config.splash);
866 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config)
868 MachineClass *machine_class = MACHINE_GET_CLASS(ms);
870 machine_free_boot_config(ms);
871 ms->boot_config = *config;
872 if (!config->has_order) {
873 ms->boot_config.has_order = true;
874 ms->boot_config.order = g_strdup(machine_class->default_boot_order);
878 static void machine_set_boot(Object *obj, Visitor *v, const char *name,
879 void *opaque, Error **errp)
882 MachineState *ms = MACHINE(obj);
883 BootConfiguration *config = NULL;
885 if (!visit_type_BootConfiguration(v, name, &config, errp)) {
888 if (config->has_order) {
889 validate_bootdevices(config->order, errp);
894 if (config->has_once) {
895 validate_bootdevices(config->once, errp);
901 machine_copy_boot_config(ms, config);
902 /* Strings live in ms->boot_config. */
907 qapi_free_BootConfiguration(config);
910 static void machine_class_init(ObjectClass *oc, void *data)
912 MachineClass *mc = MACHINE_CLASS(oc);
914 /* Default 128 MB as guest ram size */
915 mc->default_ram_size = 128 * MiB;
916 mc->rom_file_has_mr = true;
918 /* numa node memory size aligned on 8MB by default.
919 * On Linux, each node's border has to be 8MB aligned
921 mc->numa_mem_align_shift = 23;
923 object_class_property_add_str(oc, "kernel",
924 machine_get_kernel, machine_set_kernel);
925 object_class_property_set_description(oc, "kernel",
926 "Linux kernel image file");
928 object_class_property_add_str(oc, "initrd",
929 machine_get_initrd, machine_set_initrd);
930 object_class_property_set_description(oc, "initrd",
931 "Linux initial ramdisk file");
933 object_class_property_add_str(oc, "append",
934 machine_get_append, machine_set_append);
935 object_class_property_set_description(oc, "append",
936 "Linux kernel command line");
938 object_class_property_add_str(oc, "dtb",
939 machine_get_dtb, machine_set_dtb);
940 object_class_property_set_description(oc, "dtb",
941 "Linux kernel device tree file");
943 object_class_property_add_str(oc, "dumpdtb",
944 machine_get_dumpdtb, machine_set_dumpdtb);
945 object_class_property_set_description(oc, "dumpdtb",
946 "Dump current dtb to a file and quit");
948 object_class_property_add(oc, "boot", "BootConfiguration",
949 machine_get_boot, machine_set_boot,
951 object_class_property_set_description(oc, "boot",
952 "Boot configuration");
954 object_class_property_add(oc, "smp", "SMPConfiguration",
955 machine_get_smp, machine_set_smp,
957 object_class_property_set_description(oc, "smp",
960 object_class_property_add(oc, "phandle-start", "int",
961 machine_get_phandle_start, machine_set_phandle_start,
963 object_class_property_set_description(oc, "phandle-start",
964 "The first phandle ID we may generate dynamically");
966 object_class_property_add_str(oc, "dt-compatible",
967 machine_get_dt_compatible, machine_set_dt_compatible);
968 object_class_property_set_description(oc, "dt-compatible",
969 "Overrides the \"compatible\" property of the dt root node");
971 object_class_property_add_bool(oc, "dump-guest-core",
972 machine_get_dump_guest_core, machine_set_dump_guest_core);
973 object_class_property_set_description(oc, "dump-guest-core",
974 "Include guest memory in a core dump");
976 object_class_property_add_bool(oc, "mem-merge",
977 machine_get_mem_merge, machine_set_mem_merge);
978 object_class_property_set_description(oc, "mem-merge",
979 "Enable/disable memory merge support");
981 object_class_property_add_bool(oc, "usb",
982 machine_get_usb, machine_set_usb);
983 object_class_property_set_description(oc, "usb",
984 "Set on/off to enable/disable usb");
986 object_class_property_add_bool(oc, "graphics",
987 machine_get_graphics, machine_set_graphics);
988 object_class_property_set_description(oc, "graphics",
989 "Set on/off to enable/disable graphics emulation");
991 object_class_property_add_str(oc, "firmware",
992 machine_get_firmware, machine_set_firmware);
993 object_class_property_set_description(oc, "firmware",
996 object_class_property_add_bool(oc, "suppress-vmdesc",
997 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc);
998 object_class_property_set_description(oc, "suppress-vmdesc",
999 "Set on to disable self-describing migration");
1001 object_class_property_add_link(oc, "confidential-guest-support",
1002 TYPE_CONFIDENTIAL_GUEST_SUPPORT,
1003 offsetof(MachineState, cgs),
1004 machine_check_confidential_guest_support,
1005 OBJ_PROP_LINK_STRONG);
1006 object_class_property_set_description(oc, "confidential-guest-support",
1007 "Set confidential guest scheme to support");
1009 /* For compatibility */
1010 object_class_property_add_str(oc, "memory-encryption",
1011 machine_get_memory_encryption, machine_set_memory_encryption);
1012 object_class_property_set_description(oc, "memory-encryption",
1013 "Set memory encryption object to use");
1015 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND,
1016 offsetof(MachineState, memdev), object_property_allow_set_link,
1017 OBJ_PROP_LINK_STRONG);
1018 object_class_property_set_description(oc, "memory-backend",
1020 "Valid value is ID of hostmem based backend");
1022 object_class_property_add(oc, "memory", "MemorySizeConfiguration",
1023 machine_get_mem, machine_set_mem,
1025 object_class_property_set_description(oc, "memory",
1026 "Memory size configuration");
1029 static void machine_class_base_init(ObjectClass *oc, void *data)
1031 MachineClass *mc = MACHINE_CLASS(oc);
1032 mc->max_cpus = mc->max_cpus ?: 1;
1033 mc->min_cpus = mc->min_cpus ?: 1;
1034 mc->default_cpus = mc->default_cpus ?: 1;
1036 if (!object_class_is_abstract(oc)) {
1037 const char *cname = object_class_get_name(oc);
1038 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
1039 mc->name = g_strndup(cname,
1040 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
1041 mc->compat_props = g_ptr_array_new();
1045 static void machine_initfn(Object *obj)
1047 MachineState *ms = MACHINE(obj);
1048 MachineClass *mc = MACHINE_GET_CLASS(obj);
1050 container_get(obj, "/peripheral");
1051 container_get(obj, "/peripheral-anon");
1053 ms->dump_guest_core = true;
1054 ms->mem_merge = true;
1055 ms->enable_graphics = true;
1056 ms->kernel_cmdline = g_strdup("");
1057 ms->ram_size = mc->default_ram_size;
1058 ms->maxram_size = mc->default_ram_size;
1060 if (mc->nvdimm_supported) {
1061 Object *obj = OBJECT(ms);
1063 ms->nvdimms_state = g_new0(NVDIMMState, 1);
1064 object_property_add_bool(obj, "nvdimm",
1065 machine_get_nvdimm, machine_set_nvdimm);
1066 object_property_set_description(obj, "nvdimm",
1067 "Set on/off to enable/disable "
1068 "NVDIMM instantiation");
1070 object_property_add_str(obj, "nvdimm-persistence",
1071 machine_get_nvdimm_persistence,
1072 machine_set_nvdimm_persistence);
1073 object_property_set_description(obj, "nvdimm-persistence",
1074 "Set NVDIMM persistence"
1075 "Valid values are cpu, mem-ctrl");
1078 if (mc->cxl_supported) {
1079 ms->cxl_devices_state = g_new0(CXLState, 1);
1082 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
1083 ms->numa_state = g_new0(NumaState, 1);
1084 object_property_add_bool(obj, "hmat",
1085 machine_get_hmat, machine_set_hmat);
1086 object_property_set_description(obj, "hmat",
1087 "Set on/off to enable/disable "
1088 "ACPI Heterogeneous Memory Attribute "
1092 /* default to mc->default_cpus */
1093 ms->smp.cpus = mc->default_cpus;
1094 ms->smp.max_cpus = mc->default_cpus;
1095 ms->smp.sockets = 1;
1097 ms->smp.clusters = 1;
1099 ms->smp.threads = 1;
1101 machine_copy_boot_config(ms, &(BootConfiguration){ 0 });
1104 static void machine_finalize(Object *obj)
1106 MachineState *ms = MACHINE(obj);
1108 machine_free_boot_config(ms);
1109 g_free(ms->kernel_filename);
1110 g_free(ms->initrd_filename);
1111 g_free(ms->kernel_cmdline);
1113 g_free(ms->dumpdtb);
1114 g_free(ms->dt_compatible);
1115 g_free(ms->firmware);
1116 g_free(ms->device_memory);
1117 g_free(ms->nvdimms_state);
1118 g_free(ms->numa_state);
1119 g_free(ms->cxl_devices_state);
1122 bool machine_usb(MachineState *machine)
1124 return machine->usb;
1127 int machine_phandle_start(MachineState *machine)
1129 return machine->phandle_start;
1132 bool machine_dump_guest_core(MachineState *machine)
1134 return machine->dump_guest_core;
1137 bool machine_mem_merge(MachineState *machine)
1139 return machine->mem_merge;
1142 static char *cpu_slot_to_string(const CPUArchId *cpu)
1144 GString *s = g_string_new(NULL);
1145 if (cpu->props.has_socket_id) {
1146 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
1148 if (cpu->props.has_die_id) {
1150 g_string_append_printf(s, ", ");
1152 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
1154 if (cpu->props.has_cluster_id) {
1156 g_string_append_printf(s, ", ");
1158 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
1160 if (cpu->props.has_core_id) {
1162 g_string_append_printf(s, ", ");
1164 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id);
1166 if (cpu->props.has_thread_id) {
1168 g_string_append_printf(s, ", ");
1170 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id);
1172 return g_string_free(s, false);
1175 static void numa_validate_initiator(NumaState *numa_state)
1178 NodeInfo *numa_info = numa_state->nodes;
1180 for (i = 0; i < numa_state->num_nodes; i++) {
1181 if (numa_info[i].initiator == MAX_NODES) {
1182 error_report("The initiator of NUMA node %d is missing, use "
1183 "'-numa node,initiator' option to declare it", i);
1187 if (!numa_info[numa_info[i].initiator].present) {
1188 error_report("NUMA node %" PRIu16 " is missing, use "
1189 "'-numa node' option to declare it first",
1190 numa_info[i].initiator);
1194 if (!numa_info[numa_info[i].initiator].has_cpu) {
1195 error_report("The initiator of NUMA node %d is invalid", i);
1201 static void machine_numa_finish_cpu_init(MachineState *machine)
1204 bool default_mapping;
1205 GString *s = g_string_new(NULL);
1206 MachineClass *mc = MACHINE_GET_CLASS(machine);
1207 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
1209 assert(machine->numa_state->num_nodes);
1210 for (i = 0; i < possible_cpus->len; i++) {
1211 if (possible_cpus->cpus[i].props.has_node_id) {
1215 default_mapping = (i == possible_cpus->len);
1217 for (i = 0; i < possible_cpus->len; i++) {
1218 const CPUArchId *cpu_slot = &possible_cpus->cpus[i];
1220 if (!cpu_slot->props.has_node_id) {
1221 /* fetch default mapping from board and enable it */
1222 CpuInstanceProperties props = cpu_slot->props;
1224 props.node_id = mc->get_default_cpu_node_id(machine, i);
1225 if (!default_mapping) {
1226 /* record slots with not set mapping,
1227 * TODO: make it hard error in future */
1228 char *cpu_str = cpu_slot_to_string(cpu_slot);
1229 g_string_append_printf(s, "%sCPU %d [%s]",
1230 s->len ? ", " : "", i, cpu_str);
1233 /* non mapped cpus used to fallback to node 0 */
1237 props.has_node_id = true;
1238 machine_set_cpu_numa_node(machine, &props, &error_fatal);
1242 if (machine->numa_state->hmat_enabled) {
1243 numa_validate_initiator(machine->numa_state);
1246 if (s->len && !qtest_enabled()) {
1247 warn_report("CPU(s) not present in any NUMA nodes: %s",
1249 warn_report("All CPU(s) up to maxcpus should be described "
1250 "in NUMA config, ability to start up with partial NUMA "
1251 "mappings is obsoleted and will be removed in future");
1253 g_string_free(s, true);
1256 MemoryRegion *machine_consume_memdev(MachineState *machine,
1257 HostMemoryBackend *backend)
1259 MemoryRegion *ret = host_memory_backend_get_memory(backend);
1261 if (host_memory_backend_is_mapped(backend)) {
1262 error_report("memory backend %s can't be used multiple times.",
1263 object_get_canonical_path_component(OBJECT(backend)));
1266 host_memory_backend_set_mapped(backend, true);
1267 vmstate_register_ram_global(ret);
1271 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp)
1274 MachineClass *mc = MACHINE_GET_CLASS(ms);
1277 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM);
1279 if (!object_property_set_str(obj, "mem-path", path, errp)) {
1283 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) {
1286 object_property_add_child(object_get_objects_root(), mc->default_ram_id,
1288 /* Ensure backend's memory region name is equal to mc->default_ram_id */
1289 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id",
1293 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) {
1296 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp);
1304 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp)
1306 MachineClass *machine_class = MACHINE_GET_CLASS(machine);
1307 ObjectClass *oc = object_class_by_name(machine->cpu_type);
1310 /* This checkpoint is required by replay to separate prior clock
1311 reading from the other reads, because timer polling functions query
1312 clock values from the log. */
1313 replay_checkpoint(CHECKPOINT_INIT);
1315 if (!xen_enabled()) {
1316 /* On 32-bit hosts, QEMU is limited by virtual address space */
1317 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) {
1318 error_setg(errp, "at most 2047 MB RAM can be simulated");
1323 if (machine->memdev) {
1324 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev),
1325 "size", &error_abort);
1326 if (backend_size != machine->ram_size) {
1327 error_setg(errp, "Machine memory size does not match the size of the memory backend");
1330 } else if (machine_class->default_ram_id && machine->ram_size &&
1331 numa_uses_legacy_mem()) {
1332 if (!create_default_memdev(current_machine, mem_path, errp)) {
1337 if (machine->numa_state) {
1338 numa_complete_configuration(machine);
1339 if (machine->numa_state->num_nodes) {
1340 machine_numa_finish_cpu_init(machine);
1344 if (!machine->ram && machine->memdev) {
1345 machine->ram = machine_consume_memdev(machine, machine->memdev);
1348 /* If the machine supports the valid_cpu_types check and the user
1349 * specified a CPU with -cpu check here that the user CPU is supported.
1351 if (machine_class->valid_cpu_types && machine->cpu_type) {
1354 for (i = 0; machine_class->valid_cpu_types[i]; i++) {
1355 if (object_class_dynamic_cast(oc,
1356 machine_class->valid_cpu_types[i])) {
1357 /* The user specificed CPU is in the valid field, we are
1364 if (!machine_class->valid_cpu_types[i]) {
1365 /* The user specified CPU is not valid */
1366 error_report("Invalid CPU type: %s", machine->cpu_type);
1367 error_printf("The valid types are: %s",
1368 machine_class->valid_cpu_types[0]);
1369 for (i = 1; machine_class->valid_cpu_types[i]; i++) {
1370 error_printf(", %s", machine_class->valid_cpu_types[i]);
1378 /* Check if CPU type is deprecated and warn if so */
1380 if (cc && cc->deprecation_note) {
1381 warn_report("CPU model %s is deprecated -- %s", machine->cpu_type,
1382 cc->deprecation_note);
1387 * With confidential guests, the host can't see the real
1388 * contents of RAM, so there's no point in it trying to merge
1391 machine_set_mem_merge(OBJECT(machine), false, &error_abort);
1394 * Virtio devices can't count on directly accessing guest
1395 * memory, so they need iommu_platform=on to use normal DMA
1396 * mechanisms. That requires also disabling legacy virtio
1397 * support for those virtio pci devices which allow it.
1399 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy",
1401 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform",
1405 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator));
1406 machine_class->init(machine);
1407 phase_advance(PHASE_MACHINE_INITIALIZED);
1410 static NotifierList machine_init_done_notifiers =
1411 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
1413 void qemu_add_machine_init_done_notifier(Notifier *notify)
1415 notifier_list_add(&machine_init_done_notifiers, notify);
1416 if (phase_check(PHASE_MACHINE_READY)) {
1417 notify->notify(notify, NULL);
1421 void qemu_remove_machine_init_done_notifier(Notifier *notify)
1423 notifier_remove(notify);
1426 void qdev_machine_creation_done(void)
1428 cpu_synchronize_all_post_init();
1430 if (current_machine->boot_config.has_once) {
1431 qemu_boot_set(current_machine->boot_config.once, &error_fatal);
1432 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order));
1436 * ok, initial machine setup is done, starting from now we can
1437 * only create hotpluggable devices
1439 phase_advance(PHASE_MACHINE_READY);
1440 qdev_assert_realized_properly();
1442 /* TODO: once all bus devices are qdevified, this should be done
1443 * when bus is created by qdev.c */
1445 * TODO: If we had a main 'reset container' that the whole system
1446 * lived in, we could reset that using the multi-phase reset
1447 * APIs. For the moment, we just reset the sysbus, which will cause
1448 * all devices hanging off it (and all their child buses, recursively)
1449 * to be reset. Note that this will *not* reset any Device objects
1450 * which are not attached to some part of the qbus tree!
1452 qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
1454 notifier_list_notify(&machine_init_done_notifiers, NULL);
1456 if (rom_check_and_register_reset() != 0) {
1462 /* This checkpoint is required by replay to separate prior clock
1463 reading from the other reads, because timer polling functions query
1464 clock values from the log. */
1465 replay_checkpoint(CHECKPOINT_RESET);
1466 qemu_system_reset(SHUTDOWN_CAUSE_NONE);
1467 register_global_state();
1470 static const TypeInfo machine_info = {
1471 .name = TYPE_MACHINE,
1472 .parent = TYPE_OBJECT,
1474 .class_size = sizeof(MachineClass),
1475 .class_init = machine_class_init,
1476 .class_base_init = machine_class_base_init,
1477 .instance_size = sizeof(MachineState),
1478 .instance_init = machine_initfn,
1479 .instance_finalize = machine_finalize,
1482 static void machine_register_types(void)
1484 type_register_static(&machine_info);
1487 type_init(machine_register_types)