2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qemu/datadir.h"
28 #include "qapi/error.h"
29 #include "ui/console.h"
30 #include "ui/pixel_ops.h"
31 #include "hw/loader.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "migration/vmstate.h"
35 #include "qemu/error-report.h"
36 #include "qemu/module.h"
37 #include "qom/object.h"
39 #define TCX_ROM_FILE "QEMU,tcx.bin"
40 #define FCODE_MAX_ROM_SIZE 0x10000
44 #define TCX_DAC_NREGS 16
45 #define TCX_THC_NREGS 0x1000
46 #define TCX_DHC_NREGS 0x4000
47 #define TCX_TEC_NREGS 0x1000
48 #define TCX_ALT_NREGS 0x8000
49 #define TCX_STIP_NREGS 0x800000
50 #define TCX_BLIT_NREGS 0x800000
51 #define TCX_RSTIP_NREGS 0x800000
52 #define TCX_RBLIT_NREGS 0x800000
54 #define TCX_THC_MISC 0x818
55 #define TCX_THC_CURSXY 0x8fc
56 #define TCX_THC_CURSMASK 0x900
57 #define TCX_THC_CURSBITS 0x980
59 #define TYPE_TCX "SUNW,tcx"
60 OBJECT_DECLARE_SIMPLE_TYPE(TCXState, TCX)
63 SysBusDevice parent_obj;
68 uint32_t *vram24, *cplane;
71 MemoryRegion vram_mem;
72 MemoryRegion vram_8bit;
73 MemoryRegion vram_24bit;
76 MemoryRegion vram_cplane;
86 ram_addr_t vram24_offset, cplane_offset;
89 uint32_t palette[260];
90 uint8_t r[260], g[260], b[260];
91 uint16_t width, height, depth;
92 uint8_t dac_index, dac_state;
94 uint32_t cursmask[32];
95 uint32_t cursbits[32];
100 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len)
102 memory_region_set_dirty(&s->vram_mem, addr, len);
104 if (s->depth == 24) {
105 memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4,
107 memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4,
112 static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap,
113 ram_addr_t addr, int len)
117 ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len);
119 if (s->depth == 24) {
120 ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
121 s->vram24_offset + addr * 4, len * 4);
122 ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
123 s->cplane_offset + addr * 4, len * 4);
129 static void update_palette_entries(TCXState *s, int start, int end)
131 DisplaySurface *surface = qemu_console_surface(s->con);
134 for (i = start; i < end; i++) {
135 if (is_surface_bgr(surface)) {
136 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
138 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
141 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
144 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
145 const uint8_t *s, int width)
149 uint32_t *p = (uint32_t *)d;
151 for (x = 0; x < width; x++) {
153 *p++ = s1->palette[val];
157 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d,
162 uint32_t *p = (uint32_t *)d;
165 mask = s1->cursmask[y];
166 bits = s1->cursbits[y];
167 len = MIN(width - s1->cursx, 32);
169 for (x = 0; x < len; x++) {
170 if (mask & 0x80000000) {
171 if (bits & 0x80000000) {
172 *p = s1->palette[259];
174 *p = s1->palette[258];
184 XXX Could be much more optimal:
185 * detect if line/page/whole screen is in 24 bit mode
186 * if destination is also BGR, use memcpy
188 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
189 const uint8_t *s, int width,
190 const uint32_t *cplane,
193 DisplaySurface *surface = qemu_console_surface(s1->con);
196 uint32_t *p = (uint32_t *)d;
198 bgr = is_surface_bgr(surface);
199 for(x = 0; x < width; x++, s++, s24++) {
200 if (be32_to_cpu(*cplane) & 0x03000000) {
201 /* 24-bit direct, BGR order */
208 dval = rgb_to_pixel32bgr(r, g, b);
210 dval = rgb_to_pixel32(r, g, b);
212 /* 8-bit pseudocolor */
214 dval = s1->palette[val];
221 /* Fixed line length 1024 allows us to do nice tricks not possible on
224 static void tcx_update_display(void *opaque)
226 TCXState *ts = opaque;
227 DisplaySurface *surface = qemu_console_surface(ts->con);
229 DirtyBitmapSnapshot *snap = NULL;
230 int y, y_start, dd, ds;
233 if (surface_bits_per_pixel(surface) != 32) {
239 d = surface_data(surface);
241 dd = surface_stride(surface);
244 snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
245 memory_region_size(&ts->vram_mem),
248 for (y = 0; y < ts->height; y++, page += ds) {
249 if (tcx_check_dirty(ts, snap, page, ds)) {
253 tcx_draw_line32(ts, d, s, ts->width);
254 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
255 tcx_draw_cursor32(ts, d, y, ts->width);
259 /* flush to display */
260 dpy_gfx_update(ts->con, 0, y_start,
261 ts->width, y - y_start);
269 /* flush to display */
270 dpy_gfx_update(ts->con, 0, y_start,
271 ts->width, y - y_start);
276 static void tcx24_update_display(void *opaque)
278 TCXState *ts = opaque;
279 DisplaySurface *surface = qemu_console_surface(ts->con);
281 DirtyBitmapSnapshot *snap = NULL;
282 int y, y_start, dd, ds;
284 uint32_t *cptr, *s24;
286 if (surface_bits_per_pixel(surface) != 32) {
292 d = surface_data(surface);
296 dd = surface_stride(surface);
299 snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
300 memory_region_size(&ts->vram_mem),
303 for (y = 0; y < ts->height; y++, page += ds) {
304 if (tcx_check_dirty(ts, snap, page, ds)) {
308 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
309 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
310 tcx_draw_cursor32(ts, d, y, ts->width);
314 /* flush to display */
315 dpy_gfx_update(ts->con, 0, y_start,
316 ts->width, y - y_start);
326 /* flush to display */
327 dpy_gfx_update(ts->con, 0, y_start,
328 ts->width, y - y_start);
333 static void tcx_invalidate_display(void *opaque)
335 TCXState *s = opaque;
337 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
338 qemu_console_resize(s->con, s->width, s->height);
341 static void tcx24_invalidate_display(void *opaque)
343 TCXState *s = opaque;
345 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
346 qemu_console_resize(s->con, s->width, s->height);
349 static int vmstate_tcx_post_load(void *opaque, int version_id)
351 TCXState *s = opaque;
353 update_palette_entries(s, 0, 256);
354 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
358 static const VMStateDescription vmstate_tcx = {
361 .minimum_version_id = 4,
362 .post_load = vmstate_tcx_post_load,
363 .fields = (VMStateField[]) {
364 VMSTATE_UINT16(height, TCXState),
365 VMSTATE_UINT16(width, TCXState),
366 VMSTATE_UINT16(depth, TCXState),
367 VMSTATE_BUFFER(r, TCXState),
368 VMSTATE_BUFFER(g, TCXState),
369 VMSTATE_BUFFER(b, TCXState),
370 VMSTATE_UINT8(dac_index, TCXState),
371 VMSTATE_UINT8(dac_state, TCXState),
372 VMSTATE_END_OF_LIST()
376 static void tcx_reset(DeviceState *d)
378 TCXState *s = TCX(d);
380 /* Initialize palette */
381 memset(s->r, 0, 260);
382 memset(s->g, 0, 260);
383 memset(s->b, 0, 260);
384 s->r[255] = s->g[255] = s->b[255] = 255;
385 s->r[256] = s->g[256] = s->b[256] = 255;
386 s->r[258] = s->g[258] = s->b[258] = 255;
387 update_palette_entries(s, 0, 260);
388 memset(s->vram, 0, MAXX*MAXY);
389 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
393 s->cursx = 0xf000; /* Put cursor off screen */
397 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
400 TCXState *s = opaque;
403 switch (s->dac_state) {
405 val = s->r[s->dac_index] << 24;
409 val = s->g[s->dac_index] << 24;
413 val = s->b[s->dac_index] << 24;
414 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
424 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
427 TCXState *s = opaque;
431 case 0: /* Address */
432 s->dac_index = val >> 24;
435 case 4: /* Pixel colours */
436 case 12: /* Overlay (cursor) colours */
438 index = (s->dac_index & 3) + 256;
440 index = s->dac_index;
442 switch (s->dac_state) {
444 s->r[index] = val >> 24;
445 update_palette_entries(s, index, index + 1);
449 s->g[index] = val >> 24;
450 update_palette_entries(s, index, index + 1);
454 s->b[index] = val >> 24;
455 update_palette_entries(s, index, index + 1);
456 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
463 default: /* Control registers */
468 static const MemoryRegionOps tcx_dac_ops = {
469 .read = tcx_dac_readl,
470 .write = tcx_dac_writel,
471 .endianness = DEVICE_NATIVE_ENDIAN,
473 .min_access_size = 4,
474 .max_access_size = 4,
478 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr,
484 static void tcx_stip_writel(void *opaque, hwaddr addr,
485 uint64_t val, unsigned size)
487 TCXState *s = opaque;
494 addr = (addr >> 3) & 0xfffff;
495 col = cpu_to_be32(s->tmpblit);
496 if (s->depth == 24) {
497 for (i = 0; i < 32; i++) {
498 if (val & 0x80000000) {
499 s->vram[addr + i] = s->tmpblit;
500 s->vram24[addr + i] = col;
505 for (i = 0; i < 32; i++) {
506 if (val & 0x80000000) {
507 s->vram[addr + i] = s->tmpblit;
512 tcx_set_dirty(s, addr, 32);
516 static void tcx_rstip_writel(void *opaque, hwaddr addr,
517 uint64_t val, unsigned size)
519 TCXState *s = opaque;
526 addr = (addr >> 3) & 0xfffff;
527 col = cpu_to_be32(s->tmpblit);
528 if (s->depth == 24) {
529 for (i = 0; i < 32; i++) {
530 if (val & 0x80000000) {
531 s->vram[addr + i] = s->tmpblit;
532 s->vram24[addr + i] = col;
533 s->cplane[addr + i] = col;
538 for (i = 0; i < 32; i++) {
539 if (val & 0x80000000) {
540 s->vram[addr + i] = s->tmpblit;
545 tcx_set_dirty(s, addr, 32);
549 static const MemoryRegionOps tcx_stip_ops = {
550 .read = tcx_stip_readl,
551 .write = tcx_stip_writel,
552 .endianness = DEVICE_NATIVE_ENDIAN,
554 .min_access_size = 4,
555 .max_access_size = 4,
558 .min_access_size = 4,
559 .max_access_size = 8,
563 static const MemoryRegionOps tcx_rstip_ops = {
564 .read = tcx_stip_readl,
565 .write = tcx_rstip_writel,
566 .endianness = DEVICE_NATIVE_ENDIAN,
568 .min_access_size = 4,
569 .max_access_size = 4,
572 .min_access_size = 4,
573 .max_access_size = 8,
577 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
583 static void tcx_blit_writel(void *opaque, hwaddr addr,
584 uint64_t val, unsigned size)
586 TCXState *s = opaque;
593 addr = (addr >> 3) & 0xfffff;
594 adsr = val & 0xffffff;
595 len = ((val >> 24) & 0x1f) + 1;
596 if (adsr == 0xffffff) {
597 memset(&s->vram[addr], s->tmpblit, len);
598 if (s->depth == 24) {
599 val = s->tmpblit & 0xffffff;
600 val = cpu_to_be32(val);
601 for (i = 0; i < len; i++) {
602 s->vram24[addr + i] = val;
606 memcpy(&s->vram[addr], &s->vram[adsr], len);
607 if (s->depth == 24) {
608 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
611 tcx_set_dirty(s, addr, len);
615 static void tcx_rblit_writel(void *opaque, hwaddr addr,
616 uint64_t val, unsigned size)
618 TCXState *s = opaque;
625 addr = (addr >> 3) & 0xfffff;
626 adsr = val & 0xffffff;
627 len = ((val >> 24) & 0x1f) + 1;
628 if (adsr == 0xffffff) {
629 memset(&s->vram[addr], s->tmpblit, len);
630 if (s->depth == 24) {
631 val = s->tmpblit & 0xffffff;
632 val = cpu_to_be32(val);
633 for (i = 0; i < len; i++) {
634 s->vram24[addr + i] = val;
635 s->cplane[addr + i] = val;
639 memcpy(&s->vram[addr], &s->vram[adsr], len);
640 if (s->depth == 24) {
641 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
642 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4);
645 tcx_set_dirty(s, addr, len);
649 static const MemoryRegionOps tcx_blit_ops = {
650 .read = tcx_blit_readl,
651 .write = tcx_blit_writel,
652 .endianness = DEVICE_NATIVE_ENDIAN,
654 .min_access_size = 4,
655 .max_access_size = 4,
658 .min_access_size = 4,
659 .max_access_size = 8,
663 static const MemoryRegionOps tcx_rblit_ops = {
664 .read = tcx_blit_readl,
665 .write = tcx_rblit_writel,
666 .endianness = DEVICE_NATIVE_ENDIAN,
668 .min_access_size = 4,
669 .max_access_size = 4,
672 .min_access_size = 4,
673 .max_access_size = 8,
677 static void tcx_invalidate_cursor_position(TCXState *s)
679 int ymin, ymax, start, end;
681 /* invalidate only near the cursor */
683 if (ymin >= s->height) {
686 ymax = MIN(s->height, ymin + 32);
690 tcx_set_dirty(s, start, end - start);
693 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr,
696 TCXState *s = opaque;
699 if (addr == TCX_THC_MISC) {
700 val = s->thcmisc | 0x02000000;
707 static void tcx_thc_writel(void *opaque, hwaddr addr,
708 uint64_t val, unsigned size)
710 TCXState *s = opaque;
712 if (addr == TCX_THC_CURSXY) {
713 tcx_invalidate_cursor_position(s);
714 s->cursx = val >> 16;
716 tcx_invalidate_cursor_position(s);
717 } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) {
718 s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val;
719 tcx_invalidate_cursor_position(s);
720 } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) {
721 s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val;
722 tcx_invalidate_cursor_position(s);
723 } else if (addr == TCX_THC_MISC) {
729 static const MemoryRegionOps tcx_thc_ops = {
730 .read = tcx_thc_readl,
731 .write = tcx_thc_writel,
732 .endianness = DEVICE_NATIVE_ENDIAN,
734 .min_access_size = 4,
735 .max_access_size = 4,
739 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr,
745 static void tcx_dummy_writel(void *opaque, hwaddr addr,
746 uint64_t val, unsigned size)
751 static const MemoryRegionOps tcx_dummy_ops = {
752 .read = tcx_dummy_readl,
753 .write = tcx_dummy_writel,
754 .endianness = DEVICE_NATIVE_ENDIAN,
756 .min_access_size = 4,
757 .max_access_size = 4,
761 static const GraphicHwOps tcx_ops = {
762 .invalidate = tcx_invalidate_display,
763 .gfx_update = tcx_update_display,
766 static const GraphicHwOps tcx24_ops = {
767 .invalidate = tcx24_invalidate_display,
768 .gfx_update = tcx24_update_display,
771 static void tcx_initfn(Object *obj)
773 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
774 TCXState *s = TCX(obj);
776 memory_region_init_rom_nomigrate(&s->rom, obj, "tcx.prom",
777 FCODE_MAX_ROM_SIZE, &error_fatal);
778 sysbus_init_mmio(sbd, &s->rom);
780 /* 2/STIP : Stippler */
781 memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip",
783 sysbus_init_mmio(sbd, &s->stip);
785 /* 3/BLIT : Blitter */
786 memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit",
788 sysbus_init_mmio(sbd, &s->blit);
790 /* 5/RSTIP : Raw Stippler */
791 memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip",
793 sysbus_init_mmio(sbd, &s->rstip);
795 /* 6/RBLIT : Raw Blitter */
796 memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit",
798 sysbus_init_mmio(sbd, &s->rblit);
801 memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec",
803 sysbus_init_mmio(sbd, &s->tec);
806 memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac",
808 sysbus_init_mmio(sbd, &s->dac);
811 memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc",
813 sysbus_init_mmio(sbd, &s->thc);
816 memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc",
818 sysbus_init_mmio(sbd, &s->dhc);
821 memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt",
823 sysbus_init_mmio(sbd, &s->alt);
826 static void tcx_realizefn(DeviceState *dev, Error **errp)
828 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
829 TCXState *s = TCX(dev);
830 ram_addr_t vram_offset = 0;
833 char *fcode_filename;
835 memory_region_init_ram_nomigrate(&s->vram_mem, OBJECT(s), "tcx.vram",
836 s->vram_size * (1 + 4 + 4), &error_fatal);
837 vmstate_register_ram_global(&s->vram_mem);
838 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
839 vram_base = memory_region_get_ram_ptr(&s->vram_mem);
841 /* 10/ROM : FCode ROM */
842 vmstate_register_ram_global(&s->rom);
843 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
844 if (fcode_filename) {
845 ret = load_image_mr(fcode_filename, &s->rom);
846 g_free(fcode_filename);
847 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
848 warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE);
852 /* 0/DFB8 : 8-bit plane */
855 memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
856 &s->vram_mem, vram_offset, size);
857 sysbus_init_mmio(sbd, &s->vram_8bit);
861 /* 1/DFB24 : 24bit plane */
862 size = s->vram_size * 4;
863 s->vram24 = (uint32_t *)vram_base;
864 s->vram24_offset = vram_offset;
865 memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
866 &s->vram_mem, vram_offset, size);
867 sysbus_init_mmio(sbd, &s->vram_24bit);
871 /* 4/RDFB32 : Raw Framebuffer */
872 size = s->vram_size * 4;
873 s->cplane = (uint32_t *)vram_base;
874 s->cplane_offset = vram_offset;
875 memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
876 &s->vram_mem, vram_offset, size);
877 sysbus_init_mmio(sbd, &s->vram_cplane);
879 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
881 memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s,
882 "tcx.thc24", TCX_THC_NREGS);
883 sysbus_init_mmio(sbd, &s->thc24);
886 sysbus_init_irq(sbd, &s->irq);
889 s->con = graphic_console_init(dev, 0, &tcx_ops, s);
891 s->con = graphic_console_init(dev, 0, &tcx24_ops, s);
895 qemu_console_resize(s->con, s->width, s->height);
898 static Property tcx_properties[] = {
899 DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1),
900 DEFINE_PROP_UINT16("width", TCXState, width, -1),
901 DEFINE_PROP_UINT16("height", TCXState, height, -1),
902 DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
903 DEFINE_PROP_END_OF_LIST(),
906 static void tcx_class_init(ObjectClass *klass, void *data)
908 DeviceClass *dc = DEVICE_CLASS(klass);
910 dc->realize = tcx_realizefn;
911 dc->reset = tcx_reset;
912 dc->vmsd = &vmstate_tcx;
913 device_class_set_props(dc, tcx_properties);
916 static const TypeInfo tcx_info = {
918 .parent = TYPE_SYS_BUS_DEVICE,
919 .instance_size = sizeof(TCXState),
920 .instance_init = tcx_initfn,
921 .class_init = tcx_class_init,
924 static void tcx_register_types(void)
926 type_register_static(&tcx_info);
929 type_init(tcx_register_types)