2 * TI OMAP DMA gigacell.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/timer.h"
23 #include "hw/arm/omap.h"
25 #include "hw/arm/soc_dma.h"
27 struct omap_dma_channel_s {
34 enum omap_dma_port port[2];
36 omap_dma_addressing_t mode[2];
39 int32_t frame_index[2];
40 int16_t element_index[2];
49 /* auto init and linked channel data */
56 /* interruption data */
76 int omap_3_1_compatible_disable;
79 struct omap_dma_channel_s *sibling;
81 struct omap_dma_reg_set_s {
93 struct soc_dma_ch_s *dma;
95 /* unused parameters */
98 int interleave_disabled;
105 struct soc_dma_s *dma;
108 struct omap_mpu_state_s *mpu;
111 void (*intr_update)(struct omap_dma_s *s);
112 enum omap_dma_model model;
113 int omap_3_1_mapping_disabled;
122 struct omap_dma_channel_s ch[32];
123 struct omap_dma_lcd_channel_s lcd_ch;
127 #define TIMEOUT_INTR (1 << 0)
128 #define EVENT_DROP_INTR (1 << 1)
129 #define HALF_FRAME_INTR (1 << 2)
130 #define END_FRAME_INTR (1 << 3)
131 #define LAST_FRAME_INTR (1 << 4)
132 #define END_BLOCK_INTR (1 << 5)
133 #define SYNC (1 << 6)
134 #define END_PKT_INTR (1 << 7)
135 #define TRANS_ERR_INTR (1 << 8)
136 #define MISALIGN_INTR (1 << 11)
138 static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
143 static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
145 struct omap_dma_reg_set_s *a = &ch->active_set;
147 int omap_3_1 = !ch->omap_3_1_compatible_disable;
150 * TODO: verify address ranges and alignment
151 * TODO: port endianness
154 a->src = ch->addr[0];
155 a->dest = ch->addr[1];
156 a->frames = ch->frames;
157 a->elements = ch->elements;
158 a->pck_elements = ch->frame_index[!ch->src_sync];
163 if (unlikely(!ch->elements || !ch->frames)) {
164 printf("%s: bad DMA request\n", __func__);
168 for (i = 0; i < 2; i ++)
169 switch (ch->mode[i]) {
171 a->elem_delta[i] = 0;
172 a->frame_delta[i] = 0;
174 case post_incremented:
175 a->elem_delta[i] = ch->data_type;
176 a->frame_delta[i] = 0;
179 a->elem_delta[i] = ch->data_type +
180 ch->element_index[omap_3_1 ? 0 : i] - 1;
181 a->frame_delta[i] = 0;
184 a->elem_delta[i] = ch->data_type +
185 ch->element_index[omap_3_1 ? 0 : i] - 1;
186 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
187 ch->element_index[omap_3_1 ? 0 : i];
193 normal = !ch->transparent_copy && !ch->constant_fill &&
194 /* FIFO is big-endian so either (ch->endian[n] == 1) OR
195 * (ch->endian_lock[n] == 1) mean no endianism conversion. */
196 (ch->endian[0] | ch->endian_lock[0]) ==
197 (ch->endian[1] | ch->endian_lock[1]);
198 for (i = 0; i < 2; i ++) {
199 /* TODO: for a->frame_delta[i] > 0 still use the fast path, just
200 * limit min_elems in omap_dma_transfer_setup to the nearest frame
202 if (!a->elem_delta[i] && normal &&
203 (a->frames == 1 || !a->frame_delta[i]))
204 ch->dma->type[i] = soc_dma_access_const;
205 else if (a->elem_delta[i] == ch->data_type && normal &&
206 (a->frames == 1 || !a->frame_delta[i]))
207 ch->dma->type[i] = soc_dma_access_linear;
209 ch->dma->type[i] = soc_dma_access_other;
211 ch->dma->vaddr[i] = ch->addr[i];
213 soc_dma_ch_update(ch->dma);
216 static void omap_dma_activate_channel(struct omap_dma_s *s,
217 struct omap_dma_channel_s *ch)
220 if (ch->set_update) {
221 /* It's not clear when the active set is supposed to be
222 * loaded from registers. We're already loading it when the
223 * channel is enabled, and for some guests this is not enough
224 * but that may be also because of a race condition (no
225 * delays in qemu) in the guest code, which we're just
226 * working around here. */
227 omap_dma_channel_load(ch);
232 soc_dma_set_request(ch->dma, 1);
238 static void omap_dma_deactivate_channel(struct omap_dma_s *s,
239 struct omap_dma_channel_s *ch)
242 ch->cpc = ch->active_set.dest & 0xffff;
244 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
245 /* Don't deactivate the channel */
246 ch->pending_request = 0;
250 /* Don't deactivate the channel if it is synchronized and the DMA request is
252 if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync)))
258 soc_dma_set_request(ch->dma, 0);
262 static void omap_dma_enable_channel(struct omap_dma_s *s,
263 struct omap_dma_channel_s *ch)
267 ch->waiting_end_prog = 0;
268 omap_dma_channel_load(ch);
269 /* TODO: theoretically if ch->sync && ch->prefetch &&
270 * !s->dma->drqbmp[ch->sync], we should also activate and fetch
271 * from source and then stall until signalled. */
272 if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) {
273 omap_dma_activate_channel(s, ch);
278 static void omap_dma_disable_channel(struct omap_dma_s *s,
279 struct omap_dma_channel_s *ch)
283 /* Discard any pending request */
284 ch->pending_request = 0;
285 omap_dma_deactivate_channel(s, ch);
289 static void omap_dma_channel_end_prog(struct omap_dma_s *s,
290 struct omap_dma_channel_s *ch)
292 if (ch->waiting_end_prog) {
293 ch->waiting_end_prog = 0;
294 if (!ch->sync || ch->pending_request) {
295 ch->pending_request = 0;
296 omap_dma_activate_channel(s, ch);
301 static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
303 struct omap_dma_channel_s *ch = s->ch;
305 /* First three interrupts are shared between two channels each. */
306 if (ch[0].status | ch[6].status)
307 qemu_irq_raise(ch[0].irq);
308 if (ch[1].status | ch[7].status)
309 qemu_irq_raise(ch[1].irq);
310 if (ch[2].status | ch[8].status)
311 qemu_irq_raise(ch[2].irq);
313 qemu_irq_raise(ch[3].irq);
315 qemu_irq_raise(ch[4].irq);
317 qemu_irq_raise(ch[5].irq);
320 static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
322 struct omap_dma_channel_s *ch = s->ch;
325 for (i = s->chans; i; ch ++, i --)
327 qemu_irq_raise(ch->irq);
330 static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
332 s->omap_3_1_mapping_disabled = 0;
334 s->intr_update = omap_dma_interrupts_3_1_update;
337 static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
339 s->omap_3_1_mapping_disabled = 1;
341 s->intr_update = omap_dma_interrupts_3_2_update;
344 static void omap_dma_process_request(struct omap_dma_s *s, int request)
348 struct omap_dma_channel_s *ch = s->ch;
350 for (channel = 0; channel < s->chans; channel ++, ch ++) {
351 if (ch->enable && ch->sync == request) {
353 omap_dma_activate_channel(s, ch);
354 else if (!ch->pending_request)
355 ch->pending_request = 1;
357 /* Request collision */
358 /* Second request received while processing other request */
359 ch->status |= EVENT_DROP_INTR;
366 omap_dma_interrupts_update(s);
369 static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
372 struct omap_dma_channel_s *ch = dma->opaque;
373 struct omap_dma_reg_set_s *a = &ch->active_set;
374 int bytes = dma->bytes;
376 uint16_t status = ch->status;
380 /* Transfer a single element */
381 /* FIXME: check the endianness */
382 if (!ch->constant_fill)
383 cpu_physical_memory_read(a->src, value, ch->data_type);
385 *(uint32_t *) value = ch->color;
387 if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
388 cpu_physical_memory_write(a->dest, value, ch->data_type);
390 a->src += a->elem_delta[0];
391 a->dest += a->elem_delta[1];
395 if (a->element == a->elements) {
398 a->src += a->frame_delta[0];
399 a->dest += a->frame_delta[1];
402 /* If the channel is async, update cpc */
404 ch->cpc = a->dest & 0xffff;
406 } while ((bytes -= ch->data_type));
408 /* If the channel is element synchronized, deactivate it */
409 if (ch->sync && !ch->fs && !ch->bs)
410 omap_dma_deactivate_channel(s, ch);
412 /* If it is the last frame, set the LAST_FRAME interrupt */
413 if (a->element == 1 && a->frame == a->frames - 1)
414 if (ch->interrupts & LAST_FRAME_INTR)
415 ch->status |= LAST_FRAME_INTR;
417 /* If the half of the frame was reached, set the HALF_FRAME
419 if (a->element == (a->elements >> 1))
420 if (ch->interrupts & HALF_FRAME_INTR)
421 ch->status |= HALF_FRAME_INTR;
423 if (ch->fs && ch->bs) {
425 /* Check if a full packet has been transferred. */
426 if (a->pck_element == a->pck_elements) {
429 /* Set the END_PKT interrupt */
430 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
431 ch->status |= END_PKT_INTR;
433 /* If the channel is packet-synchronized, deactivate it */
435 omap_dma_deactivate_channel(s, ch);
439 if (a->element == a->elements) {
442 a->src += a->frame_delta[0];
443 a->dest += a->frame_delta[1];
446 /* If the channel is frame synchronized, deactivate it */
447 if (ch->sync && ch->fs && !ch->bs)
448 omap_dma_deactivate_channel(s, ch);
450 /* If the channel is async, update cpc */
452 ch->cpc = a->dest & 0xffff;
454 /* Set the END_FRAME interrupt */
455 if (ch->interrupts & END_FRAME_INTR)
456 ch->status |= END_FRAME_INTR;
458 if (a->frame == a->frames) {
460 /* Disable the channel */
462 if (ch->omap_3_1_compatible_disable) {
463 omap_dma_disable_channel(s, ch);
464 if (ch->link_enabled)
465 omap_dma_enable_channel(s,
466 &s->ch[ch->link_next_ch]);
469 omap_dma_disable_channel(s, ch);
470 else if (ch->repeat || ch->end_prog)
471 omap_dma_channel_load(ch);
473 ch->waiting_end_prog = 1;
474 omap_dma_deactivate_channel(s, ch);
478 if (ch->interrupts & END_BLOCK_INTR)
479 ch->status |= END_BLOCK_INTR;
482 } while (status == ch->status && ch->active);
484 omap_dma_interrupts_update(s);
489 omap_dma_intr_element_sync,
490 omap_dma_intr_last_frame,
491 omap_dma_intr_half_frame,
493 omap_dma_intr_frame_sync,
494 omap_dma_intr_packet,
495 omap_dma_intr_packet_sync,
497 __omap_dma_intr_last,
500 static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)
502 struct omap_dma_port_if_s *src_p, *dest_p;
503 struct omap_dma_reg_set_s *a;
504 struct omap_dma_channel_s *ch = dma->opaque;
505 struct omap_dma_s *s = dma->dma->opaque;
506 int frames, min_elems, elements[__omap_dma_intr_last];
510 src_p = &s->mpu->port[ch->port[0]];
511 dest_p = &s->mpu->port[ch->port[1]];
512 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
513 (!dest_p->addr_valid(s->mpu, a->dest))) {
516 if (ch->interrupts & TIMEOUT_INTR)
517 ch->status |= TIMEOUT_INTR;
518 omap_dma_deactivate_channel(s, ch);
521 printf("%s: Bus time-out in DMA%i operation\n",
527 /* Check all the conditions that terminate the transfer starting
528 * with those that can occur the soonest. */
529 #define INTR_CHECK(cond, id, nelements) \
531 elements[id] = nelements; \
532 if (elements[id] < min_elems) \
533 min_elems = elements[id]; \
535 elements[id] = INT_MAX;
539 ch->sync && !ch->fs && !ch->bs,
540 omap_dma_intr_element_sync,
544 /* TODO: for transfers where entire frames can be read and written
545 * using memcpy() but a->frame_delta is non-zero, try to still do
546 * transfers using soc_dma but limit min_elems to a->elements - ...
547 * See also the TODO in omap_dma_channel_load. */
549 (ch->interrupts & LAST_FRAME_INTR) &&
550 ((a->frame < a->frames - 1) || !a->element),
551 omap_dma_intr_last_frame,
552 (a->frames - a->frame - 2) * a->elements +
553 (a->elements - a->element + 1))
555 ch->interrupts & HALF_FRAME_INTR,
556 omap_dma_intr_half_frame,
558 (a->element >= (a->elements >> 1) ? a->elements : 0) -
561 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
563 a->elements - a->element)
565 ch->sync && ch->fs && !ch->bs,
566 omap_dma_intr_frame_sync,
567 a->elements - a->element)
572 (ch->interrupts & END_PKT_INTR) && !ch->src_sync,
573 omap_dma_intr_packet,
574 a->pck_elements - a->pck_element)
576 ch->fs && ch->bs && ch->sync,
577 omap_dma_intr_packet_sync,
578 a->pck_elements - a->pck_element)
584 (a->frames - a->frame - 1) * a->elements +
585 (a->elements - a->element))
587 dma->bytes = min_elems * ch->data_type;
589 /* Set appropriate interrupts and/or deactivate channels */
592 /* TODO: should all of this only be done if dma->update, and otherwise
593 * inside omap_dma_transfer_generic below - check what's faster. */
597 /* If the channel is element synchronized, deactivate it */
598 if (min_elems == elements[omap_dma_intr_element_sync])
599 omap_dma_deactivate_channel(s, ch);
601 /* If it is the last frame, set the LAST_FRAME interrupt */
602 if (min_elems == elements[omap_dma_intr_last_frame])
603 ch->status |= LAST_FRAME_INTR;
605 /* If exactly half of the frame was reached, set the HALF_FRAME
607 if (min_elems == elements[omap_dma_intr_half_frame])
608 ch->status |= HALF_FRAME_INTR;
610 /* If a full packet has been transferred, set the END_PKT interrupt */
611 if (min_elems == elements[omap_dma_intr_packet])
612 ch->status |= END_PKT_INTR;
614 /* If the channel is packet-synchronized, deactivate it */
615 if (min_elems == elements[omap_dma_intr_packet_sync])
616 omap_dma_deactivate_channel(s, ch);
618 /* If the channel is frame synchronized, deactivate it */
619 if (min_elems == elements[omap_dma_intr_frame_sync])
620 omap_dma_deactivate_channel(s, ch);
622 /* Set the END_FRAME interrupt */
623 if (min_elems == elements[omap_dma_intr_frame])
624 ch->status |= END_FRAME_INTR;
626 if (min_elems == elements[omap_dma_intr_block]) {
628 /* Disable the channel */
630 if (ch->omap_3_1_compatible_disable) {
631 omap_dma_disable_channel(s, ch);
632 if (ch->link_enabled)
633 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
636 omap_dma_disable_channel(s, ch);
637 else if (ch->repeat || ch->end_prog)
638 omap_dma_channel_load(ch);
640 ch->waiting_end_prog = 1;
641 omap_dma_deactivate_channel(s, ch);
645 if (ch->interrupts & END_BLOCK_INTR)
646 ch->status |= END_BLOCK_INTR;
649 /* Update packet number */
650 if (ch->fs && ch->bs) {
651 a->pck_element += min_elems;
652 a->pck_element %= a->pck_elements;
655 /* TODO: check if we really need to update anything here or perhaps we
656 * can skip part of this. */
660 a->element += min_elems;
662 frames = a->element / a->elements;
663 a->element = a->element % a->elements;
665 a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
666 a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];
668 /* If the channel is async, update cpc */
669 if (!ch->sync && frames)
670 ch->cpc = a->dest & 0xffff;
672 /* TODO: if the destination port is IMIF or EMIFF, set the dirty
680 omap_dma_interrupts_update(s);
683 void omap_dma_reset(struct soc_dma_s *dma)
686 struct omap_dma_s *s = dma->opaque;
688 soc_dma_reset(s->dma);
689 if (s->model < omap_dma_4)
694 memset(&s->irqstat, 0, sizeof(s->irqstat));
695 memset(&s->irqen, 0, sizeof(s->irqen));
696 s->lcd_ch.src = emiff;
697 s->lcd_ch.condition = 0;
698 s->lcd_ch.interrupts = 0;
700 if (s->model < omap_dma_4)
701 omap_dma_enable_3_1_mapping(s);
702 for (i = 0; i < s->chans; i ++) {
703 s->ch[i].suspend = 0;
704 s->ch[i].prefetch = 0;
705 s->ch[i].buf_disable = 0;
706 s->ch[i].src_sync = 0;
707 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
708 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
709 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
710 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
711 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
712 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
713 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
714 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
715 s->ch[i].write_mode = 0;
716 s->ch[i].data_type = 0;
717 s->ch[i].transparent_copy = 0;
718 s->ch[i].constant_fill = 0;
719 s->ch[i].color = 0x00000000;
720 s->ch[i].end_prog = 0;
722 s->ch[i].auto_init = 0;
723 s->ch[i].link_enabled = 0;
724 if (s->model < omap_dma_4)
725 s->ch[i].interrupts = 0x0003;
727 s->ch[i].interrupts = 0x0000;
729 s->ch[i].cstatus = 0;
733 s->ch[i].pending_request = 0;
734 s->ch[i].waiting_end_prog = 0;
735 s->ch[i].cpc = 0x0000;
738 s->ch[i].omap_3_1_compatible_disable = 0;
739 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
740 s->ch[i].priority = 0;
741 s->ch[i].interleave_disabled = 0;
746 static int omap_dma_ch_reg_read(struct omap_dma_s *s,
747 struct omap_dma_channel_s *ch, int reg, uint16_t *value)
750 case 0x00: /* SYS_DMA_CSDP_CH0 */
751 *value = (ch->burst[1] << 14) |
752 (ch->pack[1] << 13) |
754 (ch->burst[0] << 7) |
757 (ch->data_type >> 1);
760 case 0x02: /* SYS_DMA_CCR_CH0 */
761 if (s->model <= omap_dma_3_1)
762 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
764 *value = ch->omap_3_1_compatible_disable << 10;
765 *value |= (ch->mode[1] << 14) |
766 (ch->mode[0] << 12) |
767 (ch->end_prog << 11) |
769 (ch->auto_init << 8) |
771 (ch->priority << 6) |
772 (ch->fs << 5) | ch->sync;
775 case 0x04: /* SYS_DMA_CICR_CH0 */
776 *value = ch->interrupts;
779 case 0x06: /* SYS_DMA_CSR_CH0 */
782 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
783 *value |= (ch->sibling->status & 0x3f) << 6;
784 ch->sibling->status &= SYNC;
786 qemu_irq_lower(ch->irq);
789 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
790 *value = ch->addr[0] & 0x0000ffff;
793 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
794 *value = ch->addr[0] >> 16;
797 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
798 *value = ch->addr[1] & 0x0000ffff;
801 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
802 *value = ch->addr[1] >> 16;
805 case 0x10: /* SYS_DMA_CEN_CH0 */
806 *value = ch->elements;
809 case 0x12: /* SYS_DMA_CFN_CH0 */
813 case 0x14: /* SYS_DMA_CFI_CH0 */
814 *value = ch->frame_index[0];
817 case 0x16: /* SYS_DMA_CEI_CH0 */
818 *value = ch->element_index[0];
821 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
822 if (ch->omap_3_1_compatible_disable)
823 *value = ch->active_set.src & 0xffff; /* CSAC */
828 case 0x1a: /* DMA_CDAC */
829 *value = ch->active_set.dest & 0xffff; /* CDAC */
832 case 0x1c: /* DMA_CDEI */
833 *value = ch->element_index[1];
836 case 0x1e: /* DMA_CDFI */
837 *value = ch->frame_index[1];
840 case 0x20: /* DMA_COLOR_L */
841 *value = ch->color & 0xffff;
844 case 0x22: /* DMA_COLOR_U */
845 *value = ch->color >> 16;
848 case 0x24: /* DMA_CCR2 */
849 *value = (ch->bs << 2) |
850 (ch->transparent_copy << 1) |
854 case 0x28: /* DMA_CLNK_CTRL */
855 *value = (ch->link_enabled << 15) |
856 (ch->link_next_ch & 0xf);
859 case 0x2a: /* DMA_LCH_CTRL */
860 *value = (ch->interleave_disabled << 15) |
870 static int omap_dma_ch_reg_write(struct omap_dma_s *s,
871 struct omap_dma_channel_s *ch, int reg, uint16_t value)
874 case 0x00: /* SYS_DMA_CSDP_CH0 */
875 ch->burst[1] = (value & 0xc000) >> 14;
876 ch->pack[1] = (value & 0x2000) >> 13;
877 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
878 ch->burst[0] = (value & 0x0180) >> 7;
879 ch->pack[0] = (value & 0x0040) >> 6;
880 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
881 if (ch->port[0] >= __omap_dma_port_last) {
882 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA port %i\n",
883 __func__, ch->port[0]);
885 if (ch->port[1] >= __omap_dma_port_last) {
886 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA port %i\n",
887 __func__, ch->port[1]);
889 ch->data_type = 1 << (value & 3);
890 if ((value & 3) == 3) {
891 qemu_log_mask(LOG_GUEST_ERROR,
892 "%s: bad data_type for DMA channel\n", __func__);
897 case 0x02: /* SYS_DMA_CCR_CH0 */
898 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
899 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
900 ch->end_prog = (value & 0x0800) >> 11;
901 if (s->model >= omap_dma_3_2)
902 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
903 ch->repeat = (value & 0x0200) >> 9;
904 ch->auto_init = (value & 0x0100) >> 8;
905 ch->priority = (value & 0x0040) >> 6;
906 ch->fs = (value & 0x0020) >> 5;
907 ch->sync = value & 0x001f;
910 omap_dma_enable_channel(s, ch);
912 omap_dma_disable_channel(s, ch);
915 omap_dma_channel_end_prog(s, ch);
919 case 0x04: /* SYS_DMA_CICR_CH0 */
920 ch->interrupts = value & 0x3f;
923 case 0x06: /* SYS_DMA_CSR_CH0 */
924 OMAP_RO_REG((hwaddr) reg);
927 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
928 ch->addr[0] &= 0xffff0000;
929 ch->addr[0] |= value;
932 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
933 ch->addr[0] &= 0x0000ffff;
934 ch->addr[0] |= (uint32_t) value << 16;
937 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
938 ch->addr[1] &= 0xffff0000;
939 ch->addr[1] |= value;
942 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
943 ch->addr[1] &= 0x0000ffff;
944 ch->addr[1] |= (uint32_t) value << 16;
947 case 0x10: /* SYS_DMA_CEN_CH0 */
948 ch->elements = value;
951 case 0x12: /* SYS_DMA_CFN_CH0 */
955 case 0x14: /* SYS_DMA_CFI_CH0 */
956 ch->frame_index[0] = (int16_t) value;
959 case 0x16: /* SYS_DMA_CEI_CH0 */
960 ch->element_index[0] = (int16_t) value;
963 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
964 OMAP_RO_REG((hwaddr) reg);
967 case 0x1c: /* DMA_CDEI */
968 ch->element_index[1] = (int16_t) value;
971 case 0x1e: /* DMA_CDFI */
972 ch->frame_index[1] = (int16_t) value;
975 case 0x20: /* DMA_COLOR_L */
976 ch->color &= 0xffff0000;
980 case 0x22: /* DMA_COLOR_U */
982 ch->color |= (uint32_t)value << 16;
985 case 0x24: /* DMA_CCR2 */
986 ch->bs = (value >> 2) & 0x1;
987 ch->transparent_copy = (value >> 1) & 0x1;
988 ch->constant_fill = value & 0x1;
991 case 0x28: /* DMA_CLNK_CTRL */
992 ch->link_enabled = (value >> 15) & 0x1;
993 if (value & (1 << 14)) { /* Stop_Lnk */
994 ch->link_enabled = 0;
995 omap_dma_disable_channel(s, ch);
997 ch->link_next_ch = value & 0x1f;
1000 case 0x2a: /* DMA_LCH_CTRL */
1001 ch->interleave_disabled = (value >> 15) & 0x1;
1002 ch->type = value & 0xf;
1011 static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1015 case 0xbc0: /* DMA_LCD_CSDP */
1016 s->brust_f2 = (value >> 14) & 0x3;
1017 s->pack_f2 = (value >> 13) & 0x1;
1018 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1019 s->brust_f1 = (value >> 7) & 0x3;
1020 s->pack_f1 = (value >> 6) & 0x1;
1021 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1024 case 0xbc2: /* DMA_LCD_CCR */
1025 s->mode_f2 = (value >> 14) & 0x3;
1026 s->mode_f1 = (value >> 12) & 0x3;
1027 s->end_prog = (value >> 11) & 0x1;
1028 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1029 s->repeat = (value >> 9) & 0x1;
1030 s->auto_init = (value >> 8) & 0x1;
1031 s->running = (value >> 7) & 0x1;
1032 s->priority = (value >> 6) & 0x1;
1033 s->bs = (value >> 4) & 0x1;
1036 case 0xbc4: /* DMA_LCD_CTRL */
1037 s->dst = (value >> 8) & 0x1;
1038 s->src = ((value >> 6) & 0x3) << 1;
1040 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1041 s->interrupts = (value >> 1) & 1;
1042 s->dual = value & 1;
1045 case 0xbc8: /* TOP_B1_L */
1046 s->src_f1_top &= 0xffff0000;
1047 s->src_f1_top |= 0x0000ffff & value;
1050 case 0xbca: /* TOP_B1_U */
1051 s->src_f1_top &= 0x0000ffff;
1052 s->src_f1_top |= (uint32_t)value << 16;
1055 case 0xbcc: /* BOT_B1_L */
1056 s->src_f1_bottom &= 0xffff0000;
1057 s->src_f1_bottom |= 0x0000ffff & value;
1060 case 0xbce: /* BOT_B1_U */
1061 s->src_f1_bottom &= 0x0000ffff;
1062 s->src_f1_bottom |= (uint32_t) value << 16;
1065 case 0xbd0: /* TOP_B2_L */
1066 s->src_f2_top &= 0xffff0000;
1067 s->src_f2_top |= 0x0000ffff & value;
1070 case 0xbd2: /* TOP_B2_U */
1071 s->src_f2_top &= 0x0000ffff;
1072 s->src_f2_top |= (uint32_t) value << 16;
1075 case 0xbd4: /* BOT_B2_L */
1076 s->src_f2_bottom &= 0xffff0000;
1077 s->src_f2_bottom |= 0x0000ffff & value;
1080 case 0xbd6: /* BOT_B2_U */
1081 s->src_f2_bottom &= 0x0000ffff;
1082 s->src_f2_bottom |= (uint32_t) value << 16;
1085 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1086 s->element_index_f1 = value;
1089 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1090 s->frame_index_f1 &= 0xffff0000;
1091 s->frame_index_f1 |= 0x0000ffff & value;
1094 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1095 s->frame_index_f1 &= 0x0000ffff;
1096 s->frame_index_f1 |= (uint32_t) value << 16;
1099 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1100 s->element_index_f2 = value;
1103 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1104 s->frame_index_f2 &= 0xffff0000;
1105 s->frame_index_f2 |= 0x0000ffff & value;
1108 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1109 s->frame_index_f2 &= 0x0000ffff;
1110 s->frame_index_f2 |= (uint32_t) value << 16;
1113 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1114 s->elements_f1 = value;
1117 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1118 s->frames_f1 = value;
1121 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1122 s->elements_f2 = value;
1125 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1126 s->frames_f2 = value;
1129 case 0xbea: /* DMA_LCD_LCH_CTRL */
1130 s->lch_type = value & 0xf;
1139 static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1143 case 0xbc0: /* DMA_LCD_CSDP */
1144 *ret = (s->brust_f2 << 14) |
1145 (s->pack_f2 << 13) |
1146 ((s->data_type_f2 >> 1) << 11) |
1147 (s->brust_f1 << 7) |
1149 ((s->data_type_f1 >> 1) << 0);
1152 case 0xbc2: /* DMA_LCD_CCR */
1153 *ret = (s->mode_f2 << 14) |
1154 (s->mode_f1 << 12) |
1155 (s->end_prog << 11) |
1156 (s->omap_3_1_compatible_disable << 10) |
1158 (s->auto_init << 8) |
1160 (s->priority << 6) |
1164 case 0xbc4: /* DMA_LCD_CTRL */
1165 qemu_irq_lower(s->irq);
1166 *ret = (s->dst << 8) |
1167 ((s->src & 0x6) << 5) |
1168 (s->condition << 3) |
1169 (s->interrupts << 1) |
1173 case 0xbc8: /* TOP_B1_L */
1174 *ret = s->src_f1_top & 0xffff;
1177 case 0xbca: /* TOP_B1_U */
1178 *ret = s->src_f1_top >> 16;
1181 case 0xbcc: /* BOT_B1_L */
1182 *ret = s->src_f1_bottom & 0xffff;
1185 case 0xbce: /* BOT_B1_U */
1186 *ret = s->src_f1_bottom >> 16;
1189 case 0xbd0: /* TOP_B2_L */
1190 *ret = s->src_f2_top & 0xffff;
1193 case 0xbd2: /* TOP_B2_U */
1194 *ret = s->src_f2_top >> 16;
1197 case 0xbd4: /* BOT_B2_L */
1198 *ret = s->src_f2_bottom & 0xffff;
1201 case 0xbd6: /* BOT_B2_U */
1202 *ret = s->src_f2_bottom >> 16;
1205 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1206 *ret = s->element_index_f1;
1209 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1210 *ret = s->frame_index_f1 & 0xffff;
1213 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1214 *ret = s->frame_index_f1 >> 16;
1217 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1218 *ret = s->element_index_f2;
1221 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1222 *ret = s->frame_index_f2 & 0xffff;
1225 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1226 *ret = s->frame_index_f2 >> 16;
1229 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1230 *ret = s->elements_f1;
1233 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1234 *ret = s->frames_f1;
1237 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1238 *ret = s->elements_f2;
1241 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1242 *ret = s->frames_f2;
1245 case 0xbea: /* DMA_LCD_LCH_CTRL */
1255 static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1259 case 0x300: /* SYS_DMA_LCD_CTRL */
1260 s->src = (value & 0x40) ? imif : emiff;
1262 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1263 s->interrupts = (value >> 1) & 1;
1264 s->dual = value & 1;
1267 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1268 s->src_f1_top &= 0xffff0000;
1269 s->src_f1_top |= 0x0000ffff & value;
1272 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1273 s->src_f1_top &= 0x0000ffff;
1274 s->src_f1_top |= (uint32_t)value << 16;
1277 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1278 s->src_f1_bottom &= 0xffff0000;
1279 s->src_f1_bottom |= 0x0000ffff & value;
1282 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1283 s->src_f1_bottom &= 0x0000ffff;
1284 s->src_f1_bottom |= (uint32_t)value << 16;
1287 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1288 s->src_f2_top &= 0xffff0000;
1289 s->src_f2_top |= 0x0000ffff & value;
1292 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1293 s->src_f2_top &= 0x0000ffff;
1294 s->src_f2_top |= (uint32_t)value << 16;
1297 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1298 s->src_f2_bottom &= 0xffff0000;
1299 s->src_f2_bottom |= 0x0000ffff & value;
1302 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1303 s->src_f2_bottom &= 0x0000ffff;
1304 s->src_f2_bottom |= (uint32_t)value << 16;
1313 static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1319 case 0x300: /* SYS_DMA_LCD_CTRL */
1322 qemu_irq_lower(s->irq);
1323 *ret = ((s->src == imif) << 6) | (i << 3) |
1324 (s->interrupts << 1) | s->dual;
1327 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1328 *ret = s->src_f1_top & 0xffff;
1331 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1332 *ret = s->src_f1_top >> 16;
1335 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1336 *ret = s->src_f1_bottom & 0xffff;
1339 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1340 *ret = s->src_f1_bottom >> 16;
1343 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1344 *ret = s->src_f2_top & 0xffff;
1347 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1348 *ret = s->src_f2_top >> 16;
1351 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1352 *ret = s->src_f2_bottom & 0xffff;
1355 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1356 *ret = s->src_f2_bottom >> 16;
1365 static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1368 case 0x400: /* SYS_DMA_GCR */
1372 case 0x404: /* DMA_GSCR */
1374 omap_dma_disable_3_1_mapping(s);
1376 omap_dma_enable_3_1_mapping(s);
1379 case 0x408: /* DMA_GRST */
1381 omap_dma_reset(s->dma);
1390 static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
1394 case 0x400: /* SYS_DMA_GCR */
1398 case 0x404: /* DMA_GSCR */
1399 *ret = s->omap_3_1_mapping_disabled << 3;
1402 case 0x408: /* DMA_GRST */
1406 case 0x442: /* DMA_HW_ID */
1407 case 0x444: /* DMA_PCh2_ID */
1408 case 0x446: /* DMA_PCh0_ID */
1409 case 0x448: /* DMA_PCh1_ID */
1410 case 0x44a: /* DMA_PChG_ID */
1411 case 0x44c: /* DMA_PChD_ID */
1415 case 0x44e: /* DMA_CAPS_0_U */
1416 *ret = (s->caps[0] >> 16) & 0xffff;
1418 case 0x450: /* DMA_CAPS_0_L */
1419 *ret = (s->caps[0] >> 0) & 0xffff;
1422 case 0x452: /* DMA_CAPS_1_U */
1423 *ret = (s->caps[1] >> 16) & 0xffff;
1425 case 0x454: /* DMA_CAPS_1_L */
1426 *ret = (s->caps[1] >> 0) & 0xffff;
1429 case 0x456: /* DMA_CAPS_2 */
1433 case 0x458: /* DMA_CAPS_3 */
1437 case 0x45a: /* DMA_CAPS_4 */
1441 case 0x460: /* DMA_PCh2_SR */
1442 case 0x480: /* DMA_PCh0_SR */
1443 case 0x482: /* DMA_PCh1_SR */
1444 case 0x4c0: /* DMA_PChD_SR_0 */
1445 qemu_log_mask(LOG_UNIMP,
1446 "%s: Physical Channel Status Registers not implemented\n",
1457 static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
1459 struct omap_dma_s *s = opaque;
1464 return omap_badwidth_read16(opaque, addr);
1468 case 0x300 ... 0x3fe:
1469 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1470 if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
1475 case 0x000 ... 0x2fe:
1477 ch = (addr >> 6) & 0x0f;
1478 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1482 case 0x404 ... 0x4fe:
1483 if (s->model <= omap_dma_3_1)
1487 if (omap_dma_sys_read(s, addr, &ret))
1491 case 0xb00 ... 0xbfe:
1492 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1493 if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
1504 static void omap_dma_write(void *opaque, hwaddr addr,
1505 uint64_t value, unsigned size)
1507 struct omap_dma_s *s = opaque;
1511 omap_badwidth_write16(opaque, addr, value);
1516 case 0x300 ... 0x3fe:
1517 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1518 if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
1523 case 0x000 ... 0x2fe:
1525 ch = (addr >> 6) & 0x0f;
1526 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1530 case 0x404 ... 0x4fe:
1531 if (s->model <= omap_dma_3_1)
1535 if (omap_dma_sys_write(s, addr, value))
1539 case 0xb00 ... 0xbfe:
1540 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1541 if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
1551 static const MemoryRegionOps omap_dma_ops = {
1552 .read = omap_dma_read,
1553 .write = omap_dma_write,
1554 .endianness = DEVICE_NATIVE_ENDIAN,
1557 static void omap_dma_request(void *opaque, int drq, int req)
1559 struct omap_dma_s *s = opaque;
1560 /* The request pins are level triggered in QEMU. */
1562 if (~s->dma->drqbmp & (1ULL << drq)) {
1563 s->dma->drqbmp |= 1ULL << drq;
1564 omap_dma_process_request(s, drq);
1567 s->dma->drqbmp &= ~(1ULL << drq);
1570 /* XXX: this won't be needed once soc_dma knows about clocks. */
1571 static void omap_dma_clk_update(void *opaque, int line, int on)
1573 struct omap_dma_s *s = opaque;
1576 s->dma->freq = omap_clk_getrate(s->clk);
1578 for (i = 0; i < s->chans; i ++)
1579 if (s->ch[i].active)
1580 soc_dma_set_request(s->ch[i].dma, on);
1583 static void omap_dma_setcaps(struct omap_dma_s *s)
1591 /* XXX Only available for sDMA */
1593 (1 << 19) | /* Constant Fill Capability */
1594 (1 << 18); /* Transparent BLT Capability */
1596 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1598 (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
1599 (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
1600 (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
1601 (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
1602 (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
1603 (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
1604 (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
1605 (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
1606 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1608 (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
1609 (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
1610 (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
1611 (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
1612 (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
1613 (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
1614 (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
1615 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1617 (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
1618 (1 << 6) | /* SYNC_STATUS_CPBLTY */
1619 (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
1620 (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
1621 (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
1622 (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
1623 (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
1624 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1629 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
1630 MemoryRegion *sysmem,
1631 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1632 enum omap_dma_model model)
1634 int num_irqs, memsize, i;
1635 struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);
1637 if (model <= omap_dma_3_1) {
1647 s->lcd_ch.irq = lcd_irq;
1648 s->lcd_ch.mpu = mpu;
1650 s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);
1651 s->dma->freq = omap_clk_getrate(clk);
1652 s->dma->transfer_fn = omap_dma_transfer_generic;
1653 s->dma->setup_fn = omap_dma_transfer_setup;
1654 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1658 s->ch[num_irqs].irq = irqs[num_irqs];
1659 for (i = 0; i < 3; i ++) {
1660 s->ch[i].sibling = &s->ch[i + 6];
1661 s->ch[i + 6].sibling = &s->ch[i];
1663 for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
1664 s->ch[i].dma = &s->dma->ch[i];
1665 s->dma->ch[i].opaque = &s->ch[i];
1668 omap_dma_setcaps(s);
1669 omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0));
1670 omap_dma_reset(s->dma);
1671 omap_dma_clk_update(s, 0, 1);
1673 memory_region_init_io(&s->iomem, NULL, &omap_dma_ops, s, "omap.dma", memsize);
1674 memory_region_add_subregion(sysmem, base, &s->iomem);
1676 mpu->drq = s->dma->drq;
1681 static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
1683 struct omap_dma_channel_s *ch = s->ch;
1686 for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1)
1689 ch->cstatus |= ch->status;
1692 if ((s->irqstat[0] |= s->irqen[0] & bmp))
1693 qemu_irq_raise(s->irq[0]);
1694 if ((s->irqstat[1] |= s->irqen[1] & bmp))
1695 qemu_irq_raise(s->irq[1]);
1696 if ((s->irqstat[2] |= s->irqen[2] & bmp))
1697 qemu_irq_raise(s->irq[2]);
1698 if ((s->irqstat[3] |= s->irqen[3] & bmp))
1699 qemu_irq_raise(s->irq[3]);
1702 static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
1705 struct omap_dma_s *s = opaque;
1706 int irqn = 0, chnum;
1707 struct omap_dma_channel_s *ch;
1710 return omap_badwidth_read16(opaque, addr);
1714 case 0x00: /* DMA4_REVISION */
1717 case 0x14: /* DMA4_IRQSTATUS_L3 */
1720 case 0x10: /* DMA4_IRQSTATUS_L2 */
1723 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1726 case 0x08: /* DMA4_IRQSTATUS_L0 */
1727 return s->irqstat[irqn];
1729 case 0x24: /* DMA4_IRQENABLE_L3 */
1732 case 0x20: /* DMA4_IRQENABLE_L2 */
1735 case 0x1c: /* DMA4_IRQENABLE_L1 */
1738 case 0x18: /* DMA4_IRQENABLE_L0 */
1739 return s->irqen[irqn];
1741 case 0x28: /* DMA4_SYSSTATUS */
1742 return 1; /* RESETDONE */
1744 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1747 case 0x64: /* DMA4_CAPS_0 */
1749 case 0x6c: /* DMA4_CAPS_2 */
1751 case 0x70: /* DMA4_CAPS_3 */
1753 case 0x74: /* DMA4_CAPS_4 */
1756 case 0x78: /* DMA4_GCR */
1759 case 0x80 ... 0xfff:
1761 chnum = addr / 0x60;
1763 addr -= chnum * 0x60;
1771 /* Per-channel registers */
1773 case 0x00: /* DMA4_CCR */
1774 return (ch->buf_disable << 25) |
1775 (ch->src_sync << 24) |
1776 (ch->prefetch << 23) |
1777 ((ch->sync & 0x60) << 14) |
1779 (ch->transparent_copy << 17) |
1780 (ch->constant_fill << 16) |
1781 (ch->mode[1] << 14) |
1782 (ch->mode[0] << 12) |
1783 (0 << 10) | (0 << 9) |
1784 (ch->suspend << 8) |
1786 (ch->priority << 6) |
1787 (ch->fs << 5) | (ch->sync & 0x1f);
1789 case 0x04: /* DMA4_CLNK_CTRL */
1790 return (ch->link_enabled << 15) | ch->link_next_ch;
1792 case 0x08: /* DMA4_CICR */
1793 return ch->interrupts;
1795 case 0x0c: /* DMA4_CSR */
1798 case 0x10: /* DMA4_CSDP */
1799 return (ch->endian[0] << 21) |
1800 (ch->endian_lock[0] << 20) |
1801 (ch->endian[1] << 19) |
1802 (ch->endian_lock[1] << 18) |
1803 (ch->write_mode << 16) |
1804 (ch->burst[1] << 14) |
1805 (ch->pack[1] << 13) |
1806 (ch->translate[1] << 9) |
1807 (ch->burst[0] << 7) |
1808 (ch->pack[0] << 6) |
1809 (ch->translate[0] << 2) |
1810 (ch->data_type >> 1);
1812 case 0x14: /* DMA4_CEN */
1813 return ch->elements;
1815 case 0x18: /* DMA4_CFN */
1818 case 0x1c: /* DMA4_CSSA */
1821 case 0x20: /* DMA4_CDSA */
1824 case 0x24: /* DMA4_CSEI */
1825 return ch->element_index[0];
1827 case 0x28: /* DMA4_CSFI */
1828 return ch->frame_index[0];
1830 case 0x2c: /* DMA4_CDEI */
1831 return ch->element_index[1];
1833 case 0x30: /* DMA4_CDFI */
1834 return ch->frame_index[1];
1836 case 0x34: /* DMA4_CSAC */
1837 return ch->active_set.src & 0xffff;
1839 case 0x38: /* DMA4_CDAC */
1840 return ch->active_set.dest & 0xffff;
1842 case 0x3c: /* DMA4_CCEN */
1843 return ch->active_set.element;
1845 case 0x40: /* DMA4_CCFN */
1846 return ch->active_set.frame;
1848 case 0x44: /* DMA4_COLOR */
1849 /* XXX only in sDMA */
1858 static void omap_dma4_write(void *opaque, hwaddr addr,
1859 uint64_t value, unsigned size)
1861 struct omap_dma_s *s = opaque;
1862 int chnum, irqn = 0;
1863 struct omap_dma_channel_s *ch;
1866 omap_badwidth_write16(opaque, addr, value);
1871 case 0x14: /* DMA4_IRQSTATUS_L3 */
1874 case 0x10: /* DMA4_IRQSTATUS_L2 */
1877 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1880 case 0x08: /* DMA4_IRQSTATUS_L0 */
1881 s->irqstat[irqn] &= ~value;
1882 if (!s->irqstat[irqn])
1883 qemu_irq_lower(s->irq[irqn]);
1886 case 0x24: /* DMA4_IRQENABLE_L3 */
1889 case 0x20: /* DMA4_IRQENABLE_L2 */
1892 case 0x1c: /* DMA4_IRQENABLE_L1 */
1895 case 0x18: /* DMA4_IRQENABLE_L0 */
1896 s->irqen[irqn] = value;
1899 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1900 if (value & 2) /* SOFTRESET */
1901 omap_dma_reset(s->dma);
1902 s->ocp = value & 0x3321;
1903 if (((s->ocp >> 12) & 3) == 3) { /* MIDLEMODE */
1904 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA power mode\n",
1909 case 0x78: /* DMA4_GCR */
1910 s->gcr = value & 0x00ff00ff;
1911 if ((value & 0xff) == 0x00) { /* MAX_CHANNEL_FIFO_DEPTH */
1912 qemu_log_mask(LOG_GUEST_ERROR, "%s: wrong FIFO depth in GCR\n",
1917 case 0x80 ... 0xfff:
1919 chnum = addr / 0x60;
1921 addr -= chnum * 0x60;
1924 case 0x00: /* DMA4_REVISION */
1925 case 0x28: /* DMA4_SYSSTATUS */
1926 case 0x64: /* DMA4_CAPS_0 */
1927 case 0x6c: /* DMA4_CAPS_2 */
1928 case 0x70: /* DMA4_CAPS_3 */
1929 case 0x74: /* DMA4_CAPS_4 */
1938 /* Per-channel registers */
1940 case 0x00: /* DMA4_CCR */
1941 ch->buf_disable = (value >> 25) & 1;
1942 ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
1943 if (ch->buf_disable && !ch->src_sync) {
1944 qemu_log_mask(LOG_GUEST_ERROR,
1945 "%s: Buffering disable is not allowed in "
1946 "destination synchronised mode\n", __func__);
1948 ch->prefetch = (value >> 23) & 1;
1949 ch->bs = (value >> 18) & 1;
1950 ch->transparent_copy = (value >> 17) & 1;
1951 ch->constant_fill = (value >> 16) & 1;
1952 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
1953 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
1954 ch->suspend = (value & 0x0100) >> 8;
1955 ch->priority = (value & 0x0040) >> 6;
1956 ch->fs = (value & 0x0020) >> 5;
1957 if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) {
1958 qemu_log_mask(LOG_GUEST_ERROR,
1959 "%s: For a packet transfer at least one port "
1960 "must be constant-addressed\n", __func__);
1962 ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
1963 /* XXX must be 0x01 for CamDMA */
1966 omap_dma_enable_channel(s, ch);
1968 omap_dma_disable_channel(s, ch);
1972 case 0x04: /* DMA4_CLNK_CTRL */
1973 ch->link_enabled = (value >> 15) & 0x1;
1974 ch->link_next_ch = value & 0x1f;
1977 case 0x08: /* DMA4_CICR */
1978 ch->interrupts = value & 0x09be;
1981 case 0x0c: /* DMA4_CSR */
1982 ch->cstatus &= ~value;
1985 case 0x10: /* DMA4_CSDP */
1986 ch->endian[0] =(value >> 21) & 1;
1987 ch->endian_lock[0] =(value >> 20) & 1;
1988 ch->endian[1] =(value >> 19) & 1;
1989 ch->endian_lock[1] =(value >> 18) & 1;
1990 if (ch->endian[0] != ch->endian[1]) {
1991 qemu_log_mask(LOG_GUEST_ERROR,
1992 "%s: DMA endianness conversion enable attempt\n",
1995 ch->write_mode = (value >> 16) & 3;
1996 ch->burst[1] = (value & 0xc000) >> 14;
1997 ch->pack[1] = (value & 0x2000) >> 13;
1998 ch->translate[1] = (value & 0x1e00) >> 9;
1999 ch->burst[0] = (value & 0x0180) >> 7;
2000 ch->pack[0] = (value & 0x0040) >> 6;
2001 ch->translate[0] = (value & 0x003c) >> 2;
2002 if (ch->translate[0] | ch->translate[1]) {
2003 qemu_log_mask(LOG_GUEST_ERROR,
2004 "%s: bad MReqAddressTranslate sideband signal\n",
2007 ch->data_type = 1 << (value & 3);
2008 if ((value & 3) == 3) {
2009 qemu_log_mask(LOG_GUEST_ERROR,
2010 "%s: bad data_type for DMA channel\n", __func__);
2011 ch->data_type >>= 1;
2015 case 0x14: /* DMA4_CEN */
2017 ch->elements = value & 0xffffff;
2020 case 0x18: /* DMA4_CFN */
2021 ch->frames = value & 0xffff;
2025 case 0x1c: /* DMA4_CSSA */
2026 ch->addr[0] = (hwaddr) (uint32_t) value;
2030 case 0x20: /* DMA4_CDSA */
2031 ch->addr[1] = (hwaddr) (uint32_t) value;
2035 case 0x24: /* DMA4_CSEI */
2036 ch->element_index[0] = (int16_t) value;
2040 case 0x28: /* DMA4_CSFI */
2041 ch->frame_index[0] = (int32_t) value;
2045 case 0x2c: /* DMA4_CDEI */
2046 ch->element_index[1] = (int16_t) value;
2050 case 0x30: /* DMA4_CDFI */
2051 ch->frame_index[1] = (int32_t) value;
2055 case 0x44: /* DMA4_COLOR */
2056 /* XXX only in sDMA */
2060 case 0x34: /* DMA4_CSAC */
2061 case 0x38: /* DMA4_CDAC */
2062 case 0x3c: /* DMA4_CCEN */
2063 case 0x40: /* DMA4_CCFN */
2072 static const MemoryRegionOps omap_dma4_ops = {
2073 .read = omap_dma4_read,
2074 .write = omap_dma4_write,
2075 .endianness = DEVICE_NATIVE_ENDIAN,
2078 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
2079 MemoryRegion *sysmem,
2080 struct omap_mpu_state_s *mpu, int fifo,
2081 int chans, omap_clk iclk, omap_clk fclk)
2084 struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);
2086 s->model = omap_dma_4;
2091 s->dma = soc_dma_init(s->chans);
2092 s->dma->freq = omap_clk_getrate(fclk);
2093 s->dma->transfer_fn = omap_dma_transfer_generic;
2094 s->dma->setup_fn = omap_dma_transfer_setup;
2095 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
2097 for (i = 0; i < s->chans; i ++) {
2098 s->ch[i].dma = &s->dma->ch[i];
2099 s->dma->ch[i].opaque = &s->ch[i];
2102 memcpy(&s->irq, irqs, sizeof(s->irq));
2103 s->intr_update = omap_dma_interrupts_4_update;
2105 omap_dma_setcaps(s);
2106 omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0));
2107 omap_dma_reset(s->dma);
2108 omap_dma_clk_update(s, 0, !!s->dma->freq);
2110 memory_region_init_io(&s->iomem, NULL, &omap_dma4_ops, s, "omap.dma4", 0x1000);
2111 memory_region_add_subregion(sysmem, base, &s->iomem);
2113 mpu->drq = s->dma->drq;
2118 struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma)
2120 struct omap_dma_s *s = dma->opaque;