2 * ARM PrimeCell PL330 DMA Controller
4 * Copyright (c) 2009 Samsung Electronics.
5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
6 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
7 * Copyright (c) 2012 PetaLogix Pty Ltd.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 or later.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 #include "qemu/osdep.h"
19 #include "hw/qdev-properties.h"
20 #include "hw/sysbus.h"
21 #include "migration/vmstate.h"
22 #include "qapi/error.h"
23 #include "qemu/timer.h"
24 #include "sysemu/dma.h"
26 #include "qemu/module.h"
28 #include "qom/object.h"
30 #ifndef PL330_ERR_DEBUG
31 #define PL330_ERR_DEBUG 0
34 #define PL330_PERIPH_NUM 32
35 #define PL330_MAX_BURST_LEN 128
36 #define PL330_INSN_MAXSIZE 6
38 #define PL330_FIFO_OK 0
39 #define PL330_FIFO_STALL 1
40 #define PL330_FIFO_ERR (-1)
42 #define PL330_FAULT_UNDEF_INSTR (1 << 0)
43 #define PL330_FAULT_OPERAND_INVALID (1 << 1)
44 #define PL330_FAULT_DMAGO_ERR (1 << 4)
45 #define PL330_FAULT_EVENT_ERR (1 << 5)
46 #define PL330_FAULT_CH_PERIPH_ERR (1 << 6)
47 #define PL330_FAULT_CH_RDWR_ERR (1 << 7)
48 #define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12)
49 #define PL330_FAULT_FIFOEMPTY_ERR (1 << 13)
50 #define PL330_FAULT_INSTR_FETCH_ERR (1 << 16)
51 #define PL330_FAULT_DATA_WRITE_ERR (1 << 17)
52 #define PL330_FAULT_DATA_READ_ERR (1 << 18)
53 #define PL330_FAULT_DBG_INSTR (1 << 30)
54 #define PL330_FAULT_LOCKUP_ERR (1 << 31)
56 #define PL330_UNTAGGED 0xff
58 #define PL330_SINGLE 0x0
59 #define PL330_BURST 0x1
61 #define PL330_WATCHDOG_LIMIT 1024
63 /* IOMEM mapped registers */
64 #define PL330_REG_DSR 0x000
65 #define PL330_REG_DPC 0x004
66 #define PL330_REG_INTEN 0x020
67 #define PL330_REG_INT_EVENT_RIS 0x024
68 #define PL330_REG_INTMIS 0x028
69 #define PL330_REG_INTCLR 0x02C
70 #define PL330_REG_FSRD 0x030
71 #define PL330_REG_FSRC 0x034
72 #define PL330_REG_FTRD 0x038
73 #define PL330_REG_FTR_BASE 0x040
74 #define PL330_REG_CSR_BASE 0x100
75 #define PL330_REG_CPC_BASE 0x104
76 #define PL330_REG_CHANCTRL 0x400
77 #define PL330_REG_DBGSTATUS 0xD00
78 #define PL330_REG_DBGCMD 0xD04
79 #define PL330_REG_DBGINST0 0xD08
80 #define PL330_REG_DBGINST1 0xD0C
81 #define PL330_REG_CR0_BASE 0xE00
82 #define PL330_REG_PERIPH_ID 0xFE0
84 #define PL330_IOMEM_SIZE 0x1000
86 #define CFG_BOOT_ADDR 2
91 static const uint32_t pl330_id[] = {
92 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1
95 /* DMA channel states as they are described in PL330 Technical Reference Manual
96 * Most of them will not be used in emulation.
99 pl330_chan_stopped = 0,
100 pl330_chan_executing = 1,
101 pl330_chan_cache_miss = 2,
102 pl330_chan_updating_pc = 3,
103 pl330_chan_waiting_event = 4,
104 pl330_chan_at_barrier = 5,
105 pl330_chan_queue_busy = 6,
106 pl330_chan_waiting_periph = 7,
107 pl330_chan_killing = 8,
108 pl330_chan_completing = 9,
109 pl330_chan_fault_completing = 14,
110 pl330_chan_fault = 15,
113 typedef struct PL330State PL330State;
115 typedef struct PL330Chan {
123 uint32_t watchdog_timer;
126 uint8_t request_flag;
138 static const VMStateDescription vmstate_pl330_chan = {
139 .name = "pl330_chan",
141 .minimum_version_id = 1,
142 .fields = (VMStateField[]) {
143 VMSTATE_UINT32(src, PL330Chan),
144 VMSTATE_UINT32(dst, PL330Chan),
145 VMSTATE_UINT32(pc, PL330Chan),
146 VMSTATE_UINT32(control, PL330Chan),
147 VMSTATE_UINT32(status, PL330Chan),
148 VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2),
149 VMSTATE_UINT32(fault_type, PL330Chan),
150 VMSTATE_UINT32(watchdog_timer, PL330Chan),
151 VMSTATE_BOOL(ns, PL330Chan),
152 VMSTATE_UINT8(request_flag, PL330Chan),
153 VMSTATE_UINT8(wakeup, PL330Chan),
154 VMSTATE_UINT8(wfp_sbp, PL330Chan),
155 VMSTATE_UINT8(state, PL330Chan),
156 VMSTATE_UINT8(stall, PL330Chan),
157 VMSTATE_END_OF_LIST()
161 typedef struct PL330Fifo {
169 static const VMStateDescription vmstate_pl330_fifo = {
170 .name = "pl330_chan",
172 .minimum_version_id = 1,
173 .fields = (VMStateField[]) {
174 VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, buf_size),
175 VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, buf_size),
176 VMSTATE_UINT32(head, PL330Fifo),
177 VMSTATE_UINT32(num, PL330Fifo),
178 VMSTATE_UINT32(buf_size, PL330Fifo),
179 VMSTATE_END_OF_LIST()
183 typedef struct PL330QueueEntry {
193 static const VMStateDescription vmstate_pl330_queue_entry = {
194 .name = "pl330_queue_entry",
196 .minimum_version_id = 1,
197 .fields = (VMStateField[]) {
198 VMSTATE_UINT32(addr, PL330QueueEntry),
199 VMSTATE_UINT32(len, PL330QueueEntry),
200 VMSTATE_UINT8(n, PL330QueueEntry),
201 VMSTATE_BOOL(inc, PL330QueueEntry),
202 VMSTATE_BOOL(z, PL330QueueEntry),
203 VMSTATE_UINT8(tag, PL330QueueEntry),
204 VMSTATE_UINT8(seqn, PL330QueueEntry),
205 VMSTATE_END_OF_LIST()
209 typedef struct PL330Queue {
211 PL330QueueEntry *queue;
215 static const VMStateDescription vmstate_pl330_queue = {
216 .name = "pl330_queue",
218 .minimum_version_id = 2,
219 .fields = (VMStateField[]) {
220 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size,
221 vmstate_pl330_queue_entry,
223 VMSTATE_END_OF_LIST()
228 SysBusDevice parent_obj;
234 /* Config registers. cfg[5] = CfgDn. */
236 #define EVENT_SEC_STATE 3
237 #define PERIPH_SEC_STATE 4
238 /* cfg 0 bits and pieces */
240 uint8_t num_periph_req;
242 uint8_t mgr_ns_at_rst;
243 /* cfg 1 bits and pieces */
245 uint8_t num_i_cache_lines;
246 /* CRD bits and pieces */
252 uint16_t data_buffer_dep;
257 PL330Queue read_queue;
258 PL330Queue write_queue;
261 QEMUTimer *timer; /* is used for restore dma. */
267 uint8_t debug_status;
268 uint8_t num_faulting;
269 uint8_t periph_busy[PL330_PERIPH_NUM];
271 /* Memory region that DMA operation access */
272 MemoryRegion *mem_mr;
273 AddressSpace *mem_as;
276 #define TYPE_PL330 "pl330"
277 OBJECT_DECLARE_SIMPLE_TYPE(PL330State, PL330)
279 static const VMStateDescription vmstate_pl330 = {
282 .minimum_version_id = 2,
283 .fields = (VMStateField[]) {
284 VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan),
285 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls,
286 vmstate_pl330_chan, PL330Chan),
287 VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls),
288 VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls),
289 VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo),
290 VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue,
292 VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue,
294 VMSTATE_TIMER_PTR(timer, PL330State),
295 VMSTATE_UINT32(inten, PL330State),
296 VMSTATE_UINT32(int_status, PL330State),
297 VMSTATE_UINT32(ev_status, PL330State),
298 VMSTATE_UINT32_ARRAY(dbg, PL330State, 2),
299 VMSTATE_UINT8(debug_status, PL330State),
300 VMSTATE_UINT8(num_faulting, PL330State),
301 VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM),
302 VMSTATE_END_OF_LIST()
306 typedef struct PL330InsnDesc {
307 /* OPCODE of the instruction */
309 /* Mask so we can select several sibling instructions, such as
310 DMALD, DMALDS and DMALDB */
312 /* Size of instruction in bytes */
315 void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len);
318 static void pl330_hexdump(uint8_t *buf, size_t size)
320 unsigned int b, i, len;
323 for (b = 0; b < size; b += 16) {
329 for (i = 0; i < len; i++) {
333 sprintf(tmpbuf + strlen(tmpbuf), " %02x", buf[b + i]);
335 trace_pl330_hexdump(b, tmpbuf);
339 /* MFIFO Implementation
341 * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are
342 * stored in this buffer. Data is stored in BUF field, tags - in the
343 * corresponding array elements of TAG field.
346 /* Initialize queue. */
348 static void pl330_fifo_init(PL330Fifo *s, uint32_t size)
350 s->buf = g_malloc0(size);
351 s->tag = g_malloc0(size);
355 /* Cyclic increment */
357 static inline int pl330_fifo_inc(PL330Fifo *s, int x)
359 return (x + 1) % s->buf_size;
362 /* Number of empty bytes in MFIFO */
364 static inline int pl330_fifo_num_free(PL330Fifo *s)
366 return s->buf_size - s->num;
369 /* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG.
370 * Zero returned on success, PL330_FIFO_STALL if there is no enough free
371 * space in MFIFO to store requested amount of data. If push was unsuccessful
372 * no data is stored to MFIFO.
375 static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag)
379 if (s->buf_size - s->num < len) {
380 return PL330_FIFO_STALL;
382 for (i = 0; i < len; i++) {
383 int push_idx = (s->head + s->num + i) % s->buf_size;
384 s->buf[push_idx] = buf[i];
385 s->tag[push_idx] = tag;
388 return PL330_FIFO_OK;
391 /* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each
392 * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch
393 * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was
394 * unsuccessful no data is removed from MFIFO.
397 static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag)
402 return PL330_FIFO_STALL;
404 for (i = 0; i < len; i++) {
405 if (s->tag[s->head] == tag) {
406 int get_idx = (s->head + i) % s->buf_size;
407 buf[i] = s->buf[get_idx];
408 } else { /* Tag mismatch - Rollback transaction */
409 return PL330_FIFO_ERR;
412 s->head = (s->head + len) % s->buf_size;
414 return PL330_FIFO_OK;
417 /* Reset MFIFO. This completely erases all data in it. */
419 static inline void pl330_fifo_reset(PL330Fifo *s)
425 /* Return tag of the first byte stored in MFIFO. If MFIFO is empty
426 * PL330_UNTAGGED is returned.
429 static inline uint8_t pl330_fifo_tag(PL330Fifo *s)
431 return (!s->num) ? PL330_UNTAGGED : s->tag[s->head];
434 /* Returns non-zero if tag TAG is present in fifo or zero otherwise */
436 static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag)
441 for (n = 0; n < s->num; n++) {
442 if (s->tag[i] == tag) {
445 i = pl330_fifo_inc(s, i);
450 /* Remove all entry tagged with TAG from MFIFO */
452 static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag)
457 for (n = 0; n < s->num; n++) {
458 if (s->tag[i] != tag) {
459 s->buf[t] = s->buf[i];
460 s->tag[t] = s->tag[i];
461 t = pl330_fifo_inc(s, t);
465 i = pl330_fifo_inc(s, i);
469 /* Read-Write Queue implementation
471 * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores).
472 * Each instruction is described by source (for loads) or destination (for
473 * stores) address ADDR, width of data to be loaded/stored LEN, number of
474 * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel
475 * this instruction belongs to. Queue does not store any information about
476 * nature of the instruction: is it load or store. PL330 has different queues
477 * for loads and stores so this is already known at the top level where it
480 * Queue works as FIFO for instructions with equivalent tags, but can issue
481 * instructions with different tags in arbitrary order. SEQN field attached to
482 * each instruction helps to achieve this. For each TAG queue contains
483 * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to
484 * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is
485 * followed by SEQN=0.
487 * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed
491 static void pl330_queue_reset(PL330Queue *s)
495 for (i = 0; i < s->queue_size; i++) {
496 s->queue[i].tag = PL330_UNTAGGED;
500 /* Initialize queue */
501 static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent)
504 s->queue = g_new0(PL330QueueEntry, size);
505 s->queue_size = size;
508 /* Returns pointer to an empty slot or NULL if queue is full */
509 static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s)
513 for (i = 0; i < s->queue_size; i++) {
514 if (s->queue[i].tag == PL330_UNTAGGED) {
521 /* Put instruction in queue.
524 * - non-zero - queue is full
527 static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr,
528 int len, int n, bool inc, bool z, uint8_t tag)
530 PL330QueueEntry *entry = pl330_queue_find_empty(s);
541 entry->seqn = s->parent->hi_seqn[tag];
542 s->parent->hi_seqn[tag]++;
546 /* Returns a pointer to queue slot containing instruction which satisfies
547 * following conditions:
548 * - it has valid tag value (not PL330_UNTAGGED)
549 * - if enforce_seq is set it has to be issuable without violating queue
551 * - if TAG argument is not PL330_UNTAGGED this instruction has tag value
552 * equivalent to the argument TAG value.
553 * If such instruction cannot be found NULL is returned.
556 static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag,
561 for (i = 0; i < s->queue_size; i++) {
562 if (s->queue[i].tag != PL330_UNTAGGED) {
564 s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) &&
565 (s->queue[i].tag == tag || tag == PL330_UNTAGGED ||
574 /* Removes instruction from queue. */
576 static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e)
578 s->parent->lo_seqn[e->tag]++;
579 e->tag = PL330_UNTAGGED;
582 /* Removes all instructions tagged with TAG from queue. */
584 static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag)
588 for (i = 0; i < s->queue_size; i++) {
589 if (s->queue[i].tag == tag) {
590 s->queue[i].tag = PL330_UNTAGGED;
595 /* DMA instruction execution engine */
597 /* Moves DMA channel to the FAULT state and updates it's status. */
599 static inline void pl330_fault(PL330Chan *ch, uint32_t flags)
601 trace_pl330_fault(ch, flags);
602 ch->fault_type |= flags;
603 if (ch->state == pl330_chan_fault) {
606 ch->state = pl330_chan_fault;
607 ch->parent->num_faulting++;
608 if (ch->parent->num_faulting == 1) {
609 trace_pl330_fault_abort();
610 qemu_irq_raise(ch->parent->irq_abort);
615 * For information about instructions see PL330 Technical Reference Manual.
618 * CH - channel executing the instruction
620 * ARGS - array of 8-bit arguments
621 * LEN - number of elements in ARGS array
624 static void pl330_dmaadxh(PL330Chan *ch, uint8_t *args, bool ra, bool neg)
626 uint32_t im = (args[1] << 8) | args[0];
631 if (ch->is_manager) {
632 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
642 static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
644 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), false);
647 static void pl330_dmaadnh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
649 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), true);
652 static void pl330_dmaend(PL330Chan *ch, uint8_t opcode,
653 uint8_t *args, int len)
655 PL330State *s = ch->parent;
657 if (ch->state == pl330_chan_executing && !ch->is_manager) {
658 /* Wait for all transfers to complete */
659 if (pl330_fifo_has_tag(&s->fifo, ch->tag) ||
660 pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL ||
661 pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) {
667 trace_pl330_dmaend();
668 pl330_fifo_tagged_remove(&s->fifo, ch->tag);
669 pl330_queue_remove_tagged(&s->read_queue, ch->tag);
670 pl330_queue_remove_tagged(&s->write_queue, ch->tag);
671 ch->state = pl330_chan_stopped;
674 static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode,
675 uint8_t *args, int len)
680 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
683 periph_id = (args[0] >> 3) & 0x1f;
684 if (periph_id >= ch->parent->num_periph_req) {
685 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
688 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
689 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
695 static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
704 if (!ch->is_manager) {
705 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
709 chan_id = args[0] & 7;
710 if ((args[0] >> 3)) {
711 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
714 if (chan_id >= ch->parent->num_chnls) {
715 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
718 pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) |
719 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1]));
720 if (ch->parent->chan[chan_id].state != pl330_chan_stopped) {
721 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
725 pl330_fault(ch, PL330_FAULT_DMAGO_ERR);
728 s = &ch->parent->chan[chan_id];
731 s->state = pl330_chan_executing;
734 static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
736 uint8_t bs = opcode & 3;
741 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
744 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
745 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
749 if (bs == 1 && ch->request_flag == PL330_SINGLE) {
752 num = ((ch->control >> 4) & 0xf) + 1;
754 size = (uint32_t)1 << ((ch->control >> 1) & 0x7);
755 inc = !!(ch->control & 1);
756 ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src,
757 size, num, inc, 0, ch->tag);
759 trace_pl330_dmald(ch->tag, ch->src, size, num, inc ? 'Y' : 'N');
760 ch->src += inc ? size * num - (ch->src & (size - 1)) : 0;
764 static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
769 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
772 periph_id = (args[0] >> 3) & 0x1f;
773 if (periph_id >= ch->parent->num_periph_req) {
774 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
777 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
778 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
781 pl330_dmald(ch, opcode, args, len);
784 static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
786 uint8_t lc = (opcode & 2) >> 1;
788 ch->lc[lc] = args[0];
791 static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
793 if (ch->state == pl330_chan_fault ||
794 ch->state == pl330_chan_fault_completing) {
795 /* This is the only way for a channel to leave the faulting state */
797 ch->parent->num_faulting--;
798 if (ch->parent->num_faulting == 0) {
799 trace_pl330_dmakill();
800 qemu_irq_lower(ch->parent->irq_abort);
803 ch->state = pl330_chan_killing;
804 pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag);
805 pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag);
806 pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag);
807 ch->state = pl330_chan_stopped;
810 static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode,
811 uint8_t *args, int len)
813 uint8_t nf = (opcode & 0x10) >> 4;
814 uint8_t bs = opcode & 3;
815 uint8_t lc = (opcode & 4) >> 2;
817 trace_pl330_dmalpend(nf, bs, lc, ch->lc[lc], ch->request_flag);
820 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
823 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
824 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
828 if (!nf || ch->lc[lc]) {
832 trace_pl330_dmalpiter();
835 /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */
837 trace_pl330_dmalpfallthrough();
842 static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
844 uint8_t rd = args[0] & 7;
847 if ((args[0] >> 3)) {
848 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
851 im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) |
852 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1]));
864 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
869 static void pl330_dmanop(PL330Chan *ch, uint8_t opcode,
870 uint8_t *args, int len)
875 static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
877 if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) {
878 ch->state = pl330_chan_at_barrier;
882 ch->state = pl330_chan_executing;
886 static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
891 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
894 ev_id = (args[0] >> 3) & 0x1f;
895 if (ev_id >= ch->parent->num_events) {
896 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
899 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) {
900 pl330_fault(ch, PL330_FAULT_EVENT_ERR);
903 if (ch->parent->inten & (1 << ev_id)) {
904 ch->parent->int_status |= (1 << ev_id);
905 trace_pl330_dmasev_evirq(ev_id);
906 qemu_irq_raise(ch->parent->irq[ev_id]);
908 trace_pl330_dmasev_event(ev_id);
909 ch->parent->ev_status |= (1 << ev_id);
912 static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
914 uint8_t bs = opcode & 3;
919 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
922 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
923 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
927 num = ((ch->control >> 18) & 0xf) + 1;
928 size = (uint32_t)1 << ((ch->control >> 15) & 0x7);
929 inc = !!((ch->control >> 14) & 1);
930 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst,
931 size, num, inc, 0, ch->tag);
933 trace_pl330_dmast(ch->tag, ch->dst, size, num, inc ? 'Y' : 'N');
934 ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0;
938 static void pl330_dmastp(PL330Chan *ch, uint8_t opcode,
939 uint8_t *args, int len)
944 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
947 periph_id = (args[0] >> 3) & 0x1f;
948 if (periph_id >= ch->parent->num_periph_req) {
949 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
952 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
953 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
956 pl330_dmast(ch, opcode, args, len);
959 static void pl330_dmastz(PL330Chan *ch, uint8_t opcode,
960 uint8_t *args, int len)
965 num = ((ch->control >> 18) & 0xf) + 1;
966 size = (uint32_t)1 << ((ch->control >> 15) & 0x7);
967 inc = !!((ch->control >> 14) & 1);
968 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst,
969 size, num, inc, 1, ch->tag);
971 ch->dst += size * num;
975 static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode,
976 uint8_t *args, int len)
982 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
985 ev_id = (args[0] >> 3) & 0x1f;
986 if (ev_id >= ch->parent->num_events) {
987 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
990 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) {
991 pl330_fault(ch, PL330_FAULT_EVENT_ERR);
995 ch->state = pl330_chan_waiting_event;
996 if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) {
997 ch->state = pl330_chan_executing;
998 /* If anyone else is currently waiting on the same event, let them
999 * clear the ev_status so they pick up event as well
1001 for (i = 0; i < ch->parent->num_chnls; ++i) {
1002 PL330Chan *peer = &ch->parent->chan[i];
1003 if (peer->state == pl330_chan_waiting_event &&
1004 peer->wakeup == ev_id) {
1008 ch->parent->ev_status &= ~(1 << ev_id);
1009 trace_pl330_dmawfe(ev_id);
1015 static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode,
1016 uint8_t *args, int len)
1018 uint8_t bs = opcode & 3;
1022 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1025 periph_id = (args[0] >> 3) & 0x1f;
1026 if (periph_id >= ch->parent->num_periph_req) {
1027 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1030 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
1031 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
1036 ch->request_flag = PL330_SINGLE;
1040 ch->request_flag = PL330_BURST;
1044 ch->request_flag = PL330_BURST;
1048 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1052 if (ch->parent->periph_busy[periph_id]) {
1053 ch->state = pl330_chan_waiting_periph;
1055 } else if (ch->state == pl330_chan_waiting_periph) {
1056 ch->state = pl330_chan_executing;
1060 static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode,
1061 uint8_t *args, int len)
1063 if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) {
1064 ch->state = pl330_chan_at_barrier;
1068 ch->state = pl330_chan_executing;
1072 /* NULL terminated array of the instruction descriptions. */
1073 static const PL330InsnDesc insn_desc[] = {
1074 { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, },
1075 { .opcode = 0x5c, .opmask = 0xFD, .size = 3, .exec = pl330_dmaadnh, },
1076 { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, },
1077 { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, },
1078 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, },
1079 { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, },
1080 { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, },
1081 { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, },
1082 /* dmastp must be before dmalpend in this list, because their maps
1085 { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, },
1086 { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, },
1087 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, },
1088 { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, },
1089 { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, },
1090 { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, },
1091 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, },
1092 { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, },
1093 { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, },
1094 { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, },
1095 { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, },
1096 { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, },
1097 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, }
1100 /* Instructions which can be issued via debug registers. */
1101 static const PL330InsnDesc debug_insn_desc[] = {
1102 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, },
1103 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, },
1104 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, },
1105 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, }
1108 static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch)
1113 dma_memory_read(ch->parent->mem_as, ch->pc, &opcode, 1,
1114 MEMTXATTRS_UNSPECIFIED);
1115 for (i = 0; insn_desc[i].size; i++) {
1116 if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) {
1117 return &insn_desc[i];
1123 static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn)
1125 uint8_t buf[PL330_INSN_MAXSIZE];
1127 assert(insn->size <= PL330_INSN_MAXSIZE);
1128 dma_memory_read(ch->parent->mem_as, ch->pc, buf, insn->size,
1129 MEMTXATTRS_UNSPECIFIED);
1130 insn->exec(ch, buf[0], &buf[1], insn->size - 1);
1133 static inline void pl330_update_pc(PL330Chan *ch,
1134 const PL330InsnDesc *insn)
1136 ch->pc += insn->size;
1139 /* Try to execute current instruction in channel CH. Number of executed
1140 instructions is returned (0 or 1). */
1141 static int pl330_chan_exec(PL330Chan *ch)
1143 const PL330InsnDesc *insn;
1145 if (ch->state != pl330_chan_executing &&
1146 ch->state != pl330_chan_waiting_periph &&
1147 ch->state != pl330_chan_at_barrier &&
1148 ch->state != pl330_chan_waiting_event) {
1152 insn = pl330_fetch_insn(ch);
1154 trace_pl330_chan_exec_undef();
1155 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
1158 pl330_exec_insn(ch, insn);
1160 pl330_update_pc(ch, insn);
1161 ch->watchdog_timer = 0;
1163 /* WDT only active in exec state */
1164 } else if (ch->state == pl330_chan_executing) {
1165 ch->watchdog_timer++;
1166 if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) {
1167 pl330_fault(ch, PL330_FAULT_LOCKUP_ERR);
1173 /* Try to execute 1 instruction in each channel, one instruction from read
1174 queue and one instruction from write queue. Number of successfully executed
1175 instructions is returned. */
1176 static int pl330_exec_cycle(PL330Chan *channel)
1178 PL330State *s = channel->parent;
1183 uint8_t buf[PL330_MAX_BURST_LEN];
1185 /* Execute one instruction in each channel */
1186 num_exec += pl330_chan_exec(channel);
1188 /* Execute one instruction from read queue */
1189 q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true);
1190 if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) {
1191 int len = q->len - (q->addr & (q->len - 1));
1193 dma_memory_read(s->mem_as, q->addr, buf, len,
1194 MEMTXATTRS_UNSPECIFIED);
1195 trace_pl330_exec_cycle(q->addr, len);
1196 if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) {
1197 pl330_hexdump(buf, len);
1199 fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag);
1200 if (fifo_res == PL330_FIFO_OK) {
1206 pl330_queue_remove_insn(&s->read_queue, q);
1212 /* Execute one instruction from write queue. */
1213 q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true);
1215 int len = q->len - (q->addr & (q->len - 1));
1218 for (i = 0; i < len; i++) {
1222 fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag);
1224 if (fifo_res == PL330_FIFO_OK || q->z) {
1225 dma_memory_write(s->mem_as, q->addr, buf, len,
1226 MEMTXATTRS_UNSPECIFIED);
1227 trace_pl330_exec_cycle(q->addr, len);
1228 if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) {
1229 pl330_hexdump(buf, len);
1235 } else if (fifo_res == PL330_FIFO_STALL) {
1236 pl330_fault(&channel->parent->chan[q->tag],
1237 PL330_FAULT_FIFOEMPTY_ERR);
1241 pl330_queue_remove_insn(&s->write_queue, q);
1248 static int pl330_exec_channel(PL330Chan *channel)
1252 /* TODO: Is it all right to execute everything or should we do per-cycle
1254 while (pl330_exec_cycle(channel)) {
1258 /* Detect deadlock */
1259 if (channel->state == pl330_chan_executing) {
1260 pl330_fault(channel, PL330_FAULT_LOCKUP_ERR);
1262 /* Situation when one of the queues has deadlocked but all channels
1263 * have finished their programs should be impossible.
1269 static inline void pl330_exec(PL330State *s)
1274 insr_exec = pl330_exec_channel(&s->manager);
1276 for (i = 0; i < s->num_chnls; i++) {
1277 insr_exec += pl330_exec_channel(&s->chan[i]);
1279 } while (insr_exec);
1282 static void pl330_exec_cycle_timer(void *opaque)
1284 PL330State *s = (PL330State *)opaque;
1288 /* Stop or restore dma operations */
1290 static void pl330_dma_stop_irq(void *opaque, int irq, int level)
1292 PL330State *s = (PL330State *)opaque;
1294 if (s->periph_busy[irq] != level) {
1295 s->periph_busy[irq] = level;
1296 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
1300 static void pl330_debug_exec(PL330State *s)
1307 const PL330InsnDesc *insn;
1309 s->debug_status = 1;
1310 chan_id = (s->dbg[0] >> 8) & 0x07;
1311 opcode = (s->dbg[0] >> 16) & 0xff;
1312 args[0] = (s->dbg[0] >> 24) & 0xff;
1313 args[1] = (s->dbg[1] >> 0) & 0xff;
1314 args[2] = (s->dbg[1] >> 8) & 0xff;
1315 args[3] = (s->dbg[1] >> 16) & 0xff;
1316 args[4] = (s->dbg[1] >> 24) & 0xff;
1317 trace_pl330_debug_exec(chan_id);
1318 if (s->dbg[0] & 1) {
1319 ch = &s->chan[chan_id];
1324 for (i = 0; debug_insn_desc[i].size; i++) {
1325 if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) {
1326 insn = &debug_insn_desc[i];
1330 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR);
1334 insn->exec(ch, opcode, args, insn->size - 1);
1335 if (ch->fault_type) {
1336 ch->fault_type |= PL330_FAULT_DBG_INSTR;
1339 trace_pl330_debug_exec_stall();
1340 qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not "
1343 s->debug_status = 0;
1346 /* IOMEM mapped registers */
1348 static void pl330_iomem_write(void *opaque, hwaddr offset,
1349 uint64_t value, unsigned size)
1351 PL330State *s = (PL330State *) opaque;
1354 trace_pl330_iomem_write((unsigned)offset, (unsigned)value);
1357 case PL330_REG_INTEN:
1360 case PL330_REG_INTCLR:
1361 for (i = 0; i < s->num_events; i++) {
1362 if (s->int_status & s->inten & value & (1 << i)) {
1363 trace_pl330_iomem_write_clr(i);
1364 qemu_irq_lower(s->irq[i]);
1367 s->ev_status &= ~(value & s->inten);
1368 s->int_status &= ~(value & s->inten);
1370 case PL330_REG_DBGCMD:
1371 if ((value & 3) == 0) {
1372 pl330_debug_exec(s);
1375 qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u "
1376 "for offset " HWADDR_FMT_plx "\n", (unsigned)value,
1380 case PL330_REG_DBGINST0:
1383 case PL330_REG_DBGINST1:
1387 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " HWADDR_FMT_plx
1393 static inline uint32_t pl330_iomem_read_imp(void *opaque,
1396 PL330State *s = (PL330State *)opaque;
1401 if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) {
1402 return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2];
1404 if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) {
1405 return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2];
1407 if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) {
1408 offset -= PL330_REG_CHANCTRL;
1409 chan_id = offset >> 5;
1410 if (chan_id >= s->num_chnls) {
1411 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1412 HWADDR_FMT_plx "\n", offset);
1415 switch (offset & 0x1f) {
1417 return s->chan[chan_id].src;
1419 return s->chan[chan_id].dst;
1421 return s->chan[chan_id].control;
1423 return s->chan[chan_id].lc[0];
1425 return s->chan[chan_id].lc[1];
1427 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1428 HWADDR_FMT_plx "\n", offset);
1432 if (offset >= PL330_REG_CSR_BASE && offset < 0x400) {
1433 offset -= PL330_REG_CSR_BASE;
1434 chan_id = offset >> 3;
1435 if (chan_id >= s->num_chnls) {
1436 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1437 HWADDR_FMT_plx "\n", offset);
1440 switch ((offset >> 2) & 1) {
1442 res = (s->chan[chan_id].ns << 21) |
1443 (s->chan[chan_id].wakeup << 4) |
1444 (s->chan[chan_id].state) |
1445 (s->chan[chan_id].wfp_sbp << 14);
1448 return s->chan[chan_id].pc;
1450 qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n");
1454 if (offset >= PL330_REG_FTR_BASE && offset < 0x100) {
1455 offset -= PL330_REG_FTR_BASE;
1456 chan_id = offset >> 2;
1457 if (chan_id >= s->num_chnls) {
1458 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1459 HWADDR_FMT_plx "\n", offset);
1462 return s->chan[chan_id].fault_type;
1466 return (s->manager.ns << 9) | (s->manager.wakeup << 4) |
1467 (s->manager.state & 0xf);
1469 return s->manager.pc;
1470 case PL330_REG_INTEN:
1472 case PL330_REG_INT_EVENT_RIS:
1473 return s->ev_status;
1474 case PL330_REG_INTMIS:
1475 return s->int_status;
1476 case PL330_REG_INTCLR:
1477 /* Documentation says that we can't read this register
1478 * but linux kernel does it
1481 case PL330_REG_FSRD:
1482 return s->manager.state ? 1 : 0;
1483 case PL330_REG_FSRC:
1485 for (i = 0; i < s->num_chnls; i++) {
1486 if (s->chan[i].state == pl330_chan_fault ||
1487 s->chan[i].state == pl330_chan_fault_completing) {
1492 case PL330_REG_FTRD:
1493 return s->manager.fault_type;
1494 case PL330_REG_DBGSTATUS:
1495 return s->debug_status;
1497 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1498 HWADDR_FMT_plx "\n", offset);
1503 static uint64_t pl330_iomem_read(void *opaque, hwaddr offset,
1506 uint32_t ret = pl330_iomem_read_imp(opaque, offset);
1507 trace_pl330_iomem_read((uint32_t)offset, ret);
1511 static const MemoryRegionOps pl330_ops = {
1512 .read = pl330_iomem_read,
1513 .write = pl330_iomem_write,
1514 .endianness = DEVICE_NATIVE_ENDIAN,
1516 .min_access_size = 4,
1517 .max_access_size = 4,
1521 /* Controller logic and initialization */
1523 static void pl330_chan_reset(PL330Chan *ch)
1528 ch->state = pl330_chan_stopped;
1529 ch->watchdog_timer = 0;
1536 static void pl330_reset(DeviceState *d)
1539 PL330State *s = PL330(d);
1544 s->debug_status = 0;
1545 s->num_faulting = 0;
1546 s->manager.ns = s->mgr_ns_at_rst;
1547 pl330_fifo_reset(&s->fifo);
1548 pl330_queue_reset(&s->read_queue);
1549 pl330_queue_reset(&s->write_queue);
1551 for (i = 0; i < s->num_chnls; i++) {
1552 pl330_chan_reset(&s->chan[i]);
1554 for (i = 0; i < s->num_periph_req; i++) {
1555 s->periph_busy[i] = 0;
1558 timer_del(s->timer);
1561 static void pl330_realize(DeviceState *dev, Error **errp)
1564 PL330State *s = PL330(dev);
1566 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort);
1567 memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s,
1568 "dma", PL330_IOMEM_SIZE);
1569 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1572 error_setg(errp, "'memory' link is not set");
1574 } else if (s->mem_mr == get_system_memory()) {
1575 /* Avoid creating new AS for system memory. */
1576 s->mem_as = &address_space_memory;
1578 s->mem_as = g_new0(AddressSpace, 1);
1579 address_space_init(s->mem_as, s->mem_mr,
1580 memory_region_name(s->mem_mr));
1583 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s);
1585 s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) |
1586 (s->num_periph_req > 0 ? 1 : 0) |
1587 ((s->num_chnls - 1) & 0x7) << 4 |
1588 ((s->num_periph_req - 1) & 0x1f) << 12 |
1589 ((s->num_events - 1) & 0x1f) << 17;
1591 switch (s->i_cache_len) {
1605 error_setg(errp, "Bad value for i-cache_len property: %" PRIx8,
1609 s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4;
1611 s->chan = g_new0(PL330Chan, s->num_chnls);
1612 s->hi_seqn = g_new0(uint8_t, s->num_chnls);
1613 s->lo_seqn = g_new0(uint8_t, s->num_chnls);
1614 for (i = 0; i < s->num_chnls; i++) {
1615 s->chan[i].parent = s;
1616 s->chan[i].tag = (uint8_t)i;
1618 s->manager.parent = s;
1619 s->manager.tag = s->num_chnls;
1620 s->manager.is_manager = true;
1622 s->irq = g_new0(qemu_irq, s->num_events);
1623 for (i = 0; i < s->num_events; i++) {
1624 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1627 qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM);
1629 switch (s->data_width) {
1631 s->cfg[CFG_CRD] |= 0x2;
1634 s->cfg[CFG_CRD] |= 0x3;
1637 s->cfg[CFG_CRD] |= 0x4;
1640 error_setg(errp, "Bad value for data_width property: %" PRIx8,
1645 s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 |
1646 ((s->wr_q_dep - 1) & 0xf) << 8 |
1647 ((s->rd_cap - 1) & 0x7) << 12 |
1648 ((s->rd_q_dep - 1) & 0xf) << 16 |
1649 ((s->data_buffer_dep - 1) & 0x1ff) << 20;
1651 pl330_queue_init(&s->read_queue, s->rd_q_dep, s);
1652 pl330_queue_init(&s->write_queue, s->wr_q_dep, s);
1653 pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep);
1656 static Property pl330_properties[] = {
1658 DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8),
1659 DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4),
1660 DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16),
1661 DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0),
1663 DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4),
1664 DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8),
1666 DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0),
1667 DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0),
1668 DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0),
1670 DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64),
1671 DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8),
1672 DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16),
1673 DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8),
1674 DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16),
1675 DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256),
1677 DEFINE_PROP_LINK("memory", PL330State, mem_mr,
1678 TYPE_MEMORY_REGION, MemoryRegion *),
1680 DEFINE_PROP_END_OF_LIST(),
1683 static void pl330_class_init(ObjectClass *klass, void *data)
1685 DeviceClass *dc = DEVICE_CLASS(klass);
1687 dc->realize = pl330_realize;
1688 dc->reset = pl330_reset;
1689 device_class_set_props(dc, pl330_properties);
1690 dc->vmsd = &vmstate_pl330;
1693 static const TypeInfo pl330_type_info = {
1695 .parent = TYPE_SYS_BUS_DEVICE,
1696 .instance_size = sizeof(PL330State),
1697 .class_init = pl330_class_init,
1700 static void pl330_register_types(void)
1702 type_register_static(&pl330_type_info);
1705 type_init(pl330_register_types)