2 * GPIO device simulation in PKUnity SoC
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
12 #include "qemu/osdep.h"
13 #include "hw/sysbus.h"
14 #include "qom/object.h"
17 #include "hw/unicore32/puv3.h"
18 #include "qemu/module.h"
21 #define TYPE_PUV3_GPIO "puv3_gpio"
22 OBJECT_DECLARE_SIMPLE_TYPE(PUV3GPIOState, PUV3_GPIO)
24 struct PUV3GPIOState {
25 SysBusDevice parent_obj;
35 static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
38 PUV3GPIOState *s = opaque;
52 qemu_log_mask(LOG_GUEST_ERROR,
53 "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
56 DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
61 static void puv3_gpio_write(void *opaque, hwaddr offset,
62 uint64_t value, unsigned size)
64 PUV3GPIOState *s = opaque;
66 DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
72 if (s->reg_GPDR & value) {
75 qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
80 if (s->reg_GPDR & value) {
81 s->reg_GPLR &= ~value;
83 qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
95 qemu_log_mask(LOG_GUEST_ERROR,
96 "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
101 static const MemoryRegionOps puv3_gpio_ops = {
102 .read = puv3_gpio_read,
103 .write = puv3_gpio_write,
105 .min_access_size = 4,
106 .max_access_size = 4,
108 .endianness = DEVICE_NATIVE_ENDIAN,
111 static void puv3_gpio_realize(DeviceState *dev, Error **errp)
113 PUV3GPIOState *s = PUV3_GPIO(dev);
114 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
119 /* FIXME: these irqs not handled yet */
120 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW0]);
121 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW1]);
122 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW2]);
123 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW3]);
124 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW4]);
125 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW5]);
126 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW6]);
127 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW7]);
128 sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOHIGH]);
130 memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio",
132 sysbus_init_mmio(sbd, &s->iomem);
135 static void puv3_gpio_class_init(ObjectClass *klass, void *data)
137 DeviceClass *dc = DEVICE_CLASS(klass);
139 dc->realize = puv3_gpio_realize;
142 static const TypeInfo puv3_gpio_info = {
143 .name = TYPE_PUV3_GPIO,
144 .parent = TYPE_SYS_BUS_DEVICE,
145 .instance_size = sizeof(PUV3GPIOState),
146 .class_init = puv3_gpio_class_init,
149 static void puv3_gpio_register_type(void)
151 type_register_static(&puv3_gpio_info);
154 type_init(puv3_gpio_register_type)