2 * TPR optimization for 32-bit Windows guests (XP and Server 2003)
4 * Copyright (C) 2007-2008 Qumranet Technologies
5 * Copyright (C) 2012 Jan Kiszka, Siemens AG
7 * This work is licensed under the terms of the GNU GPL version 2, or
8 * (at your option) any later version. See the COPYING file in the
12 #include "qemu/osdep.h"
13 #include "qemu/module.h"
14 #include "sysemu/sysemu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/hw_accel.h"
17 #include "sysemu/kvm.h"
18 #include "sysemu/runstate.h"
19 #include "hw/i386/apic_internal.h"
20 #include "hw/sysbus.h"
21 #include "hw/boards.h"
22 #include "migration/vmstate.h"
23 #include "qom/object.h"
25 #define VAPIC_IO_PORT 0x7e
27 #define VAPIC_CPU_SHIFT 7
29 #define ROM_BLOCK_SIZE 512
30 #define ROM_BLOCK_MASK (~(ROM_BLOCK_SIZE - 1))
32 typedef enum VAPICMode {
38 typedef struct VAPICHandlers {
42 uint32_t get_tpr_stack;
43 } QEMU_PACKED VAPICHandlers;
45 typedef struct GuestROMState {
53 uint32_t real_tpr_addr;
56 } QEMU_PACKED GuestROMState;
58 struct VAPICROMState {
63 uint32_t rom_state_paddr;
64 uint32_t rom_state_vaddr;
66 uint32_t real_tpr_addr;
67 GuestROMState rom_state;
69 bool rom_mapped_writable;
70 VMChangeStateEntry *vmsentry;
73 #define TYPE_VAPIC "kvmvapic"
74 OBJECT_DECLARE_SIMPLE_TYPE(VAPICROMState, VAPIC)
76 #define TPR_INSTR_ABS_MODRM 0x1
77 #define TPR_INSTR_MATCH_MODRM_REG 0x2
79 typedef struct TPRInstruction {
88 /* must be sorted by length, shortest first */
89 static const TPRInstruction tpr_instr[] = {
90 { /* mov abs to eax */
92 .access = TPR_ACCESS_READ,
96 { /* mov eax to abs */
98 .access = TPR_ACCESS_WRITE,
102 { /* mov r32 to r/m32 */
104 .flags = TPR_INSTR_ABS_MODRM,
105 .access = TPR_ACCESS_WRITE,
109 { /* mov r/m32 to r32 */
111 .flags = TPR_INSTR_ABS_MODRM,
112 .access = TPR_ACCESS_READ,
119 .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
120 .access = TPR_ACCESS_READ,
124 { /* mov imm32, r/m32 (c7/0) */
127 .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
128 .access = TPR_ACCESS_WRITE,
134 static void read_guest_rom_state(VAPICROMState *s)
136 cpu_physical_memory_read(s->rom_state_paddr, &s->rom_state,
137 sizeof(GuestROMState));
140 static void write_guest_rom_state(VAPICROMState *s)
142 cpu_physical_memory_write(s->rom_state_paddr, &s->rom_state,
143 sizeof(GuestROMState));
146 static void update_guest_rom_state(VAPICROMState *s)
148 read_guest_rom_state(s);
150 s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr);
151 s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT);
153 write_guest_rom_state(s);
156 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
158 CPUState *cs = env_cpu(env);
162 if (s->state == VAPIC_ACTIVE) {
166 * If there is no prior TPR access instruction we could analyze (which is
167 * the case after resume from hibernation), we need to scan the possible
168 * virtual address space for the APIC mapping.
170 for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) {
171 paddr = cpu_get_phys_page_debug(cs, addr);
172 if (paddr != APIC_DEFAULT_ADDRESS) {
175 s->real_tpr_addr = addr + 0x80;
176 update_guest_rom_state(s);
182 static uint8_t modrm_reg(uint8_t modrm)
184 return (modrm >> 3) & 7;
187 static bool is_abs_modrm(uint8_t modrm)
189 return (modrm & 0xc7) == 0x05;
192 static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
194 return opcode[0] == instr->opcode &&
195 (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) &&
196 (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) ||
197 modrm_reg(opcode[1]) == instr->modrm_reg);
200 static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu,
201 target_ulong *pip, TPRAccess access)
203 CPUState *cs = CPU(cpu);
204 const TPRInstruction *instr;
205 target_ulong ip = *pip;
207 uint32_t real_tpr_addr;
210 if ((ip & 0xf0000000ULL) != 0x80000000ULL &&
211 (ip & 0xf0000000ULL) != 0xe0000000ULL) {
216 * Early Windows 2003 SMP initialization contains a
220 * instruction that is patched by TPR optimization. The problem is that
221 * RSP, used by the patched instruction, is zero, so the guest gets a
222 * double fault and dies.
224 if (cpu->env.regs[R_ESP] == 0) {
228 if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
230 * KVM without kernel-based TPR access reporting will pass an IP that
231 * points after the accessing instruction. So we need to look backward
232 * to find the reason.
234 for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
235 instr = &tpr_instr[i];
236 if (instr->access != access) {
239 if (cpu_memory_rw_debug(cs, ip - instr->length, opcode,
240 sizeof(opcode), 0) < 0) {
243 if (opcode_matches(opcode, instr)) {
250 if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) {
253 for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
254 instr = &tpr_instr[i];
255 if (opcode_matches(opcode, instr)) {
264 * Grab the virtual TPR address from the instruction
265 * and update the cached values.
267 if (cpu_memory_rw_debug(cs, ip + instr->addr_offset,
268 (void *)&real_tpr_addr,
269 sizeof(real_tpr_addr), 0) < 0) {
272 real_tpr_addr = le32_to_cpu(real_tpr_addr);
273 if ((real_tpr_addr & 0xfff) != 0x80) {
276 s->real_tpr_addr = real_tpr_addr;
277 update_guest_rom_state(s);
283 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
285 CPUState *cs = env_cpu(env);
287 uint32_t rom_state_vaddr;
288 uint32_t pos, patch, offset;
290 /* nothing to do if already activated */
291 if (s->state == VAPIC_ACTIVE) {
295 /* bail out if ROM init code was not executed (missing ROM?) */
296 if (s->state == VAPIC_INACTIVE) {
300 /* find out virtual address of the ROM */
301 rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000);
302 paddr = cpu_get_phys_page_debug(cs, rom_state_vaddr);
306 paddr += rom_state_vaddr & ~TARGET_PAGE_MASK;
307 if (paddr != s->rom_state_paddr) {
310 read_guest_rom_state(s);
311 if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) {
314 s->rom_state_vaddr = rom_state_vaddr;
316 /* fixup addresses in ROM if needed */
317 if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) {
320 for (pos = le32_to_cpu(s->rom_state.fixup_start);
321 pos < le32_to_cpu(s->rom_state.fixup_end);
323 cpu_physical_memory_read(paddr + pos - s->rom_state.vaddr,
324 &offset, sizeof(offset));
325 offset = le32_to_cpu(offset);
326 cpu_physical_memory_read(paddr + offset, &patch, sizeof(patch));
327 patch = le32_to_cpu(patch);
328 patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr);
329 patch = cpu_to_le32(patch);
330 cpu_physical_memory_write(paddr + offset, &patch, sizeof(patch));
332 read_guest_rom_state(s);
333 s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) -
334 le32_to_cpu(s->rom_state.vaddr);
340 * Tries to read the unique processor number from the Kernel Processor Control
341 * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR
342 * cannot be accessed or is considered invalid. This also ensures that we are
343 * not patching the wrong guest.
345 static int get_kpcr_number(X86CPU *cpu)
347 CPUX86State *env = &cpu->env;
355 if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base,
356 (void *)&kpcr, sizeof(kpcr), 0) < 0 ||
357 kpcr.self != env->segs[R_FS].base) {
363 static int vapic_enable(VAPICROMState *s, X86CPU *cpu)
365 int cpu_number = get_kpcr_number(cpu);
367 static const uint8_t enabled = 1;
369 if (cpu_number < 0) {
372 vapic_paddr = s->vapic_paddr +
373 (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
374 cpu_physical_memory_write(vapic_paddr + offsetof(VAPICState, enabled),
375 &enabled, sizeof(enabled));
376 apic_enable_vapic(cpu->apic_state, vapic_paddr);
378 s->state = VAPIC_ACTIVE;
383 static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte)
385 cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1);
388 static void patch_call(X86CPU *cpu, target_ulong ip, uint32_t target)
392 offset = cpu_to_le32(target - ip - 5);
393 patch_byte(cpu, ip, 0xe8); /* call near */
394 cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1);
397 typedef struct PatchInfo {
398 VAPICHandlers *handler;
402 static void do_patch_instruction(CPUState *cs, run_on_cpu_data data)
404 X86CPU *x86_cpu = X86_CPU(cs);
405 PatchInfo *info = (PatchInfo *) data.host_ptr;
406 VAPICHandlers *handlers = info->handler;
407 target_ulong ip = info->ip;
411 cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0);
414 case 0x89: /* mov r32 to r/m32 */
415 patch_byte(x86_cpu, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */
416 patch_call(x86_cpu, ip + 1, handlers->set_tpr);
418 case 0x8b: /* mov r/m32 to r32 */
419 patch_byte(x86_cpu, ip, 0x90);
420 patch_call(x86_cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
422 case 0xa1: /* mov abs to eax */
423 patch_call(x86_cpu, ip, handlers->get_tpr[0]);
425 case 0xa3: /* mov eax to abs */
426 patch_call(x86_cpu, ip, handlers->set_tpr_eax);
428 case 0xc7: /* mov imm32, r/m32 (c7/0) */
429 patch_byte(x86_cpu, ip, 0x68); /* push imm32 */
430 cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0);
431 cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1);
432 patch_call(x86_cpu, ip + 5, handlers->set_tpr);
434 case 0xff: /* push r/m32 */
435 patch_byte(x86_cpu, ip, 0x50); /* push eax */
436 patch_call(x86_cpu, ip + 1, handlers->get_tpr_stack);
445 static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
447 MachineState *ms = MACHINE(qdev_get_machine());
448 CPUState *cs = CPU(cpu);
449 VAPICHandlers *handlers;
452 if (ms->smp.cpus == 1) {
453 handlers = &s->rom_state.up;
455 handlers = &s->rom_state.mp;
458 info = g_new(PatchInfo, 1);
459 info->handler = handlers;
462 async_safe_run_on_cpu(cs, do_patch_instruction, RUN_ON_CPU_HOST_PTR(info));
465 void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip,
468 VAPICROMState *s = VAPIC(dev);
469 X86CPU *cpu = X86_CPU(cs);
470 CPUX86State *env = &cpu->env;
472 cpu_synchronize_state(cs);
474 if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) {
475 if (s->state == VAPIC_ACTIVE) {
476 vapic_enable(s, cpu);
480 if (update_rom_mapping(s, env, ip) < 0) {
483 if (vapic_enable(s, cpu) < 0) {
486 patch_instruction(s, cpu, ip);
489 typedef struct VAPICEnableTPRReporting {
492 } VAPICEnableTPRReporting;
494 static void vapic_do_enable_tpr_reporting(CPUState *cpu, run_on_cpu_data data)
496 VAPICEnableTPRReporting *info = data.host_ptr;
497 apic_enable_tpr_access_reporting(info->apic, info->enable);
500 static void vapic_enable_tpr_reporting(bool enable)
502 VAPICEnableTPRReporting info = {
510 info.apic = cpu->apic_state;
511 run_on_cpu(cs, vapic_do_enable_tpr_reporting, RUN_ON_CPU_HOST_PTR(&info));
515 static void vapic_reset(DeviceState *dev)
517 VAPICROMState *s = VAPIC(dev);
519 s->state = VAPIC_INACTIVE;
520 s->rom_state_paddr = 0;
521 vapic_enable_tpr_reporting(false);
525 * Set the IRQ polling hypercalls to the supported variant:
526 * - vmcall if using KVM in-kernel irqchip
527 * - 32-bit VAPIC port write otherwise
529 static int patch_hypercalls(VAPICROMState *s)
531 hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
532 static const uint8_t vmcall_pattern[] = { /* vmcall */
533 0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
535 static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */
536 0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e
538 uint8_t alternates[2];
539 const uint8_t *pattern;
540 const uint8_t *patch;
544 rom = g_malloc(s->rom_size);
545 cpu_physical_memory_read(rom_paddr, rom, s->rom_size);
547 for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) {
548 if (kvm_irqchip_in_kernel()) {
549 pattern = outl_pattern;
550 alternates[0] = outl_pattern[7];
551 alternates[1] = outl_pattern[7];
552 patch = &vmcall_pattern[5];
554 pattern = vmcall_pattern;
555 alternates[0] = vmcall_pattern[7];
556 alternates[1] = 0xd9; /* AMD's VMMCALL */
557 patch = &outl_pattern[5];
559 if (memcmp(rom + pos, pattern, 7) == 0 &&
560 (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) {
561 cpu_physical_memory_write(rom_paddr + pos + 5, patch, 3);
563 * Don't flush the tb here. Under ordinary conditions, the patched
564 * calls are miles away from the current IP. Under malicious
565 * conditions, the guest could trick us to crash.
575 * For TCG mode or the time KVM honors read-only memory regions, we need to
576 * enable write access to the option ROM so that variables can be updated by
579 static int vapic_map_rom_writable(VAPICROMState *s)
581 hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
582 MemoryRegionSection section;
587 as = sysbus_address_space(&s->busdev);
589 if (s->rom_mapped_writable) {
590 memory_region_del_subregion(as, &s->rom);
591 object_unparent(OBJECT(&s->rom));
594 /* grab RAM memory region (region @rom_paddr may still be pc.rom) */
595 section = memory_region_find(as, 0, 1);
597 /* read ROM size from RAM region */
598 if (rom_paddr + 2 >= memory_region_size(section.mr)) {
601 ram = memory_region_get_ram_ptr(section.mr);
602 rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE;
606 s->rom_size = rom_size;
608 /* We need to round to avoid creating subpages
609 * from which we cannot run code. */
610 rom_size += rom_paddr & ~TARGET_PAGE_MASK;
611 rom_paddr &= TARGET_PAGE_MASK;
612 rom_size = TARGET_PAGE_ALIGN(rom_size);
614 memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr,
615 rom_paddr, rom_size);
616 memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000);
617 s->rom_mapped_writable = true;
618 memory_region_unref(section.mr);
623 static int vapic_prepare(VAPICROMState *s)
625 if (vapic_map_rom_writable(s) < 0) {
629 if (patch_hypercalls(s) < 0) {
633 vapic_enable_tpr_reporting(true);
638 static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
641 VAPICROMState *s = opaque;
650 cpu_synchronize_state(current_cpu);
651 cpu = X86_CPU(current_cpu);
655 * The VAPIC supports two PIO-based hypercalls, both via port 0x7E.
656 * o 16-bit write access:
657 * Reports the option ROM initialization to the hypervisor. Written
658 * value is the offset of the state structure in the ROM.
659 * o 8-bit write access:
660 * Reactivates the VAPIC after a guest hibernation, i.e. after the
661 * option ROM content has been re-initialized by a guest power cycle.
662 * o 32-bit write access:
663 * Poll for pending IRQs, considering the current VAPIC state.
667 if (s->state == VAPIC_INACTIVE) {
668 rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK;
669 s->rom_state_paddr = rom_paddr + data;
671 s->state = VAPIC_STANDBY;
673 if (vapic_prepare(s) < 0) {
674 s->state = VAPIC_INACTIVE;
675 s->rom_state_paddr = 0;
682 * Disable triggering instruction in ROM by writing a NOP.
684 * We cannot do this in TCG mode as the reported IP is not
688 patch_byte(cpu, env->eip - 2, 0x66);
689 patch_byte(cpu, env->eip - 1, 0x90);
693 if (s->state == VAPIC_ACTIVE) {
696 if (update_rom_mapping(s, env, env->eip) < 0) {
699 if (find_real_tpr_addr(s, env) < 0) {
702 vapic_enable(s, cpu);
706 if (!kvm_irqchip_in_kernel()) {
707 apic_poll_irq(cpu->apic_state);
713 static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size)
718 static const MemoryRegionOps vapic_ops = {
719 .write = vapic_write,
721 .endianness = DEVICE_NATIVE_ENDIAN,
724 static void vapic_realize(DeviceState *dev, Error **errp)
726 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
727 VAPICROMState *s = VAPIC(dev);
729 memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2);
730 sysbus_add_io(sbd, VAPIC_IO_PORT, &s->io);
731 sysbus_init_ioports(sbd, VAPIC_IO_PORT, 2);
733 option_rom[nb_option_roms].name = "kvmvapic.bin";
734 option_rom[nb_option_roms].bootindex = -1;
738 static void do_vapic_enable(CPUState *cs, run_on_cpu_data data)
740 VAPICROMState *s = data.host_ptr;
741 X86CPU *cpu = X86_CPU(cs);
743 static const uint8_t enabled = 1;
744 cpu_physical_memory_write(s->vapic_paddr + offsetof(VAPICState, enabled),
745 &enabled, sizeof(enabled));
746 apic_enable_vapic(cpu->apic_state, s->vapic_paddr);
747 s->state = VAPIC_ACTIVE;
750 static void kvmvapic_vm_state_change(void *opaque, bool running,
753 MachineState *ms = MACHINE(qdev_get_machine());
754 VAPICROMState *s = opaque;
761 if (s->state == VAPIC_ACTIVE) {
762 if (ms->smp.cpus == 1) {
763 run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s));
765 zero = g_malloc0(s->rom_state.vapic_size);
766 cpu_physical_memory_write(s->vapic_paddr, zero,
767 s->rom_state.vapic_size);
772 qemu_del_vm_change_state_handler(s->vmsentry);
776 static int vapic_post_load(void *opaque, int version_id)
778 VAPICROMState *s = opaque;
781 * The old implementation of qemu-kvm did not provide the state
782 * VAPIC_STANDBY. Reconstruct it.
784 if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) {
785 s->state = VAPIC_STANDBY;
788 if (s->state != VAPIC_INACTIVE) {
789 if (vapic_prepare(s) < 0) {
796 qemu_add_vm_change_state_handler(kvmvapic_vm_state_change, s);
801 static const VMStateDescription vmstate_handlers = {
802 .name = "kvmvapic-handlers",
804 .minimum_version_id = 1,
805 .fields = (VMStateField[]) {
806 VMSTATE_UINT32(set_tpr, VAPICHandlers),
807 VMSTATE_UINT32(set_tpr_eax, VAPICHandlers),
808 VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8),
809 VMSTATE_UINT32(get_tpr_stack, VAPICHandlers),
810 VMSTATE_END_OF_LIST()
814 static const VMStateDescription vmstate_guest_rom = {
815 .name = "kvmvapic-guest-rom",
817 .minimum_version_id = 1,
818 .fields = (VMStateField[]) {
819 VMSTATE_UNUSED(8), /* signature */
820 VMSTATE_UINT32(vaddr, GuestROMState),
821 VMSTATE_UINT32(fixup_start, GuestROMState),
822 VMSTATE_UINT32(fixup_end, GuestROMState),
823 VMSTATE_UINT32(vapic_vaddr, GuestROMState),
824 VMSTATE_UINT32(vapic_size, GuestROMState),
825 VMSTATE_UINT32(vcpu_shift, GuestROMState),
826 VMSTATE_UINT32(real_tpr_addr, GuestROMState),
827 VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
828 VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
829 VMSTATE_END_OF_LIST()
833 static const VMStateDescription vmstate_vapic = {
834 .name = "kvm-tpr-opt", /* compatible with qemu-kvm VAPIC */
836 .minimum_version_id = 1,
837 .post_load = vapic_post_load,
838 .fields = (VMStateField[]) {
839 VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom,
841 VMSTATE_UINT32(state, VAPICROMState),
842 VMSTATE_UINT32(real_tpr_addr, VAPICROMState),
843 VMSTATE_UINT32(rom_state_vaddr, VAPICROMState),
844 VMSTATE_UINT32(vapic_paddr, VAPICROMState),
845 VMSTATE_UINT32(rom_state_paddr, VAPICROMState),
846 VMSTATE_END_OF_LIST()
850 static void vapic_class_init(ObjectClass *klass, void *data)
852 DeviceClass *dc = DEVICE_CLASS(klass);
854 dc->reset = vapic_reset;
855 dc->vmsd = &vmstate_vapic;
856 dc->realize = vapic_realize;
859 static const TypeInfo vapic_type = {
861 .parent = TYPE_SYS_BUS_DEVICE,
862 .instance_size = sizeof(VAPICROMState),
863 .class_init = vapic_class_init,
866 static void vapic_register(void)
868 type_register_static(&vapic_type);
871 type_init(vapic_register);