2 * QEMU IDE Emulation: PCI VIA82C686B support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "hw/pci/pci.h"
29 #include "migration/vmstate.h"
30 #include "qemu/module.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 #include "sysemu/reset.h"
35 #include "hw/ide/pci.h"
38 static uint64_t bmdma_read(void *opaque, hwaddr addr,
41 BMDMAState *bm = opaque;
45 return ((uint64_t)1 << (size * 8)) - 1;
60 trace_bmdma_read_via(addr, val);
64 static void bmdma_write(void *opaque, hwaddr addr,
65 uint64_t val, unsigned size)
67 BMDMAState *bm = opaque;
73 trace_bmdma_write_via(addr, val);
76 bmdma_cmd_writeb(bm, val);
79 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
85 static const MemoryRegionOps via_bmdma_ops = {
90 static void bmdma_setup_bar(PCIIDEState *d)
94 memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
95 for(i = 0;i < 2; i++) {
96 BMDMAState *bm = &d->bmdma[i];
98 memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
100 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
101 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
102 &bmdma_addr_ioport_ops, bm, "bmdma", 4);
103 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
107 static void via_ide_set_irq(void *opaque, int n, int level)
109 PCIDevice *d = PCI_DEVICE(opaque);
112 d->config[0x70 + n * 8] |= 0x80;
114 d->config[0x70 + n * 8] &= ~0x80;
117 level = (d->config[0x70] & 0x80) || (d->config[0x78] & 0x80);
118 n = pci_get_byte(d->config + PCI_INTERRUPT_LINE);
120 qemu_set_irq(isa_get_irq(NULL, n), level);
124 static void via_ide_reset(void *opaque)
126 PCIIDEState *d = opaque;
127 PCIDevice *pd = PCI_DEVICE(d);
128 uint8_t *pci_conf = pd->config;
131 for (i = 0; i < 2; i++) {
132 ide_bus_reset(&d->bus[i]);
135 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT);
136 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
137 PCI_STATUS_DEVSEL_MEDIUM);
139 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
140 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
141 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
142 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
143 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
144 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
146 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
147 pci_set_long(pci_conf + 0x40, 0x0a090600);
148 /* IDE misc configuration 1/2/3 */
149 pci_set_long(pci_conf + 0x44, 0x00c00068);
150 /* IDE Timing control */
151 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
152 /* IDE Address Setup Time */
153 pci_set_long(pci_conf + 0x4c, 0x000000ff);
154 /* UltraDMA Extended Timing Control*/
155 pci_set_long(pci_conf + 0x50, 0x07070707);
156 /* UltraDMA FIFO Control */
157 pci_set_long(pci_conf + 0x54, 0x00000004);
158 /* IDE primary sector size */
159 pci_set_long(pci_conf + 0x60, 0x00000200);
160 /* IDE secondary sector size */
161 pci_set_long(pci_conf + 0x68, 0x00000200);
163 pci_set_long(pci_conf + 0xc0, 0x00020001);
166 static void via_ide_realize(PCIDevice *dev, Error **errp)
168 PCIIDEState *d = PCI_IDE(dev);
169 uint8_t *pci_conf = dev->config;
172 pci_config_set_prog_interface(pci_conf, 0x8f); /* native PCI ATA mode */
173 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
174 dev->wmask[PCI_INTERRUPT_LINE] = 0xf;
176 qemu_register_reset(via_ide_reset, d);
178 memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
179 &d->bus[0], "via-ide0-data", 8);
180 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
182 memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
183 &d->bus[0], "via-ide0-cmd", 4);
184 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
186 memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
187 &d->bus[1], "via-ide1-data", 8);
188 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
190 memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
191 &d->bus[1], "via-ide1-cmd", 4);
192 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
195 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
197 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
199 for (i = 0; i < 2; i++) {
200 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
201 ide_init2(&d->bus[i], qemu_allocate_irq(via_ide_set_irq, d, i));
203 bmdma_init(&d->bus[i], &d->bmdma[i], d);
204 d->bmdma[i].bus = &d->bus[i];
205 ide_register_restart_cb(&d->bus[i]);
209 static void via_ide_exitfn(PCIDevice *dev)
211 PCIIDEState *d = PCI_IDE(dev);
214 for (i = 0; i < 2; ++i) {
215 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
216 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
220 void via_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
224 dev = pci_create_simple(bus, devfn, "via-ide");
225 pci_ide_create_devs(dev, hd_table);
228 static void via_ide_class_init(ObjectClass *klass, void *data)
230 DeviceClass *dc = DEVICE_CLASS(klass);
231 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
233 k->realize = via_ide_realize;
234 k->exit = via_ide_exitfn;
235 k->vendor_id = PCI_VENDOR_ID_VIA;
236 k->device_id = PCI_DEVICE_ID_VIA_IDE;
238 k->class_id = PCI_CLASS_STORAGE_IDE;
239 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
242 static const TypeInfo via_ide_info = {
244 .parent = TYPE_PCI_IDE,
245 .class_init = via_ide_class_init,
248 static void via_ide_register_types(void)
250 type_register_static(&via_ide_info);
253 type_init(via_ide_register_types)