4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009, 2010, 2011
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on piix.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu/osdep.h"
34 #include "qapi/error.h"
35 #include "qapi/visitor.h"
36 #include "qemu/range.h"
37 #include "hw/isa/isa.h"
38 #include "migration/vmstate.h"
40 #include "hw/isa/apm.h"
41 #include "hw/pci/pci.h"
42 #include "hw/pci/pci_bridge.h"
43 #include "hw/i386/ich9.h"
44 #include "hw/acpi/acpi.h"
45 #include "hw/acpi/ich9.h"
46 #include "hw/pci/pci_bus.h"
47 #include "hw/qdev-properties.h"
48 #include "sysemu/runstate.h"
49 #include "sysemu/sysemu.h"
50 #include "hw/core/cpu.h"
51 #include "hw/nvram/fw_cfg.h"
52 #include "qemu/cutils.h"
54 /*****************************************************************************/
55 /* ICH9 LPC PCI to ISA bridge */
57 static void ich9_lpc_reset(DeviceState *qdev);
59 /* chipset configuration register
60 * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
62 * Although it's not pci configuration space, it's little endian as Intel.
65 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
68 for (intx = 0; intx < PCI_NUM_PINS; intx++) {
69 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
73 static void ich9_cc_update(ICH9LPCState *lpc)
78 const int reg_offsets[] = {
89 /* D{25 - 31}IR, but D30IR is read only to 0. */
90 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
94 ich9_cc_update_ir(lpc->irr[slot],
95 pci_get_word(lpc->chip_config + *offset));
100 * It is arbitrarily decided how INTx lines of PCI devices behind
101 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
102 * INT[A-D] are connected to PIRQ[E-H]
104 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
105 lpc->irr[30][pci_intx] = pci_intx + 4;
109 static void ich9_cc_init(ICH9LPCState *lpc)
114 /* the default irq routing is arbitrary as long as it matches with
115 * acpi irq routing table.
116 * The one that is incompatible with piix_pci(= bochs) one is
117 * intentionally chosen to let the users know that the different
120 * int[A-D] -> pirq[E-F]
121 * avoid pirq A-D because they are used for pci express port
123 for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
124 for (intx = 0; intx < PCI_NUM_PINS; intx++) {
125 lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
131 static void ich9_cc_reset(ICH9LPCState *lpc)
133 uint8_t *c = lpc->chip_config;
135 memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
137 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
138 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
139 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
140 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
141 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
142 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
143 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
144 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
149 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
151 *addr &= ICH9_CC_ADDR_MASK;
152 if (*addr + *len >= ICH9_CC_SIZE) {
153 *len = ICH9_CC_SIZE - *addr;
157 /* val: little endian */
158 static void ich9_cc_write(void *opaque, hwaddr addr,
159 uint64_t val, unsigned len)
161 ICH9LPCState *lpc = (ICH9LPCState *)opaque;
163 ich9_cc_addr_len(&addr, &len);
164 memcpy(lpc->chip_config + addr, &val, len);
165 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
169 /* return value: little endian */
170 static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
173 ICH9LPCState *lpc = (ICH9LPCState *)opaque;
176 ich9_cc_addr_len(&addr, &len);
177 memcpy(&val, lpc->chip_config + addr, len);
183 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
185 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
186 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
189 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num,
190 int *pic_irq, int *pic_dis)
193 case 0 ... 3: /* A-D */
194 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num],
197 case 4 ... 7: /* E-H */
198 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)],
207 /* gsi: i8259+ioapic irq 0-15, otherwise assert */
208 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
212 assert(gsi < ICH9_LPC_PIC_NUM_PINS);
214 /* The pic level is the logical OR of all the PCI irqs mapped to it */
216 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
219 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
220 if (!tmp_dis && tmp_irq == gsi) {
221 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i);
224 if (gsi == lpc->sci_gsi) {
225 pic_level |= lpc->sci_level;
228 qemu_set_irq(lpc->gsi[gsi], pic_level);
231 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
232 static int ich9_pirq_to_gsi(int pirq)
234 return pirq + ICH9_LPC_PIC_NUM_PINS;
237 static int ich9_gsi_to_pirq(int gsi)
239 return gsi - ICH9_LPC_PIC_NUM_PINS;
242 /* gsi: ioapic irq 16-23, otherwise assert */
243 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
247 assert(gsi >= ICH9_LPC_PIC_NUM_PINS);
249 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi));
250 if (gsi == lpc->sci_gsi) {
251 level |= lpc->sci_level;
254 qemu_set_irq(lpc->gsi[gsi], level);
257 void ich9_lpc_set_irq(void *opaque, int pirq, int level)
259 ICH9LPCState *lpc = opaque;
260 int pic_irq, pic_dis;
263 assert(pirq < ICH9_LPC_NB_PIRQS);
265 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq));
266 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
267 ich9_lpc_update_pic(lpc, pic_irq);
270 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to
271 * a given device irq pin.
273 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
275 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
276 PCIBus *pci_bus = PCI_BUS(bus);
277 PCIDevice *lpc_pdev =
278 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)];
279 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev);
281 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
284 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
286 ICH9LPCState *lpc = opaque;
291 assert(0 <= pirq_pin);
292 assert(pirq_pin < ICH9_LPC_NB_PIRQS);
294 route.mode = PCI_INTX_ENABLED;
295 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
297 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
300 route.mode = PCI_INTX_DISABLED;
304 route.irq = ich9_pirq_to_gsi(pirq_pin);
310 void ich9_generate_smi(void)
312 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
315 /* Returns -1 on error, IRQ number on success */
316 static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
318 uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] &
319 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK;
321 case ICH9_LPC_ACPI_CTRL_9:
323 case ICH9_LPC_ACPI_CTRL_10:
325 case ICH9_LPC_ACPI_CTRL_11:
327 case ICH9_LPC_ACPI_CTRL_20:
329 case ICH9_LPC_ACPI_CTRL_21:
333 qemu_log_mask(LOG_GUEST_ERROR,
334 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel);
340 static void ich9_set_sci(void *opaque, int irq_num, int level)
342 ICH9LPCState *lpc = opaque;
345 assert(irq_num == 0);
347 if (level == lpc->sci_level) {
350 lpc->sci_level = level;
357 if (irq >= ICH9_LPC_PIC_NUM_PINS) {
358 ich9_lpc_update_apic(lpc, irq);
360 ich9_lpc_update_pic(lpc, irq);
364 static void smi_features_ok_callback(void *opaque)
366 ICH9LPCState *lpc = opaque;
367 uint64_t guest_features;
368 uint64_t guest_cpu_hotplug_features;
370 if (lpc->smi_features_ok) {
371 /* negotiation already complete, features locked */
375 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features);
376 le64_to_cpus(&guest_features);
377 if (guest_features & ~lpc->smi_host_features) {
378 /* guest requests invalid features, leave @features_ok at zero */
382 guest_cpu_hotplug_features = guest_features &
383 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) |
384 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
385 if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) &&
386 guest_cpu_hotplug_features) {
388 * cpu hot-[un]plug with SMI requires SMI broadcast,
389 * leave @features_ok at zero
394 if (guest_cpu_hotplug_features ==
395 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) {
396 /* cpu hot-unplug is unsupported without cpu-hotplug */
400 /* valid feature subset requested, lock it down, report success */
401 lpc->smi_negotiated_features = guest_features;
402 lpc->smi_features_ok = 1;
405 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
407 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
409 FWCfgState *fw_cfg = fw_cfg_find();
411 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
412 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
414 if (lpc->smi_host_features && fw_cfg) {
415 uint64_t host_features_le;
417 host_features_le = cpu_to_le64(lpc->smi_host_features);
418 memcpy(lpc->smi_host_features_le, &host_features_le,
419 sizeof host_features_le);
420 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features",
421 lpc->smi_host_features_le,
422 sizeof lpc->smi_host_features_le);
424 /* The other two guest-visible fields are cleared on device reset, we
425 * just link them into fw_cfg here.
427 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features",
429 lpc->smi_guest_features_le,
430 sizeof lpc->smi_guest_features_le,
432 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok",
433 smi_features_ok_callback, NULL, lpc,
434 &lpc->smi_features_ok,
435 sizeof lpc->smi_features_ok,
439 ich9_lpc_reset(DEVICE(lpc));
444 static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
446 ICH9LPCState *lpc = arg;
448 /* ACPI specs 3.0, 4.7.2.5 */
449 acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
450 val == ICH9_APM_ACPI_ENABLE,
451 val == ICH9_APM_ACPI_DISABLE);
452 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
456 /* SMI_EN = PMBASE + 30. SMI control and enable register */
457 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
458 if (lpc->smi_negotiated_features &
459 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) {
462 cpu_interrupt(cs, CPU_INTERRUPT_SMI);
465 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI);
472 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc)
474 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
475 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL);
478 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) {
479 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
484 ich9_pm_iospace_update(&lpc->pm, pm_io_base);
486 new_gsi = ich9_lpc_sci_irq(lpc);
490 if (lpc->sci_level && new_gsi != lpc->sci_gsi) {
491 qemu_set_irq(lpc->pm.irq, 0);
492 lpc->sci_gsi = new_gsi;
493 qemu_set_irq(lpc->pm.irq, 1);
495 lpc->sci_gsi = new_gsi;
499 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old)
501 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
503 if (rcba_old & ICH9_LPC_RCBA_EN) {
504 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem);
506 if (rcba & ICH9_LPC_RCBA_EN) {
507 memory_region_add_subregion_overlap(get_system_memory(),
508 rcba & ICH9_LPC_RCBA_BA_MASK,
513 /* config:GEN_PMCON* */
515 ich9_lpc_pmcon_update(ICH9LPCState *lpc)
517 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
520 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
521 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
522 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
523 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
524 lpc->pm.smi_en_wmask &= ~1;
528 static int ich9_lpc_post_load(void *opaque, int version_id)
530 ICH9LPCState *lpc = opaque;
532 ich9_lpc_pmbase_sci_update(lpc);
533 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */);
534 ich9_lpc_pmcon_update(lpc);
538 static void ich9_lpc_config_write(PCIDevice *d,
539 uint32_t addr, uint32_t val, int len)
541 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
542 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
544 pci_default_write_config(d, addr, val, len);
545 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) ||
546 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) {
547 ich9_lpc_pmbase_sci_update(lpc);
549 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
550 ich9_lpc_rcba_update(lpc, rcba_old);
552 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
553 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
555 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
556 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
558 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
559 ich9_lpc_pmcon_update(lpc);
563 static void ich9_lpc_reset(DeviceState *qdev)
565 PCIDevice *d = PCI_DEVICE(qdev);
566 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
567 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
570 for (i = 0; i < 4; i++) {
571 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
572 ICH9_LPC_PIRQ_ROUT_DEFAULT);
574 for (i = 0; i < 4; i++) {
575 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
576 ICH9_LPC_PIRQ_ROUT_DEFAULT);
578 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
580 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
581 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
585 ich9_lpc_pmbase_sci_update(lpc);
586 ich9_lpc_rcba_update(lpc, rcba_old);
591 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le);
592 lpc->smi_features_ok = 0;
593 lpc->smi_negotiated_features = 0;
596 /* root complex register block is mapped into memory space */
597 static const MemoryRegionOps rcrb_mmio_ops = {
598 .read = ich9_cc_read,
599 .write = ich9_cc_write,
600 .endianness = DEVICE_LITTLE_ENDIAN,
603 static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
605 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
606 MemoryRegion *io_as = pci_address_space_io(&s->d);
609 pci_conf = s->d.config;
610 if (memory_region_present(io_as, 0x3f8)) {
612 pci_conf[0x82] |= 0x01;
614 if (memory_region_present(io_as, 0x2f8)) {
616 pci_conf[0x82] |= 0x02;
618 if (memory_region_present(io_as, 0x378)) {
620 pci_conf[0x82] |= 0x04;
622 if (memory_region_present(io_as, 0x3f2)) {
624 pci_conf[0x82] |= 0x08;
629 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
632 ICH9LPCState *lpc = opaque;
635 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
638 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
641 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len)
643 ICH9LPCState *lpc = opaque;
648 static const MemoryRegionOps ich9_rst_cnt_ops = {
649 .read = ich9_rst_cnt_read,
650 .write = ich9_rst_cnt_write,
651 .endianness = DEVICE_LITTLE_ENDIAN
654 static void ich9_lpc_initfn(Object *obj)
656 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
658 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
659 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
661 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT,
662 &lpc->sci_gsi, OBJ_PROP_FLAG_READ);
663 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
664 &acpi_enable_cmd, OBJ_PROP_FLAG_READ);
665 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
666 &acpi_disable_cmd, OBJ_PROP_FLAG_READ);
667 object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP,
668 &lpc->smi_negotiated_features,
671 ich9_pm_add_properties(obj, &lpc->pm);
674 static void ich9_lpc_realize(PCIDevice *d, Error **errp)
676 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
677 DeviceState *dev = DEVICE(d);
680 if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) &&
681 !(lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) {
683 * smi_features_ok_callback() throws an error on this.
685 * So bail out here instead of advertizing the invalid
686 * configuration and get obscure firmware failures from that.
688 error_setg(errp, "cpu hot-unplug requires cpu hot-plug");
692 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
698 pci_set_long(d->wmask + ICH9_LPC_PMBASE,
699 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
700 pci_set_byte(d->wmask + ICH9_LPC_PMBASE,
701 ICH9_LPC_ACPI_CTRL_ACPI_EN |
702 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK);
704 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
705 "lpc-rcrb-mmio", ICH9_CC_SIZE);
707 lpc->isa_bus = isa_bus;
710 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
712 lpc->machine_ready.notify = ich9_lpc_machine_ready;
713 qemu_add_machine_init_done_notifier(&lpc->machine_ready);
715 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
716 "lpc-reset-control", 1);
717 memory_region_add_subregion_overlap(pci_address_space_io(d),
718 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
721 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
723 isa_bus_irqs(isa_bus, lpc->gsi);
726 static bool ich9_rst_cnt_needed(void *opaque)
728 ICH9LPCState *lpc = opaque;
730 return (lpc->rst_cnt != 0);
733 static const VMStateDescription vmstate_ich9_rst_cnt = {
734 .name = "ICH9LPC/rst_cnt",
736 .minimum_version_id = 1,
737 .needed = ich9_rst_cnt_needed,
738 .fields = (VMStateField[]) {
739 VMSTATE_UINT8(rst_cnt, ICH9LPCState),
740 VMSTATE_END_OF_LIST()
744 static bool ich9_smi_feat_needed(void *opaque)
746 ICH9LPCState *lpc = opaque;
748 return !buffer_is_zero(lpc->smi_guest_features_le,
749 sizeof lpc->smi_guest_features_le) ||
750 lpc->smi_features_ok;
753 static const VMStateDescription vmstate_ich9_smi_feat = {
754 .name = "ICH9LPC/smi_feat",
756 .minimum_version_id = 1,
757 .needed = ich9_smi_feat_needed,
758 .fields = (VMStateField[]) {
759 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState,
761 VMSTATE_UINT8(smi_features_ok, ICH9LPCState),
762 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState),
763 VMSTATE_END_OF_LIST()
767 static const VMStateDescription vmstate_ich9_lpc = {
770 .minimum_version_id = 1,
771 .post_load = ich9_lpc_post_load,
772 .fields = (VMStateField[]) {
773 VMSTATE_PCI_DEVICE(d, ICH9LPCState),
774 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
775 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
776 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
777 VMSTATE_UINT32(sci_level, ICH9LPCState),
778 VMSTATE_END_OF_LIST()
780 .subsections = (const VMStateDescription*[]) {
781 &vmstate_ich9_rst_cnt,
782 &vmstate_ich9_smi_feat,
787 static Property ich9_lpc_properties[] = {
788 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true),
789 DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false),
790 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
791 ICH9_LPC_SMI_F_BROADCAST_BIT, true),
792 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features,
793 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true),
794 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features,
795 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, true),
796 DEFINE_PROP_END_OF_LIST(),
799 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
801 ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
803 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev);
806 static void ich9_lpc_class_init(ObjectClass *klass, void *data)
808 DeviceClass *dc = DEVICE_CLASS(klass);
809 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
810 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
811 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
813 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
814 dc->reset = ich9_lpc_reset;
815 k->realize = ich9_lpc_realize;
816 dc->vmsd = &vmstate_ich9_lpc;
817 device_class_set_props(dc, ich9_lpc_properties);
818 k->config_write = ich9_lpc_config_write;
819 dc->desc = "ICH9 LPC bridge";
820 k->vendor_id = PCI_VENDOR_ID_INTEL;
821 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
822 k->revision = ICH9_A2_LPC_REVISION;
823 k->class_id = PCI_CLASS_BRIDGE_ISA;
825 * Reason: part of ICH9 southbridge, needs to be wired up by
828 dc->user_creatable = false;
829 hc->pre_plug = ich9_pm_device_pre_plug_cb;
830 hc->plug = ich9_pm_device_plug_cb;
831 hc->unplug_request = ich9_pm_device_unplug_request_cb;
832 hc->unplug = ich9_pm_device_unplug_cb;
833 adevc->ospm_status = ich9_pm_ospm_status;
834 adevc->send_event = ich9_send_gpe;
835 adevc->madt_cpu = pc_madt_cpu_entry;
838 static const TypeInfo ich9_lpc_info = {
839 .name = TYPE_ICH9_LPC_DEVICE,
840 .parent = TYPE_PCI_DEVICE,
841 .instance_size = sizeof(ICH9LPCState),
842 .instance_init = ich9_lpc_initfn,
843 .class_init = ich9_lpc_class_init,
844 .interfaces = (InterfaceInfo[]) {
845 { TYPE_HOTPLUG_HANDLER },
846 { TYPE_ACPI_DEVICE_IF },
847 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
852 static void ich9_lpc_register(void)
854 type_register_static(&ich9_lpc_info);
857 type_init(ich9_lpc_register);