2 * VT82C686B south bridge support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
13 #include "qemu/osdep.h"
14 #include "hw/isa/vt82c686.h"
15 #include "hw/i2c/i2c.h"
16 #include "hw/pci/pci.h"
17 #include "hw/qdev-properties.h"
18 #include "hw/isa/isa.h"
19 #include "hw/isa/superio.h"
20 #include "hw/sysbus.h"
21 #include "migration/vmstate.h"
22 #include "hw/mips/mips.h"
23 #include "hw/isa/apm.h"
24 #include "hw/acpi/acpi.h"
25 #include "hw/i2c/pm_smbus.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "qemu/timer.h"
29 #include "exec/address-spaces.h"
30 #include "qom/object.h"
32 /* #define DEBUG_VT82C686B */
34 #ifdef DEBUG_VT82C686B
35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
37 #define DPRINTF(fmt, ...)
40 typedef struct SuperIOConfig {
41 uint8_t config[0x100];
46 struct VT82C686BISAState {
49 SuperIOConfig superio_conf;
52 #define TYPE_VT82C686B_ISA "vt82c686b-isa"
53 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
55 static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
58 SuperIOConfig *superio_conf = opaque;
60 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
62 superio_conf->index = data & 0xff;
64 bool can_write = true;
66 switch (superio_conf->index) {
79 if ((data & 0xff) != 0xfe) {
80 DPRINTF("change uart 1 base. unsupported yet\n");
85 if ((data & 0xff) != 0xbe) {
86 DPRINTF("change uart 2 base. unsupported yet\n");
95 superio_conf->config[superio_conf->index] = data & 0xff;
100 static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
102 SuperIOConfig *superio_conf = opaque;
104 DPRINTF("superio_ioport_readb address 0x%x\n", addr);
105 return superio_conf->config[superio_conf->index];
108 static const MemoryRegionOps superio_ops = {
109 .read = superio_ioport_readb,
110 .write = superio_ioport_writeb,
111 .endianness = DEVICE_NATIVE_ENDIAN,
113 .min_access_size = 1,
114 .max_access_size = 1,
118 static void vt82c686b_isa_reset(DeviceState *dev)
120 VT82C686BISAState *vt82c = VT82C686B_ISA(dev);
121 uint8_t *pci_conf = vt82c->dev.config;
123 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
124 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
125 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
126 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
128 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
129 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
130 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
131 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
132 pci_conf[0x59] = 0x04;
133 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
134 pci_conf[0x5f] = 0x04;
135 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
137 vt82c->superio_conf.config[0xe0] = 0x3c;
138 vt82c->superio_conf.config[0xe2] = 0x03;
139 vt82c->superio_conf.config[0xe3] = 0xfc;
140 vt82c->superio_conf.config[0xe6] = 0xde;
141 vt82c->superio_conf.config[0xe7] = 0xfe;
142 vt82c->superio_conf.config[0xe8] = 0xbe;
145 /* write config pci function0 registers. PCI-ISA bridge */
146 static void vt82c686b_write_config(PCIDevice *d, uint32_t address,
147 uint32_t val, int len)
149 VT82C686BISAState *vt686 = VT82C686B_ISA(d);
151 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
154 pci_default_write_config(d, address, val, len);
155 if (address == 0x85) { /* enable or disable super IO configure */
156 memory_region_set_enabled(&vt686->superio, val & 0x2);
160 #define ACPI_DBG_IO_ADDR 0xb044
162 struct VT686PMState {
168 uint32_t smb_io_base;
171 struct VIAAC97State {
175 struct VIAMC97State {
179 #define TYPE_VT82C686B_PM "VT82C686B_PM"
180 OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM)
182 static void pm_update_sci(VT686PMState *s)
184 int sci_level, pmsts;
186 pmsts = acpi_pm1_evt_get_sts(&s->ar);
187 sci_level = (((pmsts & s->ar.pm1.evt.en) &
188 (ACPI_BITMASK_RT_CLOCK_ENABLE |
189 ACPI_BITMASK_POWER_BUTTON_ENABLE |
190 ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
191 ACPI_BITMASK_TIMER_ENABLE)) != 0);
192 pci_set_irq(&s->dev, sci_level);
193 /* schedule a timer interruption if needed */
194 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
195 !(pmsts & ACPI_BITMASK_TIMER_STATUS));
198 static void pm_tmr_timer(ACPIREGS *ar)
200 VT686PMState *s = container_of(ar, VT686PMState, ar);
204 static void pm_io_space_update(VT686PMState *s)
208 pm_io_base = pci_get_long(s->dev.config + 0x40);
209 pm_io_base &= 0xffc0;
211 memory_region_transaction_begin();
212 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
213 memory_region_set_address(&s->io, pm_io_base);
214 memory_region_transaction_commit();
217 static void pm_write_config(PCIDevice *d,
218 uint32_t address, uint32_t val, int len)
220 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
222 pci_default_write_config(d, address, val, len);
225 static int vmstate_acpi_post_load(void *opaque, int version_id)
227 VT686PMState *s = opaque;
229 pm_io_space_update(s);
233 static const VMStateDescription vmstate_acpi = {
234 .name = "vt82c686b_pm",
236 .minimum_version_id = 1,
237 .post_load = vmstate_acpi_post_load,
238 .fields = (VMStateField[]) {
239 VMSTATE_PCI_DEVICE(dev, VT686PMState),
240 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
241 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
242 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
243 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
244 VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
245 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
246 VMSTATE_END_OF_LIST()
251 * TODO: VIA_AC97 and VIA_MC97
252 * just register a PCI device now, functionalities will be implemented later.
255 OBJECT_DECLARE_SIMPLE_TYPE(VIAMC97State, VIA_MC97)
256 OBJECT_DECLARE_SIMPLE_TYPE(VIAAC97State, VIA_AC97)
258 static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp)
260 VIAAC97State *s = VIA_AC97(dev);
261 uint8_t *pci_conf = s->dev.config;
263 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
265 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
266 PCI_STATUS_DEVSEL_MEDIUM);
267 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
270 static void via_ac97_class_init(ObjectClass *klass, void *data)
272 DeviceClass *dc = DEVICE_CLASS(klass);
273 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
275 k->realize = vt82c686b_ac97_realize;
276 k->vendor_id = PCI_VENDOR_ID_VIA;
277 k->device_id = PCI_DEVICE_ID_VIA_AC97;
279 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
280 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
284 static const TypeInfo via_ac97_info = {
285 .name = TYPE_VIA_AC97,
286 .parent = TYPE_PCI_DEVICE,
287 .instance_size = sizeof(VIAAC97State),
288 .class_init = via_ac97_class_init,
289 .interfaces = (InterfaceInfo[]) {
290 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
295 static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp)
297 VIAMC97State *s = VIA_MC97(dev);
298 uint8_t *pci_conf = s->dev.config;
300 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
301 PCI_COMMAND_VGA_PALETTE);
302 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
303 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
306 static void via_mc97_class_init(ObjectClass *klass, void *data)
308 DeviceClass *dc = DEVICE_CLASS(klass);
309 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
311 k->realize = vt82c686b_mc97_realize;
312 k->vendor_id = PCI_VENDOR_ID_VIA;
313 k->device_id = PCI_DEVICE_ID_VIA_MC97;
314 k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
316 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
320 static const TypeInfo via_mc97_info = {
321 .name = TYPE_VIA_MC97,
322 .parent = TYPE_PCI_DEVICE,
323 .instance_size = sizeof(VIAMC97State),
324 .class_init = via_mc97_class_init,
325 .interfaces = (InterfaceInfo[]) {
326 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
331 /* vt82c686 pm init */
332 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
334 VT686PMState *s = VT82C686B_PM(dev);
337 pci_conf = s->dev.config;
338 pci_set_word(pci_conf + PCI_COMMAND, 0);
339 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
340 PCI_STATUS_DEVSEL_MEDIUM);
342 /* 0x48-0x4B is Power Management I/O Base */
343 pci_set_long(pci_conf + 0x48, 0x00000001);
345 /* SMB ports:0xeee0~0xeeef */
346 s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0);
347 pci_conf[0x90] = s->smb_io_base | 1;
348 pci_conf[0x91] = s->smb_io_base >> 8;
349 pci_conf[0xd2] = 0x90;
350 pm_smbus_init(DEVICE(s), &s->smb, false);
351 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
353 apm_init(dev, &s->apm, NULL, s);
355 memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
356 memory_region_set_enabled(&s->io, false);
357 memory_region_add_subregion(get_system_io(), 0, &s->io);
359 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
360 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
361 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
364 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
370 dev = pci_new(devfn, TYPE_VT82C686B_PM);
371 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
373 s = VT82C686B_PM(dev);
375 pci_realize_and_unref(dev, bus, &error_fatal);
380 static Property via_pm_properties[] = {
381 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
382 DEFINE_PROP_END_OF_LIST(),
385 static void via_pm_class_init(ObjectClass *klass, void *data)
387 DeviceClass *dc = DEVICE_CLASS(klass);
388 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
390 k->realize = vt82c686b_pm_realize;
391 k->config_write = pm_write_config;
392 k->vendor_id = PCI_VENDOR_ID_VIA;
393 k->device_id = PCI_DEVICE_ID_VIA_ACPI;
394 k->class_id = PCI_CLASS_BRIDGE_OTHER;
397 dc->vmsd = &vmstate_acpi;
398 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
399 device_class_set_props(dc, via_pm_properties);
402 static const TypeInfo via_pm_info = {
403 .name = TYPE_VT82C686B_PM,
404 .parent = TYPE_PCI_DEVICE,
405 .instance_size = sizeof(VT686PMState),
406 .class_init = via_pm_class_init,
407 .interfaces = (InterfaceInfo[]) {
408 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
413 static const VMStateDescription vmstate_via = {
416 .minimum_version_id = 1,
417 .fields = (VMStateField[]) {
418 VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
419 VMSTATE_END_OF_LIST()
423 /* init the PCI-to-ISA bridge */
424 static void vt82c686b_realize(PCIDevice *d, Error **errp)
426 VT82C686BISAState *vt82c = VT82C686B_ISA(d);
432 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
433 pci_address_space_io(d), errp);
438 pci_conf = d->config;
439 pci_config_set_prog_interface(pci_conf, 0x0);
442 for (i = 0x00; i < 0xff; i++) {
443 if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
448 memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops,
449 &vt82c->superio_conf, "superio", 2);
450 memory_region_set_enabled(&vt82c->superio, false);
452 * The floppy also uses 0x3f0 and 0x3f1.
453 * But we do not emulate a floppy, so just set it here.
455 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
459 ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn)
463 d = pci_create_simple_multifunction(bus, devfn, true, TYPE_VT82C686B_ISA);
464 return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
467 static void via_class_init(ObjectClass *klass, void *data)
469 DeviceClass *dc = DEVICE_CLASS(klass);
470 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
472 k->realize = vt82c686b_realize;
473 k->config_write = vt82c686b_write_config;
474 k->vendor_id = PCI_VENDOR_ID_VIA;
475 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
476 k->class_id = PCI_CLASS_BRIDGE_ISA;
478 dc->reset = vt82c686b_isa_reset;
479 dc->desc = "ISA bridge";
480 dc->vmsd = &vmstate_via;
482 * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
483 * e.g. by mips_fuloong2e_init()
485 dc->user_creatable = false;
488 static const TypeInfo via_info = {
489 .name = TYPE_VT82C686B_ISA,
490 .parent = TYPE_PCI_DEVICE,
491 .instance_size = sizeof(VT82C686BISAState),
492 .class_init = via_class_init,
493 .interfaces = (InterfaceInfo[]) {
494 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
499 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
501 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
503 sc->serial.count = 2;
504 sc->parallel.count = 1;
506 sc->floppy.count = 1;
509 static const TypeInfo via_superio_info = {
510 .name = TYPE_VT82C686B_SUPERIO,
511 .parent = TYPE_ISA_SUPERIO,
512 .instance_size = sizeof(ISASuperIODevice),
513 .class_size = sizeof(ISASuperIOClass),
514 .class_init = vt82c686b_superio_class_init,
517 static void vt82c686b_register_types(void)
519 type_register_static(&via_ac97_info);
520 type_register_static(&via_mc97_info);
521 type_register_static(&via_pm_info);
522 type_register_static(&via_superio_info);
523 type_register_static(&via_info);
526 type_init(vt82c686b_register_types)