2 * VT82C686B south bridge support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
13 #include "qemu/osdep.h"
14 #include "hw/isa/vt82c686.h"
15 #include "hw/pci/pci.h"
16 #include "hw/qdev-properties.h"
17 #include "hw/isa/isa.h"
18 #include "hw/isa/superio.h"
19 #include "migration/vmstate.h"
20 #include "hw/isa/apm.h"
21 #include "hw/acpi/acpi.h"
22 #include "hw/i2c/pm_smbus.h"
23 #include "qapi/error.h"
24 #include "qemu/module.h"
25 #include "qemu/range.h"
26 #include "qemu/timer.h"
27 #include "exec/address-spaces.h"
30 OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM)
40 static void pm_io_space_update(VT686PMState *s)
44 pm_io_base = pci_get_long(s->dev.config + 0x40);
47 memory_region_transaction_begin();
48 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
49 memory_region_set_address(&s->io, pm_io_base);
50 memory_region_transaction_commit();
53 static void smb_io_space_update(VT686PMState *s)
55 uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL;
57 memory_region_transaction_begin();
58 memory_region_set_address(&s->smb.io, smbase);
59 memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0));
60 memory_region_transaction_commit();
63 static int vmstate_acpi_post_load(void *opaque, int version_id)
65 VT686PMState *s = opaque;
67 pm_io_space_update(s);
68 smb_io_space_update(s);
72 static const VMStateDescription vmstate_acpi = {
73 .name = "vt82c686b_pm",
75 .minimum_version_id = 1,
76 .post_load = vmstate_acpi_post_load,
77 .fields = (VMStateField[]) {
78 VMSTATE_PCI_DEVICE(dev, VT686PMState),
79 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
80 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
81 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
82 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
83 VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
84 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
89 static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
91 VT686PMState *s = VT82C686B_PM(d);
93 trace_via_pm_write(addr, val, len);
94 pci_default_write_config(d, addr, val, len);
95 if (ranges_overlap(addr, len, 0x90, 4)) {
96 uint32_t v = pci_get_long(s->dev.config + 0x90);
97 pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1);
99 if (range_covers_byte(addr, len, 0xd2)) {
100 s->dev.config[0xd2] &= 0xf;
101 smb_io_space_update(s);
105 static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size)
107 trace_via_pm_io_write(addr, data, size);
110 static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size)
112 trace_via_pm_io_read(addr, 0, size);
116 static const MemoryRegionOps pm_io_ops = {
118 .write = pm_io_write,
119 .endianness = DEVICE_NATIVE_ENDIAN,
121 .min_access_size = 1,
122 .max_access_size = 1,
126 static void pm_update_sci(VT686PMState *s)
128 int sci_level, pmsts;
130 pmsts = acpi_pm1_evt_get_sts(&s->ar);
131 sci_level = (((pmsts & s->ar.pm1.evt.en) &
132 (ACPI_BITMASK_RT_CLOCK_ENABLE |
133 ACPI_BITMASK_POWER_BUTTON_ENABLE |
134 ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
135 ACPI_BITMASK_TIMER_ENABLE)) != 0);
136 pci_set_irq(&s->dev, sci_level);
137 /* schedule a timer interruption if needed */
138 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
139 !(pmsts & ACPI_BITMASK_TIMER_STATUS));
142 static void pm_tmr_timer(ACPIREGS *ar)
144 VT686PMState *s = container_of(ar, VT686PMState, ar);
148 static void vt82c686b_pm_reset(DeviceState *d)
150 VT686PMState *s = VT82C686B_PM(d);
153 pci_set_long(s->dev.config + 0x90, 1);
154 s->dev.config[0xd2] = 0;
156 smb_io_space_update(s);
159 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
161 VT686PMState *s = VT82C686B_PM(dev);
164 pci_conf = s->dev.config;
165 pci_set_word(pci_conf + PCI_COMMAND, 0);
166 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
167 PCI_STATUS_DEVSEL_MEDIUM);
169 /* 0x48-0x4B is Power Management I/O Base */
170 pci_set_long(pci_conf + 0x48, 0x00000001);
172 pm_smbus_init(DEVICE(s), &s->smb, false);
173 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io);
174 memory_region_set_enabled(&s->smb.io, false);
176 apm_init(dev, &s->apm, NULL, s);
178 memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s,
180 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io);
181 memory_region_set_enabled(&s->io, false);
183 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
184 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
185 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
188 static void via_pm_class_init(ObjectClass *klass, void *data)
190 DeviceClass *dc = DEVICE_CLASS(klass);
191 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
193 k->realize = vt82c686b_pm_realize;
194 k->config_write = pm_write_config;
195 k->vendor_id = PCI_VENDOR_ID_VIA;
196 k->device_id = PCI_DEVICE_ID_VIA_ACPI;
197 k->class_id = PCI_CLASS_BRIDGE_OTHER;
199 dc->reset = vt82c686b_pm_reset;
201 dc->vmsd = &vmstate_acpi;
202 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
205 static const TypeInfo via_pm_info = {
206 .name = TYPE_VT82C686B_PM,
207 .parent = TYPE_PCI_DEVICE,
208 .instance_size = sizeof(VT686PMState),
209 .class_init = via_pm_class_init,
210 .interfaces = (InterfaceInfo[]) {
211 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
217 typedef struct SuperIOConfig {
223 static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
226 SuperIOConfig *sc = opaque;
228 if (addr == 0x3f0) { /* config index register */
229 sc->index = data & 0xff;
231 bool can_write = true;
232 /* 0x3f1, config data register */
233 trace_via_superio_write(sc->index, data & 0xff);
246 /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
252 sc->regs[sc->index] = data & 0xff;
257 static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
259 SuperIOConfig *sc = opaque;
260 uint8_t val = sc->regs[sc->index];
262 trace_via_superio_read(sc->index, val);
266 static const MemoryRegionOps superio_cfg_ops = {
267 .read = superio_cfg_read,
268 .write = superio_cfg_write,
269 .endianness = DEVICE_NATIVE_ENDIAN,
271 .min_access_size = 1,
272 .max_access_size = 1,
277 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
279 struct VT82C686BISAState {
281 SuperIOConfig superio_cfg;
284 static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
285 uint32_t val, int len)
287 VT82C686BISAState *s = VT82C686B_ISA(d);
289 trace_via_isa_write(addr, val, len);
290 pci_default_write_config(d, addr, val, len);
292 /* BIT(1): enable or disable superio config io ports */
293 memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
297 static const VMStateDescription vmstate_via = {
300 .minimum_version_id = 1,
301 .fields = (VMStateField[]) {
302 VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
303 VMSTATE_END_OF_LIST()
307 static void vt82c686b_isa_reset(DeviceState *dev)
309 VT82C686BISAState *s = VT82C686B_ISA(dev);
310 uint8_t *pci_conf = s->dev.config;
312 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
313 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
314 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
315 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
317 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
318 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
319 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
320 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
321 pci_conf[0x59] = 0x04;
322 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
323 pci_conf[0x5f] = 0x04;
324 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
326 s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
327 s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
328 s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
329 s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
330 s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
331 s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
334 static void vt82c686b_realize(PCIDevice *d, Error **errp)
336 VT82C686BISAState *s = VT82C686B_ISA(d);
342 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
343 pci_address_space_io(d), errp);
348 pci_conf = d->config;
349 pci_config_set_prog_interface(pci_conf, 0x0);
352 for (i = 0x00; i < 0xff; i++) {
353 if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
358 memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
359 &s->superio_cfg, "superio_cfg", 2);
360 memory_region_set_enabled(&s->superio_cfg.io, false);
362 * The floppy also uses 0x3f0 and 0x3f1.
363 * But we do not emulate a floppy, so just set it here.
365 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
369 static void via_class_init(ObjectClass *klass, void *data)
371 DeviceClass *dc = DEVICE_CLASS(klass);
372 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
374 k->realize = vt82c686b_realize;
375 k->config_write = vt82c686b_write_config;
376 k->vendor_id = PCI_VENDOR_ID_VIA;
377 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
378 k->class_id = PCI_CLASS_BRIDGE_ISA;
380 dc->reset = vt82c686b_isa_reset;
381 dc->desc = "ISA bridge";
382 dc->vmsd = &vmstate_via;
384 * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
385 * e.g. by mips_fuloong2e_init()
387 dc->user_creatable = false;
390 static const TypeInfo via_info = {
391 .name = TYPE_VT82C686B_ISA,
392 .parent = TYPE_PCI_DEVICE,
393 .instance_size = sizeof(VT82C686BISAState),
394 .class_init = via_class_init,
395 .interfaces = (InterfaceInfo[]) {
396 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
402 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
404 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
406 sc->serial.count = 2;
407 sc->parallel.count = 1;
409 sc->floppy.count = 1;
412 static const TypeInfo via_superio_info = {
413 .name = TYPE_VT82C686B_SUPERIO,
414 .parent = TYPE_ISA_SUPERIO,
415 .instance_size = sizeof(ISASuperIODevice),
416 .class_size = sizeof(ISASuperIOClass),
417 .class_init = vt82c686b_superio_class_init,
421 static void vt82c686b_register_types(void)
423 type_register_static(&via_pm_info);
424 type_register_static(&via_info);
425 type_register_static(&via_superio_info);
428 type_init(vt82c686b_register_types)