2 * VT82C686B south bridge support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
13 #include "qemu/osdep.h"
14 #include "hw/isa/vt82c686.h"
15 #include "hw/pci/pci.h"
16 #include "hw/qdev-properties.h"
17 #include "hw/isa/isa.h"
18 #include "hw/isa/superio.h"
19 #include "migration/vmstate.h"
20 #include "hw/isa/apm.h"
21 #include "hw/acpi/acpi.h"
22 #include "hw/i2c/pm_smbus.h"
23 #include "qapi/error.h"
24 #include "qemu/module.h"
25 #include "qemu/range.h"
26 #include "qemu/timer.h"
27 #include "exec/address-spaces.h"
30 #define TYPE_VIA_PM "via-pm"
31 OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM)
41 static void pm_io_space_update(ViaPMState *s)
43 uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL;
45 memory_region_transaction_begin();
46 memory_region_set_address(&s->io, pmbase);
47 memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7));
48 memory_region_transaction_commit();
51 static void smb_io_space_update(ViaPMState *s)
53 uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL;
55 memory_region_transaction_begin();
56 memory_region_set_address(&s->smb.io, smbase);
57 memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0));
58 memory_region_transaction_commit();
61 static int vmstate_acpi_post_load(void *opaque, int version_id)
63 ViaPMState *s = opaque;
65 pm_io_space_update(s);
66 smb_io_space_update(s);
70 static const VMStateDescription vmstate_acpi = {
71 .name = "vt82c686b_pm",
73 .minimum_version_id = 1,
74 .post_load = vmstate_acpi_post_load,
75 .fields = (VMStateField[]) {
76 VMSTATE_PCI_DEVICE(dev, ViaPMState),
77 VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState),
78 VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState),
79 VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState),
80 VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState),
81 VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState),
82 VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState),
87 static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
89 ViaPMState *s = VIA_PM(d);
91 trace_via_pm_write(addr, val, len);
92 pci_default_write_config(d, addr, val, len);
93 if (ranges_overlap(addr, len, 0x48, 4)) {
94 uint32_t v = pci_get_long(s->dev.config + 0x48);
95 pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1);
97 if (range_covers_byte(addr, len, 0x41)) {
98 pm_io_space_update(s);
100 if (ranges_overlap(addr, len, 0x90, 4)) {
101 uint32_t v = pci_get_long(s->dev.config + 0x90);
102 pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1);
104 if (range_covers_byte(addr, len, 0xd2)) {
105 s->dev.config[0xd2] &= 0xf;
106 smb_io_space_update(s);
110 static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size)
112 trace_via_pm_io_write(addr, data, size);
115 static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size)
117 trace_via_pm_io_read(addr, 0, size);
121 static const MemoryRegionOps pm_io_ops = {
123 .write = pm_io_write,
124 .endianness = DEVICE_NATIVE_ENDIAN,
126 .min_access_size = 1,
127 .max_access_size = 1,
131 static void pm_update_sci(ViaPMState *s)
133 int sci_level, pmsts;
135 pmsts = acpi_pm1_evt_get_sts(&s->ar);
136 sci_level = (((pmsts & s->ar.pm1.evt.en) &
137 (ACPI_BITMASK_RT_CLOCK_ENABLE |
138 ACPI_BITMASK_POWER_BUTTON_ENABLE |
139 ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
140 ACPI_BITMASK_TIMER_ENABLE)) != 0);
141 pci_set_irq(&s->dev, sci_level);
142 /* schedule a timer interruption if needed */
143 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
144 !(pmsts & ACPI_BITMASK_TIMER_STATUS));
147 static void pm_tmr_timer(ACPIREGS *ar)
149 ViaPMState *s = container_of(ar, ViaPMState, ar);
153 static void via_pm_reset(DeviceState *d)
155 ViaPMState *s = VIA_PM(d);
157 memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0,
158 PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE);
159 /* Power Management IO base */
160 pci_set_long(s->dev.config + 0x48, 1);
162 pci_set_long(s->dev.config + 0x90, 1);
164 pm_io_space_update(s);
165 smb_io_space_update(s);
168 static void via_pm_realize(PCIDevice *dev, Error **errp)
170 ViaPMState *s = VIA_PM(dev);
172 pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK |
173 PCI_STATUS_DEVSEL_MEDIUM);
175 pm_smbus_init(DEVICE(s), &s->smb, false);
176 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io);
177 memory_region_set_enabled(&s->smb.io, false);
179 apm_init(dev, &s->apm, NULL, s);
181 memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128);
182 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io);
183 memory_region_set_enabled(&s->io, false);
185 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
186 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
187 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
190 typedef struct via_pm_init_info {
194 static void via_pm_class_init(ObjectClass *klass, void *data)
196 DeviceClass *dc = DEVICE_CLASS(klass);
197 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
198 ViaPMInitInfo *info = data;
200 k->realize = via_pm_realize;
201 k->config_write = pm_write_config;
202 k->vendor_id = PCI_VENDOR_ID_VIA;
203 k->device_id = info->device_id;
204 k->class_id = PCI_CLASS_BRIDGE_OTHER;
206 dc->reset = via_pm_reset;
207 /* Reason: part of VIA south bridge, does not exist stand alone */
208 dc->user_creatable = false;
209 dc->vmsd = &vmstate_acpi;
212 static const TypeInfo via_pm_info = {
214 .parent = TYPE_PCI_DEVICE,
215 .instance_size = sizeof(ViaPMState),
217 .interfaces = (InterfaceInfo[]) {
218 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
223 static const ViaPMInitInfo vt82c686b_pm_init_info = {
224 .device_id = PCI_DEVICE_ID_VIA_82C686B_PM,
227 static const TypeInfo vt82c686b_pm_info = {
228 .name = TYPE_VT82C686B_PM,
229 .parent = TYPE_VIA_PM,
230 .class_init = via_pm_class_init,
231 .class_data = (void *)&vt82c686b_pm_init_info,
234 static const ViaPMInitInfo vt8231_pm_init_info = {
235 .device_id = PCI_DEVICE_ID_VIA_8231_PM,
238 static const TypeInfo vt8231_pm_info = {
239 .name = TYPE_VT8231_PM,
240 .parent = TYPE_VIA_PM,
241 .class_init = via_pm_class_init,
242 .class_data = (void *)&vt8231_pm_init_info,
246 typedef struct SuperIOConfig {
252 static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
255 SuperIOConfig *sc = opaque;
257 if (addr == 0x3f0) { /* config index register */
258 sc->index = data & 0xff;
260 bool can_write = true;
261 /* 0x3f1, config data register */
262 trace_via_superio_write(sc->index, data & 0xff);
275 /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
281 sc->regs[sc->index] = data & 0xff;
286 static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
288 SuperIOConfig *sc = opaque;
289 uint8_t val = sc->regs[sc->index];
291 trace_via_superio_read(sc->index, val);
295 static const MemoryRegionOps superio_cfg_ops = {
296 .read = superio_cfg_read,
297 .write = superio_cfg_write,
298 .endianness = DEVICE_NATIVE_ENDIAN,
300 .min_access_size = 1,
301 .max_access_size = 1,
306 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
308 struct VT82C686BISAState {
310 SuperIOConfig superio_cfg;
313 static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
314 uint32_t val, int len)
316 VT82C686BISAState *s = VT82C686B_ISA(d);
318 trace_via_isa_write(addr, val, len);
319 pci_default_write_config(d, addr, val, len);
321 /* BIT(1): enable or disable superio config io ports */
322 memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
326 static const VMStateDescription vmstate_via = {
329 .minimum_version_id = 1,
330 .fields = (VMStateField[]) {
331 VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
332 VMSTATE_END_OF_LIST()
336 static void vt82c686b_isa_reset(DeviceState *dev)
338 VT82C686BISAState *s = VT82C686B_ISA(dev);
339 uint8_t *pci_conf = s->dev.config;
341 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
342 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
343 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
344 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
346 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
347 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
348 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
349 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
350 pci_conf[0x59] = 0x04;
351 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
352 pci_conf[0x5f] = 0x04;
353 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
355 s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
356 s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
357 s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
358 s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
359 s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
360 s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
363 static void vt82c686b_realize(PCIDevice *d, Error **errp)
365 VT82C686BISAState *s = VT82C686B_ISA(d);
366 DeviceState *dev = DEVICE(d);
370 isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d),
373 for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
374 if (i < PCI_COMMAND || i >= PCI_REVISION_ID) {
379 memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
380 &s->superio_cfg, "superio_cfg", 2);
381 memory_region_set_enabled(&s->superio_cfg.io, false);
383 * The floppy also uses 0x3f0 and 0x3f1.
384 * But we do not emulate a floppy, so just set it here.
386 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
390 static void via_class_init(ObjectClass *klass, void *data)
392 DeviceClass *dc = DEVICE_CLASS(klass);
393 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
395 k->realize = vt82c686b_realize;
396 k->config_write = vt82c686b_write_config;
397 k->vendor_id = PCI_VENDOR_ID_VIA;
398 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
399 k->class_id = PCI_CLASS_BRIDGE_ISA;
401 dc->reset = vt82c686b_isa_reset;
402 dc->desc = "ISA bridge";
403 dc->vmsd = &vmstate_via;
405 * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
406 * e.g. by mips_fuloong2e_init()
408 dc->user_creatable = false;
411 static const TypeInfo via_info = {
412 .name = TYPE_VT82C686B_ISA,
413 .parent = TYPE_PCI_DEVICE,
414 .instance_size = sizeof(VT82C686BISAState),
415 .class_init = via_class_init,
416 .interfaces = (InterfaceInfo[]) {
417 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
423 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
425 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
427 sc->serial.count = 2;
428 sc->parallel.count = 1;
430 sc->floppy.count = 1;
433 static const TypeInfo via_superio_info = {
434 .name = TYPE_VT82C686B_SUPERIO,
435 .parent = TYPE_ISA_SUPERIO,
436 .instance_size = sizeof(ISASuperIODevice),
437 .class_size = sizeof(ISASuperIOClass),
438 .class_init = vt82c686b_superio_class_init,
442 static void vt82c686b_register_types(void)
444 type_register_static(&via_pm_info);
445 type_register_static(&vt82c686b_pm_info);
446 type_register_static(&vt8231_pm_info);
447 type_register_static(&via_info);
448 type_register_static(&via_superio_info);
451 type_init(vt82c686b_register_types)