2 * Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
9 #include "qemu/osdep.h"
10 #include "qemu/error-report.h"
13 #include "hw/boards.h"
15 #include "hw/m68k/mcf.h"
16 #include "qemu/timer.h"
17 #include "hw/ptimer.h"
18 #include "sysemu/sysemu.h"
19 #include "hw/sysbus.h"
21 /* General purpose timer module. */
42 static void m5206_timer_update(m5206_timer_state *s)
44 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF))
45 qemu_irq_raise(s->irq);
47 qemu_irq_lower(s->irq);
50 static void m5206_timer_reset(m5206_timer_state *s)
56 static void m5206_timer_recalibrate(m5206_timer_state *s)
61 ptimer_transaction_begin(s->timer);
62 ptimer_stop(s->timer);
64 if ((s->tmr & TMR_RST) == 0) {
68 prescale = (s->tmr >> 8) + 1;
69 mode = (s->tmr >> 1) & 3;
73 if (mode == 3 || mode == 0) {
74 qemu_log_mask(LOG_UNIMP, "m5206_timer: mode %d not implemented\n",
78 if ((s->tmr & TMR_FRR) == 0) {
79 qemu_log_mask(LOG_UNIMP,
80 "m5206_timer: free running mode not implemented\n");
84 /* Assume 66MHz system clock. */
85 ptimer_set_freq(s->timer, 66000000 / prescale);
87 ptimer_set_limit(s->timer, s->trr, 0);
89 ptimer_run(s->timer, 0);
91 ptimer_transaction_commit(s->timer);
94 static void m5206_timer_trigger(void *opaque)
96 m5206_timer_state *s = (m5206_timer_state *)opaque;
98 m5206_timer_update(s);
101 static uint32_t m5206_timer_read(m5206_timer_state *s, uint32_t addr)
111 return s->trr - ptimer_get_count(s->timer);
119 static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val)
123 if ((s->tmr & TMR_RST) != 0 && (val & TMR_RST) == 0) {
124 m5206_timer_reset(s);
127 m5206_timer_recalibrate(s);
131 m5206_timer_recalibrate(s);
137 ptimer_transaction_begin(s->timer);
138 ptimer_set_count(s->timer, val);
139 ptimer_transaction_commit(s->timer);
147 m5206_timer_update(s);
150 static m5206_timer_state *m5206_timer_init(qemu_irq irq)
152 m5206_timer_state *s;
154 s = g_new0(m5206_timer_state, 1);
155 s->timer = ptimer_init(m5206_timer_trigger, s, PTIMER_POLICY_LEGACY);
157 m5206_timer_reset(s);
161 /* System Integration Module. */
164 SysBusDevice parent_obj;
169 m5206_timer_state *timer[2];
173 uint16_t imr; /* 1 == interrupt is masked. */
178 /* Include the UART vector registers here. */
182 #define MCF5206_MBAR(obj) OBJECT_CHECK(m5206_mbar_state, (obj), TYPE_MCF5206_MBAR)
184 /* Interrupt controller. */
186 static int m5206_find_pending_irq(m5206_mbar_state *s)
195 active = s->ipr & ~s->imr;
199 for (i = 1; i < 14; i++) {
200 if (active & (1 << i)) {
201 if ((s->icr[i] & 0x1f) > level) {
202 level = s->icr[i] & 0x1f;
214 static void m5206_mbar_update(m5206_mbar_state *s)
220 irq = m5206_find_pending_irq(s);
224 level = (tmp >> 2) & 7;
240 /* Unknown vector. */
241 qemu_log_mask(LOG_UNIMP, "%s: Unhandled vector for IRQ %d\n",
251 m68k_set_irq_level(s->cpu, level, vector);
254 static void m5206_mbar_set_irq(void *opaque, int irq, int level)
256 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
260 s->ipr &= ~(1 << irq);
262 m5206_mbar_update(s);
265 /* System Integration Module. */
267 static void m5206_mbar_reset(DeviceState *dev)
269 m5206_mbar_state *s = MCF5206_MBAR(dev);
291 static uint64_t m5206_mbar_read(m5206_mbar_state *s,
292 uint16_t offset, unsigned size)
294 if (offset >= 0x100 && offset < 0x120) {
295 return m5206_timer_read(s->timer[0], offset - 0x100);
296 } else if (offset >= 0x120 && offset < 0x140) {
297 return m5206_timer_read(s->timer[1], offset - 0x120);
298 } else if (offset >= 0x140 && offset < 0x160) {
299 return mcf_uart_read(s->uart[0], offset - 0x140, size);
300 } else if (offset >= 0x180 && offset < 0x1a0) {
301 return mcf_uart_read(s->uart[1], offset - 0x180, size);
304 case 0x03: return s->scr;
305 case 0x14 ... 0x20: return s->icr[offset - 0x13];
306 case 0x36: return s->imr;
307 case 0x3a: return s->ipr;
308 case 0x40: return s->rsr;
310 case 0x42: return s->swivr;
312 /* DRAM mask register. */
313 /* FIXME: currently hardcoded to 128Mb. */
316 while (mask > current_machine->ram_size) {
319 return mask & 0x0ffe0000;
321 case 0x5c: return 1; /* DRAM bank 1 empty. */
322 case 0xcb: return s->par;
323 case 0x170: return s->uivr[0];
324 case 0x1b0: return s->uivr[1];
326 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad MBAR offset 0x%"PRIx16"\n",
331 static void m5206_mbar_write(m5206_mbar_state *s, uint16_t offset,
332 uint64_t value, unsigned size)
334 if (offset >= 0x100 && offset < 0x120) {
335 m5206_timer_write(s->timer[0], offset - 0x100, value);
337 } else if (offset >= 0x120 && offset < 0x140) {
338 m5206_timer_write(s->timer[1], offset - 0x120, value);
340 } else if (offset >= 0x140 && offset < 0x160) {
341 mcf_uart_write(s->uart[0], offset - 0x140, value, size);
343 } else if (offset >= 0x180 && offset < 0x1a0) {
344 mcf_uart_write(s->uart[1], offset - 0x180, value, size);
352 s->icr[offset - 0x13] = value;
353 m5206_mbar_update(s);
357 m5206_mbar_update(s);
363 /* TODO: implement watchdog. */
374 case 0x178: case 0x17c: case 0x1c8: case 0x1bc:
375 /* Not implemented: UART Output port bits. */
381 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad MBAR offset 0x%"PRIx16"\n",
387 /* Internal peripherals use a variety of register widths.
388 This lookup table allows a single routine to handle all of them. */
389 static const uint8_t m5206_mbar_width[] =
391 /* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
392 /* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
393 /* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4,
394 /* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
395 /* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0,
396 /* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
397 /* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
398 /* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
401 static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset);
402 static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset);
404 static uint32_t m5206_mbar_readb(void *opaque, hwaddr offset)
406 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
408 if (offset >= 0x200) {
409 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX,
413 if (m5206_mbar_width[offset >> 2] > 1) {
415 val = m5206_mbar_readw(opaque, offset & ~1);
416 if ((offset & 1) == 0) {
421 return m5206_mbar_read(s, offset, 1);
424 static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset)
426 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
429 if (offset >= 0x200) {
430 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX,
434 width = m5206_mbar_width[offset >> 2];
437 val = m5206_mbar_readl(opaque, offset & ~3);
438 if ((offset & 3) == 0)
441 } else if (width < 2) {
443 val = m5206_mbar_readb(opaque, offset) << 8;
444 val |= m5206_mbar_readb(opaque, offset + 1);
447 return m5206_mbar_read(s, offset, 2);
450 static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset)
452 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
455 if (offset >= 0x200) {
456 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX,
460 width = m5206_mbar_width[offset >> 2];
463 val = m5206_mbar_readw(opaque, offset) << 16;
464 val |= m5206_mbar_readw(opaque, offset + 2);
467 return m5206_mbar_read(s, offset, 4);
470 static void m5206_mbar_writew(void *opaque, hwaddr offset,
472 static void m5206_mbar_writel(void *opaque, hwaddr offset,
475 static void m5206_mbar_writeb(void *opaque, hwaddr offset,
478 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
481 if (offset >= 0x200) {
482 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX,
486 width = m5206_mbar_width[offset >> 2];
489 tmp = m5206_mbar_readw(opaque, offset & ~1);
491 tmp = (tmp & 0xff00) | value;
493 tmp = (tmp & 0x00ff) | (value << 8);
495 m5206_mbar_writew(opaque, offset & ~1, tmp);
498 m5206_mbar_write(s, offset, value, 1);
501 static void m5206_mbar_writew(void *opaque, hwaddr offset,
504 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
507 if (offset >= 0x200) {
508 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX,
512 width = m5206_mbar_width[offset >> 2];
515 tmp = m5206_mbar_readl(opaque, offset & ~3);
517 tmp = (tmp & 0xffff0000) | value;
519 tmp = (tmp & 0x0000ffff) | (value << 16);
521 m5206_mbar_writel(opaque, offset & ~3, tmp);
523 } else if (width < 2) {
524 m5206_mbar_writeb(opaque, offset, value >> 8);
525 m5206_mbar_writeb(opaque, offset + 1, value & 0xff);
528 m5206_mbar_write(s, offset, value, 2);
531 static void m5206_mbar_writel(void *opaque, hwaddr offset,
534 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
537 if (offset >= 0x200) {
538 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX,
542 width = m5206_mbar_width[offset >> 2];
544 m5206_mbar_writew(opaque, offset, value >> 16);
545 m5206_mbar_writew(opaque, offset + 2, value & 0xffff);
548 m5206_mbar_write(s, offset, value, 4);
551 static uint64_t m5206_mbar_readfn(void *opaque, hwaddr addr, unsigned size)
555 return m5206_mbar_readb(opaque, addr);
557 return m5206_mbar_readw(opaque, addr);
559 return m5206_mbar_readl(opaque, addr);
561 g_assert_not_reached();
565 static void m5206_mbar_writefn(void *opaque, hwaddr addr,
566 uint64_t value, unsigned size)
570 m5206_mbar_writeb(opaque, addr, value);
573 m5206_mbar_writew(opaque, addr, value);
576 m5206_mbar_writel(opaque, addr, value);
579 g_assert_not_reached();
583 static const MemoryRegionOps m5206_mbar_ops = {
584 .read = m5206_mbar_readfn,
585 .write = m5206_mbar_writefn,
586 .valid.min_access_size = 1,
587 .valid.max_access_size = 4,
588 .endianness = DEVICE_NATIVE_ENDIAN,
591 static void mcf5206_mbar_realize(DeviceState *dev, Error **errp)
593 m5206_mbar_state *s = MCF5206_MBAR(dev);
595 memory_region_init_io(&s->iomem, NULL, &m5206_mbar_ops, s,
597 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
599 s->pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
600 s->timer[0] = m5206_timer_init(s->pic[9]);
601 s->timer[1] = m5206_timer_init(s->pic[10]);
602 s->uart[0] = mcf_uart_init(s->pic[12], serial_hd(0));
603 s->uart[1] = mcf_uart_init(s->pic[13], serial_hd(1));
604 s->cpu = M68K_CPU(qemu_get_cpu(0));
607 static void mcf5206_mbar_class_init(ObjectClass *oc, void *data)
609 DeviceClass *dc = DEVICE_CLASS(oc);
611 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
612 dc->desc = "MCF5206 system integration module";
613 dc->realize = mcf5206_mbar_realize;
614 dc->reset = m5206_mbar_reset;
617 static const TypeInfo mcf5206_mbar_info = {
618 .name = TYPE_MCF5206_MBAR,
619 .parent = TYPE_SYS_BUS_DEVICE,
620 .instance_size = sizeof(m5206_mbar_state),
621 .class_init = mcf5206_mbar_class_init,
624 static void mcf5206_mbar_register_types(void)
626 type_register_static(&mcf5206_mbar_info);
629 type_init(mcf5206_mbar_register_types)