hw/mem/cxl_type3.c

   1 #include "qemu/osdep.h"
   2 #include "qemu/units.h"
   3 #include "qemu/error-report.h"
   4 #include "hw/mem/memory-device.h"
   5 #include "hw/mem/pc-dimm.h"
   6 #include "hw/pci/pci.h"
   7 #include "hw/qdev-properties.h"
   8 #include "qapi/error.h"
   9 #include "qemu/log.h"
  10 #include "qemu/module.h"
  11 #include "qemu/pmem.h"
  12 #include "qemu/range.h"
  13 #include "qemu/rcu.h"
  14 #include "sysemu/hostmem.h"
  15 #include "hw/cxl/cxl.h"
  16
  17 static void build_dvsecs(CXLType3Dev *ct3d)
  18 {
  19     CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
  20     uint8_t *dvsec;
  21
  22     dvsec = (uint8_t *)&(CXLDVSECDevice){
  23         .cap = 0x1e,
  24         .ctrl = 0x2,
  25         .status2 = 0x2,
  26         .range1_size_hi = ct3d->hostmem->size >> 32,
  27         .range1_size_lo = (2 << 5) | (2 << 2) | 0x3 |
  28         (ct3d->hostmem->size & 0xF0000000),
  29         .range1_base_hi = 0,
  30         .range1_base_lo = 0,
  31     };
  32     cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
  33                                PCIE_CXL_DEVICE_DVSEC_LENGTH,
  34                                PCIE_CXL_DEVICE_DVSEC,
  35                                PCIE_CXL2_DEVICE_DVSEC_REVID, dvsec);
  36
  37     dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
  38         .rsvd         = 0,
  39         .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
  40         .reg0_base_hi = 0,
  41         .reg1_base_lo = RBI_CXL_DEVICE_REG | CXL_DEVICE_REG_BAR_IDX,
  42         .reg1_base_hi = 0,
  43     };
  44     cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
  45                                REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
  46                                REG_LOC_DVSEC_REVID, dvsec);
  47     dvsec = (uint8_t *)&(CXLDVSECDeviceGPF){
  48         .phase2_duration = 0x603, /* 3 seconds */
  49         .phase2_power = 0x33, /* 0x33 miliwatts */
  50     };
  51     cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
  52                                GPF_DEVICE_DVSEC_LENGTH, GPF_PORT_DVSEC,
  53                                GPF_DEVICE_DVSEC_REVID, dvsec);
  54 }
  55
  56 static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)
  57 {
  58     ComponentRegisters *cregs = &ct3d->cxl_cstate.crb;
  59     uint32_t *cache_mem = cregs->cache_mem_registers;
  60
  61     assert(which == 0);
  62
  63     /* TODO: Sanity checks that the decoder is possible */
  64     ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
  65     ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0);
  66
  67     ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
  68 }
  69
  70 static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
  71                            unsigned size)
  72 {
  73     CXLComponentState *cxl_cstate = opaque;
  74     ComponentRegisters *cregs = &cxl_cstate->crb;
  75     CXLType3Dev *ct3d = container_of(cxl_cstate, CXLType3Dev, cxl_cstate);
  76     uint32_t *cache_mem = cregs->cache_mem_registers;
  77     bool should_commit = false;
  78     int which_hdm = -1;
  79
  80     assert(size == 4);
  81     g_assert(offset < CXL2_COMPONENT_CM_REGION_SIZE);
  82
  83     switch (offset) {
  84     case A_CXL_HDM_DECODER0_CTRL:
  85         should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
  86         which_hdm = 0;
  87         break;
  88     default:
  89         break;
  90     }
  91
  92     stl_le_p((uint8_t *)cache_mem + offset, value);
  93     if (should_commit) {
  94         hdm_decoder_commit(ct3d, which_hdm);
  95     }
  96 }
  97
  98 static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
  99 {
 100     MemoryRegion *mr;
 101
 102     if (!ct3d->hostmem) {
 103         error_setg(errp, "memdev property must be set");
 104         return false;
 105     }
 106
 107     mr = host_memory_backend_get_memory(ct3d->hostmem);
 108     if (!mr) {
 109         error_setg(errp, "memdev property must be set");
 110         return false;
 111     }
 112     memory_region_set_nonvolatile(mr, true);
 113     memory_region_set_enabled(mr, true);
 114     host_memory_backend_set_mapped(ct3d->hostmem, true);
 115     ct3d->cxl_dstate.pmem_size = ct3d->hostmem->size;
 116
 117     if (!ct3d->lsa) {
 118         error_setg(errp, "lsa property must be set");
 119         return false;
 120     }
 121
 122     return true;
 123 }
 124
 125 static void ct3_realize(PCIDevice *pci_dev, Error **errp)
 126 {
 127     CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
 128     CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
 129     ComponentRegisters *regs = &cxl_cstate->crb;
 130     MemoryRegion *mr = &regs->component_registers;
 131     uint8_t *pci_conf = pci_dev->config;
 132
 133     if (!cxl_setup_memory(ct3d, errp)) {
 134         return;
 135     }
 136
 137     pci_config_set_prog_interface(pci_conf, 0x10);
 138     pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL);
 139
 140     pcie_endpoint_cap_init(pci_dev, 0x80);
 141     cxl_cstate->dvsec_offset = 0x100;
 142
 143     ct3d->cxl_cstate.pdev = pci_dev;
 144     build_dvsecs(ct3d);
 145
 146     regs->special_ops = g_new0(MemoryRegionOps, 1);
 147     regs->special_ops->write = ct3d_reg_write;
 148
 149     cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate,
 150                                       TYPE_CXL_TYPE3);
 151
 152     pci_register_bar(
 153         pci_dev, CXL_COMPONENT_REG_BAR_IDX,
 154         PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, mr);
 155
 156     cxl_device_register_block_init(OBJECT(pci_dev), &ct3d->cxl_dstate);
 157     pci_register_bar(pci_dev, CXL_DEVICE_REG_BAR_IDX,
 158                      PCI_BASE_ADDRESS_SPACE_MEMORY |
 159                          PCI_BASE_ADDRESS_MEM_TYPE_64,
 160                      &ct3d->cxl_dstate.device_registers);
 161 }
 162
 163 static void ct3_exit(PCIDevice *pci_dev)
 164 {
 165     CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
 166     CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
 167     ComponentRegisters *regs = &cxl_cstate->crb;
 168
 169     g_free(regs->special_ops);
 170 }
 171
 172 static void ct3d_reset(DeviceState *dev)
 173 {
 174     CXLType3Dev *ct3d = CXL_TYPE3(dev);
 175     uint32_t *reg_state = ct3d->cxl_cstate.crb.cache_mem_registers;
 176     uint32_t *write_msk = ct3d->cxl_cstate.crb.cache_mem_regs_write_mask;
 177
 178     cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DEVICE);
 179     cxl_device_register_init_common(&ct3d->cxl_dstate);
 180 }
 181
 182 static Property ct3_props[] = {
 183     DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND,
 184                      HostMemoryBackend *),
 185     DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND,
 186                      HostMemoryBackend *),
 187     DEFINE_PROP_END_OF_LIST(),
 188 };
 189
 190 static uint64_t get_lsa_size(CXLType3Dev *ct3d)
 191 {
 192     MemoryRegion *mr;
 193
 194     mr = host_memory_backend_get_memory(ct3d->lsa);
 195     return memory_region_size(mr);
 196 }
 197
 198 static void validate_lsa_access(MemoryRegion *mr, uint64_t size,
 199                                 uint64_t offset)
 200 {
 201     assert(offset + size <= memory_region_size(mr));
 202     assert(offset + size > offset);
 203 }
 204
 205 static uint64_t get_lsa(CXLType3Dev *ct3d, void *buf, uint64_t size,
 206                     uint64_t offset)
 207 {
 208     MemoryRegion *mr;
 209     void *lsa;
 210
 211     mr = host_memory_backend_get_memory(ct3d->lsa);
 212     validate_lsa_access(mr, size, offset);
 213
 214     lsa = memory_region_get_ram_ptr(mr) + offset;
 215     memcpy(buf, lsa, size);
 216
 217     return size;
 218 }
 219
 220 static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size,
 221                     uint64_t offset)
 222 {
 223     MemoryRegion *mr;
 224     void *lsa;
 225
 226     mr = host_memory_backend_get_memory(ct3d->lsa);
 227     validate_lsa_access(mr, size, offset);
 228
 229     lsa = memory_region_get_ram_ptr(mr) + offset;
 230     memcpy(lsa, buf, size);
 231     memory_region_set_dirty(mr, offset, size);
 232
 233     /*
 234      * Just like the PMEM, if the guest is not allowed to exit gracefully, label
 235      * updates will get lost.
 236      */
 237 }
 238
 239 static void ct3_class_init(ObjectClass *oc, void *data)
 240 {
 241     DeviceClass *dc = DEVICE_CLASS(oc);
 242     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
 243     CXLType3Class *cvc = CXL_TYPE3_CLASS(oc);
 244
 245     pc->realize = ct3_realize;
 246     pc->exit = ct3_exit;
 247     pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
 248     pc->vendor_id = PCI_VENDOR_ID_INTEL;
 249     pc->device_id = 0xd93; /* LVF for now */
 250     pc->revision = 1;
 251
 252     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 253     dc->desc = "CXL PMEM Device (Type 3)";
 254     dc->reset = ct3d_reset;
 255     device_class_set_props(dc, ct3_props);
 256
 257     cvc->get_lsa_size = get_lsa_size;
 258     cvc->get_lsa = get_lsa;
 259     cvc->set_lsa = set_lsa;
 260 }
 261
 262 static const TypeInfo ct3d_info = {
 263     .name = TYPE_CXL_TYPE3,
 264     .parent = TYPE_PCI_DEVICE,
 265     .class_size = sizeof(struct CXLType3Class),
 266     .class_init = ct3_class_init,
 267     .instance_size = sizeof(CXLType3Dev),
 268     .interfaces = (InterfaceInfo[]) {
 269         { INTERFACE_CXL_DEVICE },
 270         { INTERFACE_PCIE_DEVICE },
 271         {}
 272     },
 273 };
 274
 275 static void ct3d_registers(void)
 276 {
 277     type_register_static(&ct3d_info);
 278 }
 279
 280 type_init(ct3d_registers);