hw/mem/cxl_type3.c

   1 #include "qemu/osdep.h"
   2 #include "qemu/units.h"
   3 #include "qemu/error-report.h"
   4 #include "hw/mem/memory-device.h"
   5 #include "hw/mem/pc-dimm.h"
   6 #include "hw/pci/pci.h"
   7 #include "hw/qdev-properties.h"
   8 #include "qapi/error.h"
   9 #include "qemu/log.h"
  10 #include "qemu/module.h"
  11 #include "qemu/range.h"
  12 #include "qemu/rcu.h"
  13 #include "sysemu/hostmem.h"
  14 #include "hw/cxl/cxl.h"
  15
  16 static void build_dvsecs(CXLType3Dev *ct3d)
  17 {
  18     CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
  19     uint8_t *dvsec;
  20
  21     dvsec = (uint8_t *)&(CXLDVSECDevice){
  22         .cap = 0x1e,
  23         .ctrl = 0x2,
  24         .status2 = 0x2,
  25         .range1_size_hi = ct3d->hostmem->size >> 32,
  26         .range1_size_lo = (2 << 5) | (2 << 2) | 0x3 |
  27         (ct3d->hostmem->size & 0xF0000000),
  28         .range1_base_hi = 0,
  29         .range1_base_lo = 0,
  30     };
  31     cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
  32                                PCIE_CXL_DEVICE_DVSEC_LENGTH,
  33                                PCIE_CXL_DEVICE_DVSEC,
  34                                PCIE_CXL2_DEVICE_DVSEC_REVID, dvsec);
  35
  36     dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
  37         .rsvd         = 0,
  38         .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
  39         .reg0_base_hi = 0,
  40         .reg1_base_lo = RBI_CXL_DEVICE_REG | CXL_DEVICE_REG_BAR_IDX,
  41         .reg1_base_hi = 0,
  42     };
  43     cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
  44                                REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
  45                                REG_LOC_DVSEC_REVID, dvsec);
  46     dvsec = (uint8_t *)&(CXLDVSECDeviceGPF){
  47         .phase2_duration = 0x603, /* 3 seconds */
  48         .phase2_power = 0x33, /* 0x33 miliwatts */
  49     };
  50     cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
  51                                GPF_DEVICE_DVSEC_LENGTH, GPF_PORT_DVSEC,
  52                                GPF_DEVICE_DVSEC_REVID, dvsec);
  53 }
  54
  55 static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)
  56 {
  57     ComponentRegisters *cregs = &ct3d->cxl_cstate.crb;
  58     uint32_t *cache_mem = cregs->cache_mem_registers;
  59
  60     assert(which == 0);
  61
  62     /* TODO: Sanity checks that the decoder is possible */
  63     ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
  64     ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0);
  65
  66     ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
  67 }
  68
  69 static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
  70                            unsigned size)
  71 {
  72     CXLComponentState *cxl_cstate = opaque;
  73     ComponentRegisters *cregs = &cxl_cstate->crb;
  74     CXLType3Dev *ct3d = container_of(cxl_cstate, CXLType3Dev, cxl_cstate);
  75     uint32_t *cache_mem = cregs->cache_mem_registers;
  76     bool should_commit = false;
  77     int which_hdm = -1;
  78
  79     assert(size == 4);
  80     g_assert(offset < CXL2_COMPONENT_CM_REGION_SIZE);
  81
  82     switch (offset) {
  83     case A_CXL_HDM_DECODER0_CTRL:
  84         should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
  85         which_hdm = 0;
  86         break;
  87     default:
  88         break;
  89     }
  90
  91     stl_le_p((uint8_t *)cache_mem + offset, value);
  92     if (should_commit) {
  93         hdm_decoder_commit(ct3d, which_hdm);
  94     }
  95 }
  96
  97 static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
  98 {
  99     MemoryRegion *mr;
 100
 101     if (!ct3d->hostmem) {
 102         error_setg(errp, "memdev property must be set");
 103         return false;
 104     }
 105
 106     mr = host_memory_backend_get_memory(ct3d->hostmem);
 107     if (!mr) {
 108         error_setg(errp, "memdev property must be set");
 109         return false;
 110     }
 111     memory_region_set_nonvolatile(mr, true);
 112     memory_region_set_enabled(mr, true);
 113     host_memory_backend_set_mapped(ct3d->hostmem, true);
 114     ct3d->cxl_dstate.pmem_size = ct3d->hostmem->size;
 115
 116     return true;
 117 }
 118
 119 static void ct3_realize(PCIDevice *pci_dev, Error **errp)
 120 {
 121     CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
 122     CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
 123     ComponentRegisters *regs = &cxl_cstate->crb;
 124     MemoryRegion *mr = &regs->component_registers;
 125     uint8_t *pci_conf = pci_dev->config;
 126
 127     if (!cxl_setup_memory(ct3d, errp)) {
 128         return;
 129     }
 130
 131     pci_config_set_prog_interface(pci_conf, 0x10);
 132     pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL);
 133
 134     pcie_endpoint_cap_init(pci_dev, 0x80);
 135     cxl_cstate->dvsec_offset = 0x100;
 136
 137     ct3d->cxl_cstate.pdev = pci_dev;
 138     build_dvsecs(ct3d);
 139
 140     regs->special_ops = g_new0(MemoryRegionOps, 1);
 141     regs->special_ops->write = ct3d_reg_write;
 142
 143     cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate,
 144                                       TYPE_CXL_TYPE3);
 145
 146     pci_register_bar(
 147         pci_dev, CXL_COMPONENT_REG_BAR_IDX,
 148         PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, mr);
 149
 150     cxl_device_register_block_init(OBJECT(pci_dev), &ct3d->cxl_dstate);
 151     pci_register_bar(pci_dev, CXL_DEVICE_REG_BAR_IDX,
 152                      PCI_BASE_ADDRESS_SPACE_MEMORY |
 153                          PCI_BASE_ADDRESS_MEM_TYPE_64,
 154                      &ct3d->cxl_dstate.device_registers);
 155 }
 156
 157 static void ct3_exit(PCIDevice *pci_dev)
 158 {
 159     CXLType3Dev *ct3d = CXL_TYPE3(pci_dev);
 160     CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
 161     ComponentRegisters *regs = &cxl_cstate->crb;
 162
 163     g_free(regs->special_ops);
 164 }
 165
 166 static void ct3d_reset(DeviceState *dev)
 167 {
 168     CXLType3Dev *ct3d = CXL_TYPE3(dev);
 169     uint32_t *reg_state = ct3d->cxl_cstate.crb.cache_mem_registers;
 170     uint32_t *write_msk = ct3d->cxl_cstate.crb.cache_mem_regs_write_mask;
 171
 172     cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DEVICE);
 173     cxl_device_register_init_common(&ct3d->cxl_dstate);
 174 }
 175
 176 static Property ct3_props[] = {
 177     DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND,
 178                      HostMemoryBackend *),
 179     DEFINE_PROP_END_OF_LIST(),
 180 };
 181
 182 static uint64_t get_lsa_size(CXLType3Dev *ct3d)
 183 {
 184     return 0;
 185 }
 186
 187 static void ct3_class_init(ObjectClass *oc, void *data)
 188 {
 189     DeviceClass *dc = DEVICE_CLASS(oc);
 190     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
 191     CXLType3Class *cvc = CXL_TYPE3_CLASS(oc);
 192
 193     pc->realize = ct3_realize;
 194     pc->exit = ct3_exit;
 195     pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
 196     pc->vendor_id = PCI_VENDOR_ID_INTEL;
 197     pc->device_id = 0xd93; /* LVF for now */
 198     pc->revision = 1;
 199
 200     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 201     dc->desc = "CXL PMEM Device (Type 3)";
 202     dc->reset = ct3d_reset;
 203     device_class_set_props(dc, ct3_props);
 204
 205     cvc->get_lsa_size = get_lsa_size;
 206 }
 207
 208 static const TypeInfo ct3d_info = {
 209     .name = TYPE_CXL_TYPE3,
 210     .parent = TYPE_PCI_DEVICE,
 211     .class_size = sizeof(struct CXLType3Class),
 212     .class_init = ct3_class_init,
 213     .instance_size = sizeof(CXLType3Dev),
 214     .interfaces = (InterfaceInfo[]) {
 215         { INTERFACE_CXL_DEVICE },
 216         { INTERFACE_PCIE_DEVICE },
 217         {}
 218     },
 219 };
 220
 221 static void ct3d_registers(void)
 222 {
 223     type_register_static(&ct3d_info);
 224 }
 225
 226 type_init(ct3d_registers);