2 * ARM dummy L210, L220, PL310 cache controller.
4 * Copyright (c) 2010-2012 Calxeda
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or any later version, as published by the Free Software
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/sysbus.h"
24 #include "migration/vmstate.h"
26 #include "qemu/module.h"
27 #include "qom/object.h"
30 #define CACHE_ID 0x410000c8
32 #define TYPE_ARM_L2X0 "l2x0"
33 OBJECT_DECLARE_SIMPLE_TYPE(L2x0State, ARM_L2X0)
36 SysBusDevice parent_obj;
44 uint32_t filter_start;
48 static const VMStateDescription vmstate_l2x0 = {
51 .minimum_version_id = 1,
52 .fields = (VMStateField[]) {
53 VMSTATE_UINT32(ctrl, L2x0State),
54 VMSTATE_UINT32(aux_ctrl, L2x0State),
55 VMSTATE_UINT32(data_ctrl, L2x0State),
56 VMSTATE_UINT32(tag_ctrl, L2x0State),
57 VMSTATE_UINT32(filter_start, L2x0State),
58 VMSTATE_UINT32(filter_end, L2x0State),
64 static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
68 L2x0State *s = (L2x0State *)opaque;
70 if (offset >= 0x730 && offset < 0x800) {
71 return 0; /* cache ops complete */
77 /* aux_ctrl values affect cache_type values */
78 cache_data = (s->aux_ctrl & (7 << 17)) >> 15;
79 cache_data |= (s->aux_ctrl & (1 << 16)) >> 16;
80 return s->cache_type |= (cache_data << 18) | (cache_data << 6);
90 return s->filter_start;
100 qemu_log_mask(LOG_GUEST_ERROR,
101 "l2x0_priv_read: Bad offset %x\n", (int)offset);
107 static void l2x0_priv_write(void *opaque, hwaddr offset,
108 uint64_t value, unsigned size)
110 L2x0State *s = (L2x0State *)opaque;
112 if (offset >= 0x730 && offset < 0x800) {
127 s->data_ctrl = value;
130 s->filter_start = value;
133 s->filter_end = value;
142 qemu_log_mask(LOG_GUEST_ERROR,
143 "l2x0_priv_write: Bad offset %x\n", (int)offset);
148 static void l2x0_priv_reset(DeviceState *dev)
150 L2x0State *s = ARM_L2X0(dev);
153 s->aux_ctrl = 0x02020000;
160 static const MemoryRegionOps l2x0_mem_ops = {
161 .read = l2x0_priv_read,
162 .write = l2x0_priv_write,
163 .endianness = DEVICE_NATIVE_ENDIAN,
166 static void l2x0_priv_init(Object *obj)
168 L2x0State *s = ARM_L2X0(obj);
169 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
171 memory_region_init_io(&s->iomem, obj, &l2x0_mem_ops, s,
173 sysbus_init_mmio(dev, &s->iomem);
176 static Property l2x0_properties[] = {
177 DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100),
178 DEFINE_PROP_END_OF_LIST(),
181 static void l2x0_class_init(ObjectClass *klass, void *data)
183 DeviceClass *dc = DEVICE_CLASS(klass);
185 dc->vmsd = &vmstate_l2x0;
186 device_class_set_props(dc, l2x0_properties);
187 dc->reset = l2x0_priv_reset;
190 static const TypeInfo l2x0_info = {
191 .name = TYPE_ARM_L2X0,
192 .parent = TYPE_SYS_BUS_DEVICE,
193 .instance_size = sizeof(L2x0State),
194 .instance_init = l2x0_priv_init,
195 .class_init = l2x0_class_init,
198 static void l2x0_register_types(void)
200 type_register_static(&l2x0_info);
203 type_init(l2x0_register_types)