2 * Arm SSE CPU PWRCTRL register block
4 * Copyright (c) 2021 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
13 * This is a model of the "CPU<N>_PWRCTRL block" which is part of the
14 * Arm Corstone SSE-300 Example Subsystem and documented in
15 * https://developer.arm.com/documentation/101773/0000
18 #include "qemu/osdep.h"
20 #include "qemu/module.h"
22 #include "qapi/error.h"
23 #include "migration/vmstate.h"
24 #include "hw/sysbus.h"
25 #include "hw/registerfields.h"
26 #include "hw/misc/armsse-cpu-pwrctrl.h"
43 static const int cpu_pwrctrl_id[] = {
44 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
45 0x5a, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
46 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
49 static uint64_t pwrctrl_read(void *opaque, hwaddr offset, unsigned size)
51 ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(opaque);
58 case A_PID4 ... A_CID3:
59 r = cpu_pwrctrl_id[(offset - A_PID4) / 4];
62 qemu_log_mask(LOG_GUEST_ERROR,
63 "SSE CPU_PWRCTRL read: bad offset %x\n", (int)offset);
67 trace_armsse_cpu_pwrctrl_read(offset, r, size);
71 static void pwrctrl_write(void *opaque, hwaddr offset,
72 uint64_t value, unsigned size)
74 ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(opaque);
76 trace_armsse_cpu_pwrctrl_write(offset, value, size);
80 qemu_log_mask(LOG_UNIMP,
81 "SSE CPU_PWRCTRL: CPUPWRCFG unimplemented\n");
85 qemu_log_mask(LOG_GUEST_ERROR,
86 "SSE CPU_PWRCTRL write: bad offset 0x%x\n", (int)offset);
91 static const MemoryRegionOps pwrctrl_ops = {
93 .write = pwrctrl_write,
94 .endianness = DEVICE_LITTLE_ENDIAN,
95 .impl.min_access_size = 4,
96 .impl.max_access_size = 4,
97 .valid.min_access_size = 4,
98 .valid.max_access_size = 4,
101 static void pwrctrl_reset(DeviceState *dev)
103 ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(dev);
108 static const VMStateDescription pwrctrl_vmstate = {
109 .name = "armsse-cpu-pwrctrl",
111 .minimum_version_id = 1,
112 .fields = (VMStateField[]) {
113 VMSTATE_UINT32(cpupwrcfg, ARMSSECPUPwrCtrl),
114 VMSTATE_END_OF_LIST()
118 static void pwrctrl_init(Object *obj)
120 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
121 ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(obj);
123 memory_region_init_io(&s->iomem, obj, &pwrctrl_ops,
124 s, "armsse-cpu-pwrctrl", 0x1000);
125 sysbus_init_mmio(sbd, &s->iomem);
128 static void pwrctrl_class_init(ObjectClass *klass, void *data)
130 DeviceClass *dc = DEVICE_CLASS(klass);
132 dc->reset = pwrctrl_reset;
133 dc->vmsd = &pwrctrl_vmstate;
136 static const TypeInfo pwrctrl_info = {
137 .name = TYPE_ARMSSE_CPU_PWRCTRL,
138 .parent = TYPE_SYS_BUS_DEVICE,
139 .instance_size = sizeof(ARMSSECPUPwrCtrl),
140 .instance_init = pwrctrl_init,
141 .class_init = pwrctrl_class_init,
144 static void pwrctrl_register_types(void)
146 type_register_static(&pwrctrl_info);
149 type_init(pwrctrl_register_types);