2 * HP-PARISC Lasi chipset emulation.
4 * (C) 2019 by Helge Deller <deller@gmx.de>
6 * This work is licensed under the GNU GPL license version 2 or later.
8 * Documentation available at:
9 * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
12 #include "qemu/osdep.h"
13 #include "qemu/units.h"
15 #include "qapi/error.h"
18 #include "sysemu/sysemu.h"
19 #include "sysemu/runstate.h"
20 #include "migration/vmstate.h"
21 #include "qom/object.h"
22 #include "hw/misc/lasi.h"
25 static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
26 unsigned size, bool is_write,
43 case LASI_PCR ... LASI_AMR:
47 trace_lasi_chip_mem_valid(addr, ret);
51 static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
52 uint64_t *data, unsigned size,
55 LasiState *s = opaque;
56 MemTxResult ret = MEMTX_OK;
68 /* Any read to IPR clears the register. */
72 val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
89 case LASI_VER: /* only version 0 existed. */
101 /* Controlled by lasi_chip_mem_valid above. */
102 g_assert_not_reached();
105 trace_lasi_chip_read(addr, val);
111 static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
112 uint64_t val, unsigned size,
115 LasiState *s = opaque;
117 trace_lasi_chip_write(addr, val);
125 if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff)) {
126 qemu_log_mask(LOG_GUEST_ERROR,
127 "LASI: tried to set invalid %lx IMR value.\n",
128 (unsigned long) val);
132 /* Any write to IPR clears the register. */
137 /* if (val & ICR_TOC_BIT) issue_toc(); */
144 /* XXX: reset parallel port */
147 /* XXX: reset serial port */
150 /* XXX: reset LAN card */
153 s->rtc_ref = val - time(NULL);
157 if (val == 0x02) { /* immediately power off */
158 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
168 break; /* XXX: TODO: Reset various devices. */
174 /* Controlled by lasi_chip_mem_valid above. */
175 g_assert_not_reached();
180 static const MemoryRegionOps lasi_chip_ops = {
181 .read_with_attrs = lasi_chip_read_with_attrs,
182 .write_with_attrs = lasi_chip_write_with_attrs,
183 .endianness = DEVICE_BIG_ENDIAN,
185 .min_access_size = 1,
186 .max_access_size = 4,
187 .accepts = lasi_chip_mem_valid,
190 .min_access_size = 1,
191 .max_access_size = 4,
195 static const VMStateDescription vmstate_lasi = {
198 .minimum_version_id = 1,
199 .fields = (VMStateField[]) {
200 VMSTATE_UINT32(irr, LasiState),
201 VMSTATE_UINT32(imr, LasiState),
202 VMSTATE_UINT32(ipr, LasiState),
203 VMSTATE_UINT32(icr, LasiState),
204 VMSTATE_UINT32(iar, LasiState),
205 VMSTATE_UINT32(errlog, LasiState),
206 VMSTATE_UINT32(amr, LasiState),
207 VMSTATE_UINT32_V(rtc_ref, LasiState, 2),
208 VMSTATE_END_OF_LIST()
213 static void lasi_set_irq(void *opaque, int irq, int level)
215 LasiState *s = opaque;
216 uint32_t bit = 1u << irq;
221 uint32_t iar = s->iar;
223 if ((s->icr & ICR_BUS_ERROR_BIT) == 0) {
224 stl_be_phys(&address_space_memory, iar & -32, iar & 31);
230 static void lasi_reset(DeviceState *dev)
232 LasiState *s = LASI_CHIP(dev);
234 s->iar = 0xFFFB0000 + 3; /* CPU_HPA + 3 */
236 /* Real time clock (RTC), it's only one 32-bit counter @9000 */
240 static void lasi_init(Object *obj)
242 LasiState *s = LASI_CHIP(obj);
243 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
245 memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
246 s, "lasi", 0x100000);
248 sysbus_init_mmio(sbd, &s->this_mem);
250 qdev_init_gpio_in(DEVICE(obj), lasi_set_irq, LASI_IRQS);
253 static void lasi_class_init(ObjectClass *klass, void *data)
255 DeviceClass *dc = DEVICE_CLASS(klass);
257 dc->reset = lasi_reset;
258 dc->vmsd = &vmstate_lasi;
261 static const TypeInfo lasi_pcihost_info = {
262 .name = TYPE_LASI_CHIP,
263 .parent = TYPE_SYS_BUS_DEVICE,
264 .instance_init = lasi_init,
265 .instance_size = sizeof(LasiState),
266 .class_init = lasi_class_init,
269 static void lasi_register_types(void)
271 type_register_static(&lasi_pcihost_info);
274 type_init(lasi_register_types)