3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
5 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Copyright (c) 2007 Jocelyn Mayer
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu/datadir.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
31 #include "hw/ppc/ppc.h"
32 #include "hw/qdev-properties.h"
34 #include "hw/boards.h"
35 #include "hw/input/adb.h"
36 #include "sysemu/sysemu.h"
38 #include "hw/isa/isa.h"
39 #include "hw/pci/pci.h"
40 #include "hw/pci/pci_host.h"
41 #include "hw/pci-host/grackle.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/misc/macio/macio.h"
45 #include "hw/loader.h"
46 #include "hw/fw-path-provider.h"
48 #include "qemu/error-report.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/reset.h"
54 #define CFG_ADDR 0xf0000510
55 #define TBFREQ 16600000UL
56 #define CLOCKFREQ 266000000UL
57 #define BUSFREQ 66000000UL
59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
61 #define GRACKLE_BASE 0xfec00000
62 #define PROM_BASE 0xffc00000
63 #define PROM_SIZE (4 * MiB)
65 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
68 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
71 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
73 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
76 static void ppc_heathrow_reset(void *opaque)
78 PowerPCCPU *cpu = opaque;
83 static void ppc_heathrow_init(MachineState *machine)
85 const char *bios_name = machine->firmware ?: PROM_FILENAME;
86 PowerPCCPU *cpu = NULL;
87 CPUPPCState *env = NULL;
89 int i, bios_size = -1;
90 MemoryRegion *bios = g_new(MemoryRegion, 1);
92 uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0;
93 int32_t kernel_size = 0, initrd_size = 0;
96 MACIOIDEState *macio_ide;
98 DeviceState *dev, *pic_dev, *grackle_dev;
100 uint16_t ppc_boot_device;
101 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
103 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
106 for (i = 0; i < machine->smp.cpus; i++) {
107 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
110 /* Set time-base frequency to 16.6 Mhz */
111 cpu_ppc_tb_init(env, TBFREQ);
112 qemu_register_reset(ppc_heathrow_reset, cpu);
116 if (machine->ram_size > 2047 * MiB) {
117 error_report("Too much memory for this machine: %" PRId64 " MB, "
118 "maximum 2047 MB", machine->ram_size / MiB);
122 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
124 /* allocate and load firmware ROM */
125 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE,
127 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
129 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
131 /* Load OpenBIOS (ELF) */
132 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr,
133 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
134 /* Unfortunately, load_elf sign-extends reading elf32 */
135 bios_addr = (uint32_t)bios_addr;
137 if (bios_size <= 0) {
138 /* or if could not load ELF try loading a binary ROM image */
139 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
140 bios_addr = PROM_BASE;
144 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) {
145 error_report("could not load PowerPC bios '%s'", bios_name);
149 if (machine->kernel_filename) {
150 int bswap_needed = 0;
155 kernel_base = KERNEL_LOAD_ADDR;
156 kernel_size = load_elf(machine->kernel_filename, NULL,
157 translate_kernel_address, NULL, NULL, NULL,
158 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
160 kernel_size = load_aout(machine->kernel_filename, kernel_base,
161 machine->ram_size - kernel_base,
162 bswap_needed, TARGET_PAGE_SIZE);
164 kernel_size = load_image_targphys(machine->kernel_filename,
166 machine->ram_size - kernel_base);
167 if (kernel_size < 0) {
168 error_report("could not load kernel '%s'",
169 machine->kernel_filename);
173 if (machine->initrd_filename) {
174 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
176 initrd_size = load_image_targphys(machine->initrd_filename,
178 machine->ram_size - initrd_base);
179 if (initrd_size < 0) {
180 error_report("could not load initial ram disk '%s'",
181 machine->initrd_filename);
184 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
186 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
188 ppc_boot_device = 'm';
190 ppc_boot_device = '\0';
191 for (i = 0; machine->boot_config.order[i] != '\0'; i++) {
193 * TOFIX: for now, the second IDE channel is not properly
194 * used by OHW. The Mac floppy disk are not emulated.
195 * For now, OHW cannot boot from the network.
198 if (machine->boot_config.order[i] >= 'a' &&
199 machine->boot_config.order[i] <= 'f') {
200 ppc_boot_device = machine->boot_config.order[i];
204 if (machine->boot_config.order[i] >= 'c' &&
205 machine->boot_config.order[i] <= 'd') {
206 ppc_boot_device = machine->boot_config.order[i];
211 if (ppc_boot_device == '\0') {
212 error_report("No valid boot device for G3 Beige machine");
217 /* Grackle PCI host bridge */
218 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
219 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000);
220 s = SYS_BUS_DEVICE(grackle_dev);
221 sysbus_realize_and_unref(s, &error_fatal);
223 sysbus_mmio_map(s, 0, GRACKLE_BASE);
224 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
226 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
227 sysbus_mmio_get_region(s, 2));
228 /* Register 2 MB of ISA IO space */
229 memory_region_add_subregion(get_system_memory(), 0xfe000000,
230 sysbus_mmio_get_region(s, 3));
232 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus;
235 macio = OBJECT(pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO));
236 qdev_prop_set_uint64(DEVICE(macio), "frequency", tbfreq);
238 dev = DEVICE(object_resolve_path_component(macio, "escc"));
239 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
240 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
242 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal);
244 pic_dev = DEVICE(object_resolve_path_component(macio, "pic"));
245 for (i = 0; i < 4; i++) {
246 qdev_connect_gpio_out(grackle_dev, i,
247 qdev_get_gpio_in(pic_dev, 0x15 + i));
250 /* Connect the heathrow PIC outputs to the 6xx bus */
251 for (i = 0; i < machine->smp.cpus; i++) {
252 switch (PPC_INPUT(env)) {
253 case PPC_FLAGS_INPUT_6xx:
254 /* XXX: we register only 1 output pin for heathrow PIC */
255 qdev_connect_gpio_out(pic_dev, 0,
256 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
259 error_report("Bus model not supported on OldWorld Mac machine");
264 pci_vga_init(pci_bus);
266 for (i = 0; i < nb_nics; i++) {
267 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
271 ide_drive_get(hd, ARRAY_SIZE(hd));
272 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]"));
273 macio_ide_init_drives(macio_ide, hd);
275 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]"));
276 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
279 dev = DEVICE(object_resolve_path_component(macio, "cuda"));
280 adb_bus = qdev_get_child_bus(dev, "adb.0");
281 dev = qdev_new(TYPE_ADB_KEYBOARD);
282 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
283 dev = qdev_new(TYPE_ADB_MOUSE);
284 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
286 if (machine_usb(machine)) {
287 pci_create_simple(pci_bus, -1, "pci-ohci");
290 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
293 /* No PCI init: the BIOS will do it */
295 dev = qdev_new(TYPE_FW_CFG_MEM);
296 fw_cfg = FW_CFG(dev);
297 qdev_prop_set_uint32(dev, "data_width", 1);
298 qdev_prop_set_bit(dev, "dma_enabled", false);
299 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
301 s = SYS_BUS_DEVICE(dev);
302 sysbus_realize_and_unref(s, &error_fatal);
303 sysbus_mmio_map(s, 0, CFG_ADDR);
304 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
306 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
307 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
308 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
309 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
310 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
311 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
312 if (machine->kernel_cmdline) {
313 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
314 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
315 machine->kernel_cmdline);
317 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
319 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
320 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
321 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
323 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
324 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
325 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
327 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
331 hypercall = g_malloc(16);
332 kvmppc_get_hypercall(env, hypercall, 16);
333 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
334 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
336 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
337 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
338 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
339 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
341 /* MacOS NDRV VGA driver */
342 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
347 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
348 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
353 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
357 * Implementation of an interface to adjust firmware path
358 * for the bootindex property handling.
360 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
364 MACIOIDEState *macio_ide;
366 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
367 pci = PCI_DEVICE(dev);
368 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
371 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
372 macio_ide = MACIO_IDE(dev);
373 return g_strdup_printf("ata-3@%x", macio_ide->addr);
376 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
377 return g_strdup("disk");
380 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
381 return g_strdup("cdrom");
384 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
385 return g_strdup("disk");
391 static int heathrow_kvm_type(MachineState *machine, const char *arg)
393 /* Always force PR KVM */
397 static void heathrow_class_init(ObjectClass *oc, void *data)
399 MachineClass *mc = MACHINE_CLASS(oc);
400 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
402 mc->desc = "Heathrow based PowerMAC";
403 mc->init = ppc_heathrow_init;
404 mc->block_default_type = IF_IDE;
405 /* SMP is not supported currently */
408 mc->is_default = true;
410 /* TOFIX "cad" when Mac floppy is implemented */
411 mc->default_boot_order = "cd";
412 mc->kvm_type = heathrow_kvm_type;
413 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
414 mc->default_display = "std";
415 mc->ignore_boot_device_suffixes = true;
416 mc->default_ram_id = "ppc_heathrow.ram";
417 fwc->get_dev_path = heathrow_fw_dev_path;
420 static const TypeInfo ppc_heathrow_machine_info = {
421 .name = MACHINE_TYPE_NAME("g3beige"),
422 .parent = TYPE_MACHINE,
423 .class_init = heathrow_class_init,
424 .interfaces = (InterfaceInfo[]) {
425 { TYPE_FW_PATH_PROVIDER },
430 static void ppc_heathrow_register_types(void)
432 type_register_static(&ppc_heathrow_machine_info);
435 type_init(ppc_heathrow_register_types);