2 * Emulation of the ibm,plb-pcix PCI controller
3 * This is found in some 440 SoCs e.g. the 460EX.
5 * Copyright (c) 2016-2018 BALATON Zoltan
7 * Derived from ppc4xx_pci.c and pci-host/ppce500.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, version 2, as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
25 #include "qemu/module.h"
27 #include "hw/ppc/ppc.h"
28 #include "hw/ppc/ppc4xx.h"
29 #include "hw/pci/pci_device.h"
30 #include "hw/pci/pci_host.h"
32 #include "qom/object.h"
47 #define TYPE_PPC440_PCIX_HOST_BRIDGE "ppc440-pcix-host"
48 OBJECT_DECLARE_SIMPLE_TYPE(PPC440PCIXState, PPC440_PCIX_HOST_BRIDGE)
50 #define PPC440_PCIX_NR_POMS 3
51 #define PPC440_PCIX_NR_PIMS 3
53 struct PPC440PCIXState {
54 PCIHostState parent_obj;
57 struct PLBOutMap pom[PPC440_PCIX_NR_POMS];
58 struct PLBInMap pim[PPC440_PCIX_NR_PIMS];
64 MemoryRegion container;
69 #define PPC440_REG_BASE 0x80000
70 #define PPC440_REG_SIZE 0xff
72 #define PCIC0_CFGADDR 0x0
73 #define PCIC0_CFGDATA 0x4
75 #define PCIX0_POM0LAL 0x68
76 #define PCIX0_POM0LAH 0x6c
77 #define PCIX0_POM0SA 0x70
78 #define PCIX0_POM0PCIAL 0x74
79 #define PCIX0_POM0PCIAH 0x78
80 #define PCIX0_POM1LAL 0x7c
81 #define PCIX0_POM1LAH 0x80
82 #define PCIX0_POM1SA 0x84
83 #define PCIX0_POM1PCIAL 0x88
84 #define PCIX0_POM1PCIAH 0x8c
85 #define PCIX0_POM2SA 0x90
87 #define PCIX0_PIM0SAL 0x98
88 #define PCIX0_PIM0LAL 0x9c
89 #define PCIX0_PIM0LAH 0xa0
90 #define PCIX0_PIM1SA 0xa4
91 #define PCIX0_PIM1LAL 0xa8
92 #define PCIX0_PIM1LAH 0xac
93 #define PCIX0_PIM2SAL 0xb0
94 #define PCIX0_PIM2LAL 0xb4
95 #define PCIX0_PIM2LAH 0xb8
96 #define PCIX0_PIM0SAH 0xf8
97 #define PCIX0_PIM2SAH 0xfc
99 #define PCIX0_STS 0xe0
101 #define PCI_ALL_SIZE (PPC440_REG_BASE + PPC440_REG_SIZE)
103 static void ppc440_pcix_clear_region(MemoryRegion *parent,
106 if (memory_region_is_mapped(mem)) {
107 memory_region_del_subregion(parent, mem);
108 object_unparent(OBJECT(mem));
113 static void ppc440_pcix_update_pim(PPC440PCIXState *s, int idx)
115 MemoryRegion *mem = &s->pim[idx].mr;
119 /* Before we modify anything, unmap and destroy the region */
120 ppc440_pcix_clear_region(&s->bm, mem);
122 if (!(s->pim[idx].sa & 1)) {
123 /* Not enabled, nothing to do */
127 name = g_strdup_printf("PCI Inbound Window %d", idx);
128 size = ~(s->pim[idx].sa & ~7ULL) + 1;
129 memory_region_init_alias(mem, OBJECT(s), name, get_system_memory(),
130 s->pim[idx].la, size);
131 memory_region_add_subregion_overlap(&s->bm, 0, mem, -1);
134 trace_ppc440_pcix_update_pim(idx, size, s->pim[idx].la);
138 static void ppc440_pcix_update_pom(PPC440PCIXState *s, int idx)
140 MemoryRegion *mem = &s->pom[idx].mr;
141 MemoryRegion *address_space_mem = get_system_memory();
145 /* Before we modify anything, unmap and destroy the region */
146 ppc440_pcix_clear_region(address_space_mem, mem);
148 if (!(s->pom[idx].sa & 1)) {
149 /* Not enabled, nothing to do */
153 name = g_strdup_printf("PCI Outbound Window %d", idx);
154 size = ~(s->pom[idx].sa & 0xfffffffe) + 1;
158 memory_region_init_alias(mem, OBJECT(s), name, &s->busmem,
159 s->pom[idx].pcia, size);
160 memory_region_add_subregion(address_space_mem, s->pom[idx].la, mem);
163 trace_ppc440_pcix_update_pom(idx, size, s->pom[idx].la, s->pom[idx].pcia);
166 static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr,
167 uint64_t val, unsigned size)
169 struct PPC440PCIXState *s = opaque;
171 trace_ppc440_pcix_reg_write(addr, val, size);
173 case PCI_VENDOR_ID ... PCI_MAX_LAT:
174 stl_le_p(s->dev->config + addr, val);
178 s->pom[0].la &= 0xffffffff00000000ULL;
180 ppc440_pcix_update_pom(s, 0);
183 s->pom[0].la &= 0xffffffffULL;
184 s->pom[0].la |= val << 32;
185 ppc440_pcix_update_pom(s, 0);
189 ppc440_pcix_update_pom(s, 0);
191 case PCIX0_POM0PCIAL:
192 s->pom[0].pcia &= 0xffffffff00000000ULL;
193 s->pom[0].pcia |= val;
194 ppc440_pcix_update_pom(s, 0);
196 case PCIX0_POM0PCIAH:
197 s->pom[0].pcia &= 0xffffffffULL;
198 s->pom[0].pcia |= val << 32;
199 ppc440_pcix_update_pom(s, 0);
202 s->pom[1].la &= 0xffffffff00000000ULL;
204 ppc440_pcix_update_pom(s, 1);
207 s->pom[1].la &= 0xffffffffULL;
208 s->pom[1].la |= val << 32;
209 ppc440_pcix_update_pom(s, 1);
213 ppc440_pcix_update_pom(s, 1);
215 case PCIX0_POM1PCIAL:
216 s->pom[1].pcia &= 0xffffffff00000000ULL;
217 s->pom[1].pcia |= val;
218 ppc440_pcix_update_pom(s, 1);
220 case PCIX0_POM1PCIAH:
221 s->pom[1].pcia &= 0xffffffffULL;
222 s->pom[1].pcia |= val << 32;
223 ppc440_pcix_update_pom(s, 1);
230 s->pim[0].sa &= 0xffffffff00000000ULL;
232 ppc440_pcix_update_pim(s, 0);
235 s->pim[0].la &= 0xffffffff00000000ULL;
237 ppc440_pcix_update_pim(s, 0);
240 s->pim[0].la &= 0xffffffffULL;
241 s->pim[0].la |= val << 32;
242 ppc440_pcix_update_pim(s, 0);
246 ppc440_pcix_update_pim(s, 1);
249 s->pim[1].la &= 0xffffffff00000000ULL;
251 ppc440_pcix_update_pim(s, 1);
254 s->pim[1].la &= 0xffffffffULL;
255 s->pim[1].la |= val << 32;
256 ppc440_pcix_update_pim(s, 1);
259 s->pim[2].sa &= 0xffffffff00000000ULL;
261 ppc440_pcix_update_pim(s, 2);
264 s->pim[2].la &= 0xffffffff00000000ULL;
266 ppc440_pcix_update_pim(s, 2);
269 s->pim[2].la &= 0xffffffffULL;
270 s->pim[2].la |= val << 32;
271 ppc440_pcix_update_pim(s, 2);
279 s->pim[0].sa &= 0xffffffffULL;
280 s->pim[0].sa |= val << 32;
281 ppc440_pcix_update_pim(s, 0);
284 s->pim[2].sa &= 0xffffffffULL;
285 s->pim[2].sa |= val << 32;
286 ppc440_pcix_update_pim(s, 2);
290 qemu_log_mask(LOG_UNIMP,
291 "%s: unhandled PCI internal register 0x%"HWADDR_PRIx"\n",
297 static uint64_t ppc440_pcix_reg_read4(void *opaque, hwaddr addr,
300 struct PPC440PCIXState *s = opaque;
304 case PCI_VENDOR_ID ... PCI_MAX_LAT:
305 val = ldl_le_p(s->dev->config + addr);
312 val = s->pom[0].la >> 32;
317 case PCIX0_POM0PCIAL:
318 val = s->pom[0].pcia;
320 case PCIX0_POM0PCIAH:
321 val = s->pom[0].pcia >> 32;
327 val = s->pom[1].la >> 32;
332 case PCIX0_POM1PCIAL:
333 val = s->pom[1].pcia;
335 case PCIX0_POM1PCIAH:
336 val = s->pom[1].pcia >> 32;
349 val = s->pim[0].la >> 32;
358 val = s->pim[1].la >> 32;
367 val = s->pim[2].la >> 32;
375 val = s->pim[0].sa >> 32;
378 val = s->pim[2].sa >> 32;
382 qemu_log_mask(LOG_UNIMP,
383 "%s: invalid PCI internal register 0x%" HWADDR_PRIx "\n",
388 trace_ppc440_pcix_reg_read(addr, val);
392 static const MemoryRegionOps pci_reg_ops = {
393 .read = ppc440_pcix_reg_read4,
394 .write = ppc440_pcix_reg_write4,
395 .endianness = DEVICE_LITTLE_ENDIAN,
398 static void ppc440_pcix_reset(DeviceState *dev)
400 struct PPC440PCIXState *s = PPC440_PCIX_HOST_BRIDGE(dev);
403 for (i = 0; i < PPC440_PCIX_NR_POMS; i++) {
404 ppc440_pcix_clear_region(get_system_memory(), &s->pom[i].mr);
406 for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
407 ppc440_pcix_clear_region(&s->bm, &s->pim[i].mr);
409 memset(s->pom, 0, sizeof(s->pom));
410 memset(s->pim, 0, sizeof(s->pim));
411 for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
412 s->pim[i].sa = 0xffffffff00000000ULL;
418 * All four IRQ[ABCD] pins from all slots are tied to a single board
419 * IRQ, so our mapping function here maps everything to IRQ 0.
420 * The code in pci_change_irq_level() tracks the number of times
421 * the mapped IRQ is asserted and deasserted, so if multiple devices
422 * assert an IRQ at the same time the behaviour is correct.
424 * This may need further refactoring for boards that use multiple IRQ lines.
426 static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int irq_num)
428 trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, 0);
432 static void ppc440_pcix_set_irq(void *opaque, int irq_num, int level)
434 qemu_irq *pci_irq = opaque;
436 trace_ppc440_pcix_set_irq(irq_num);
438 error_report("%s: PCI irq %d", __func__, irq_num);
441 qemu_set_irq(*pci_irq, level);
444 static AddressSpace *ppc440_pcix_set_iommu(PCIBus *b, void *opaque, int devfn)
446 PPC440PCIXState *s = opaque;
452 * Some guests on sam460ex write all kinds of garbage here such as
453 * missing enable bit and low bits set and still expect this to work
454 * (apparently it does on real hardware because these boot there) so
455 * we have to override these ops here and fix it up
457 static void pci_host_config_write(void *opaque, hwaddr addr,
458 uint64_t val, unsigned len)
460 PCIHostState *s = opaque;
462 if (addr != 0 || len != 4) {
465 s->config_reg = (val & 0xfffffffcULL) | (1UL << 31);
468 static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
471 PCIHostState *s = opaque;
472 uint32_t val = s->config_reg;
477 const MemoryRegionOps ppc440_pcix_host_conf_ops = {
478 .read = pci_host_config_read,
479 .write = pci_host_config_write,
480 .endianness = DEVICE_LITTLE_ENDIAN,
483 static void ppc440_pcix_realize(DeviceState *dev, Error **errp)
485 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
489 h = PCI_HOST_BRIDGE(dev);
490 s = PPC440_PCIX_HOST_BRIDGE(dev);
492 sysbus_init_irq(sbd, &s->irq);
493 memory_region_init(&s->busmem, OBJECT(dev), "pci bus memory", UINT64_MAX);
494 h->bus = pci_register_root_bus(dev, NULL, ppc440_pcix_set_irq,
495 ppc440_pcix_map_irq, &s->irq, &s->busmem,
496 get_system_io(), PCI_DEVFN(0, 0), 1, TYPE_PCI_BUS);
498 s->dev = pci_create_simple(h->bus, PCI_DEVFN(0, 0), "ppc4xx-host-bridge");
500 memory_region_init(&s->bm, OBJECT(s), "bm-ppc440-pcix", UINT64_MAX);
501 memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
502 address_space_init(&s->bm_as, &s->bm, "pci-bm");
503 pci_setup_iommu(h->bus, ppc440_pcix_set_iommu, s);
505 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
506 memory_region_init_io(&h->conf_mem, OBJECT(s), &ppc440_pcix_host_conf_ops,
507 h, "pci-conf-idx", 4);
508 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops,
509 h, "pci-conf-data", 4);
510 memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
511 "pci.reg", PPC440_REG_SIZE);
512 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
513 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
514 memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->iomem);
515 sysbus_init_mmio(sbd, &s->container);
518 static void ppc440_pcix_class_init(ObjectClass *klass, void *data)
520 DeviceClass *dc = DEVICE_CLASS(klass);
522 dc->realize = ppc440_pcix_realize;
523 dc->reset = ppc440_pcix_reset;
526 static const TypeInfo ppc440_pcix_info = {
527 .name = TYPE_PPC440_PCIX_HOST_BRIDGE,
528 .parent = TYPE_PCI_HOST_BRIDGE,
529 .instance_size = sizeof(PPC440PCIXState),
530 .class_init = ppc440_pcix_class_init,
533 static void ppc440_pcix_register_types(void)
535 type_register_static(&ppc440_pcix_info);
538 type_init(ppc440_pcix_register_types)