2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
14 * Copyright IBM Corp. 2008
16 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
20 * This file implements emulation of the 32-bit PCI controller found in some
21 * 4xx SoCs, such as the 440EP.
24 #include "qemu/osdep.h"
27 #include "hw/ppc/ppc.h"
28 #include "hw/ppc/ppc4xx.h"
29 #include "migration/vmstate.h"
30 #include "qemu/module.h"
31 #include "sysemu/reset.h"
32 #include "hw/pci/pci_device.h"
33 #include "hw/pci/pci_host.h"
35 #include "qom/object.h"
49 OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST)
51 #define PPC4xx_PCI_NR_PMMS 3
52 #define PPC4xx_PCI_NR_PTMS 2
54 #define PPC4xx_PCI_NUM_DEVS 5
56 struct PPC4xxPCIState {
57 PCIHostState parent_obj;
59 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
60 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
61 qemu_irq irq[PPC4xx_PCI_NUM_DEVS];
63 MemoryRegion container;
67 #define PCIC0_CFGADDR 0x0
68 #define PCIC0_CFGDATA 0x4
71 * PLB Memory Map (PMM) registers specify which PLB addresses are translated to
74 #define PCIL0_PMM0LA 0x0
75 #define PCIL0_PMM0MA 0x4
76 #define PCIL0_PMM0PCILA 0x8
77 #define PCIL0_PMM0PCIHA 0xc
78 #define PCIL0_PMM1LA 0x10
79 #define PCIL0_PMM1MA 0x14
80 #define PCIL0_PMM1PCILA 0x18
81 #define PCIL0_PMM1PCIHA 0x1c
82 #define PCIL0_PMM2LA 0x20
83 #define PCIL0_PMM2MA 0x24
84 #define PCIL0_PMM2PCILA 0x28
85 #define PCIL0_PMM2PCIHA 0x2c
88 * PCI Target Map (PTM) registers specify which PCI addresses are translated to
91 #define PCIL0_PTM1MS 0x30
92 #define PCIL0_PTM1LA 0x34
93 #define PCIL0_PTM2MS 0x38
94 #define PCIL0_PTM2LA 0x3c
95 #define PCI_REG_BASE 0x800000
96 #define PCI_REG_SIZE 0x40
98 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
100 static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
101 uint64_t value, unsigned size)
103 struct PPC4xxPCIState *pci = opaque;
106 * We ignore all target attempts at PCI configuration, effectively
107 * assuming a bidirectional 1:1 mapping of PLB and PCI space.
111 pci->pmm[0].la = value;
114 pci->pmm[0].ma = value;
116 case PCIL0_PMM0PCIHA:
117 pci->pmm[0].pciha = value;
119 case PCIL0_PMM0PCILA:
120 pci->pmm[0].pcila = value;
124 pci->pmm[1].la = value;
127 pci->pmm[1].ma = value;
129 case PCIL0_PMM1PCIHA:
130 pci->pmm[1].pciha = value;
132 case PCIL0_PMM1PCILA:
133 pci->pmm[1].pcila = value;
137 pci->pmm[2].la = value;
140 pci->pmm[2].ma = value;
142 case PCIL0_PMM2PCIHA:
143 pci->pmm[2].pciha = value;
145 case PCIL0_PMM2PCILA:
146 pci->pmm[2].pcila = value;
150 pci->ptm[0].ms = value;
153 pci->ptm[0].la = value;
156 pci->ptm[1].ms = value;
159 pci->ptm[1].la = value;
163 qemu_log_mask(LOG_GUEST_ERROR,
164 "%s: unhandled PCI internal register 0x%" HWADDR_PRIx "\n",
170 static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
173 struct PPC4xxPCIState *pci = opaque;
178 value = pci->pmm[0].la;
181 value = pci->pmm[0].ma;
183 case PCIL0_PMM0PCIHA:
184 value = pci->pmm[0].pciha;
186 case PCIL0_PMM0PCILA:
187 value = pci->pmm[0].pcila;
191 value = pci->pmm[1].la;
194 value = pci->pmm[1].ma;
196 case PCIL0_PMM1PCIHA:
197 value = pci->pmm[1].pciha;
199 case PCIL0_PMM1PCILA:
200 value = pci->pmm[1].pcila;
204 value = pci->pmm[2].la;
207 value = pci->pmm[2].ma;
209 case PCIL0_PMM2PCIHA:
210 value = pci->pmm[2].pciha;
212 case PCIL0_PMM2PCILA:
213 value = pci->pmm[2].pcila;
217 value = pci->ptm[0].ms;
220 value = pci->ptm[0].la;
223 value = pci->ptm[1].ms;
226 value = pci->ptm[1].la;
230 qemu_log_mask(LOG_GUEST_ERROR,
231 "%s: invalid PCI internal register 0x%" HWADDR_PRIx "\n",
239 static const MemoryRegionOps pci_reg_ops = {
240 .read = ppc4xx_pci_reg_read4,
241 .write = ppc4xx_pci_reg_write4,
242 .endianness = DEVICE_LITTLE_ENDIAN,
245 static void ppc4xx_pci_reset(void *opaque)
247 struct PPC4xxPCIState *pci = opaque;
249 memset(pci->pmm, 0, sizeof(pci->pmm));
250 memset(pci->ptm, 0, sizeof(pci->ptm));
254 * On Bamboo, all pins from each slot are tied to a single board IRQ.
255 * This may need further refactoring for other boards.
257 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
259 int slot = PCI_SLOT(pci_dev->devfn);
261 trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
263 return slot > 0 ? slot - 1 : PPC4xx_PCI_NUM_DEVS - 1;
266 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
268 qemu_irq *pci_irqs = opaque;
270 trace_ppc4xx_pci_set_irq(irq_num);
271 assert(irq_num >= 0 && irq_num < PPC4xx_PCI_NUM_DEVS);
272 qemu_set_irq(pci_irqs[irq_num], level);
275 static const VMStateDescription vmstate_pci_master_map = {
276 .name = "pci_master_map",
278 .minimum_version_id = 0,
279 .fields = (VMStateField[]) {
280 VMSTATE_UINT32(la, struct PCIMasterMap),
281 VMSTATE_UINT32(ma, struct PCIMasterMap),
282 VMSTATE_UINT32(pcila, struct PCIMasterMap),
283 VMSTATE_UINT32(pciha, struct PCIMasterMap),
284 VMSTATE_END_OF_LIST()
288 static const VMStateDescription vmstate_pci_target_map = {
289 .name = "pci_target_map",
291 .minimum_version_id = 0,
292 .fields = (VMStateField[]) {
293 VMSTATE_UINT32(ms, struct PCITargetMap),
294 VMSTATE_UINT32(la, struct PCITargetMap),
295 VMSTATE_END_OF_LIST()
299 static const VMStateDescription vmstate_ppc4xx_pci = {
300 .name = "ppc4xx_pci",
302 .minimum_version_id = 1,
303 .fields = (VMStateField[]) {
304 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
305 vmstate_pci_master_map,
306 struct PCIMasterMap),
307 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
308 vmstate_pci_target_map,
309 struct PCITargetMap),
310 VMSTATE_END_OF_LIST()
314 /* XXX Interrupt acknowledge cycles not supported. */
315 static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
317 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
323 h = PCI_HOST_BRIDGE(dev);
324 s = PPC4xx_PCI_HOST(dev);
326 for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
327 sysbus_init_irq(sbd, &s->irq[i]);
330 b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
331 ppc4xx_pci_map_irq, s->irq, get_system_memory(),
332 get_system_io(), 0, ARRAY_SIZE(s->irq),
336 pci_create_simple(b, 0, TYPE_PPC4xx_HOST_BRIDGE);
338 /* XXX split into 2 memory regions, one for config space, one for regs */
339 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
340 memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
342 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
344 memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
345 "pci.reg", PCI_REG_SIZE);
346 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
347 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
348 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
349 sysbus_init_mmio(sbd, &s->container);
350 qemu_register_reset(ppc4xx_pci_reset, s);
353 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
355 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
356 DeviceClass *dc = DEVICE_CLASS(klass);
358 dc->desc = "Host bridge";
359 k->vendor_id = PCI_VENDOR_ID_IBM;
360 k->device_id = PCI_DEVICE_ID_IBM_440GX;
361 k->class_id = PCI_CLASS_BRIDGE_OTHER;
363 * PCI-facing part of the host bridge, not usable without the
364 * host-facing part, which can't be device_add'ed, yet.
366 dc->user_creatable = false;
369 static const TypeInfo ppc4xx_host_bridge_info = {
370 .name = TYPE_PPC4xx_HOST_BRIDGE,
371 .parent = TYPE_PCI_DEVICE,
372 .instance_size = sizeof(PCIDevice),
373 .class_init = ppc4xx_host_bridge_class_init,
374 .interfaces = (InterfaceInfo[]) {
375 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
380 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
382 DeviceClass *dc = DEVICE_CLASS(klass);
384 dc->realize = ppc4xx_pcihost_realize;
385 dc->vmsd = &vmstate_ppc4xx_pci;
388 static const TypeInfo ppc4xx_pcihost_info = {
389 .name = TYPE_PPC4xx_PCI_HOST,
390 .parent = TYPE_PCI_HOST_BRIDGE,
391 .instance_size = sizeof(PPC4xxPCIState),
392 .class_init = ppc4xx_pcihost_class_init,
395 static void ppc4xx_pci_register_types(void)
397 type_register_static(&ppc4xx_pcihost_info);
398 type_register_static(&ppc4xx_host_bridge_info);
401 type_init(ppc4xx_pci_register_types)