2 * QEMU PowerPC 4xx embedded processors SDRAM controller emulation
4 * DDR SDRAM controller:
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * DDR2 SDRAM controller:
26 * Copyright (c) 2012 François Revol
27 * Copyright (c) 2016-2019 BALATON Zoltan
29 * This work is licensed under the GNU GPL license version 2 or later.
32 #include "qemu/osdep.h"
33 #include "qemu/units.h"
34 #include "qapi/error.h"
36 #include "qemu/error-report.h"
37 #include "exec/address-spaces.h" /* get_system_memory() */
39 #include "hw/qdev-properties.h"
40 #include "hw/ppc/ppc4xx.h"
43 /*****************************************************************************/
44 /* Shared functions */
47 * Split RAM between SDRAM banks.
49 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
50 * and must be 0-terminated.
52 * The 4xx SDRAM controller supports a small number of banks, and each bank
53 * must be one of a small set of sizes. The number of banks and the supported
54 * sizes varies by SoC.
56 static bool ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
57 Ppc4xxSdramBank ram_banks[],
58 const ram_addr_t sdram_bank_sizes[],
62 ram_addr_t size_left = memory_region_size(ram);
68 for (i = 0; i < nr_banks; i++) {
69 for (j = 0; sdram_bank_sizes[j] != 0; j++) {
70 bank_size = sdram_bank_sizes[j];
71 if (bank_size <= size_left) {
74 ram_banks[i].base = base;
75 ram_banks[i].size = bank_size;
77 size_left -= bank_size;
78 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
79 memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
80 ram_banks[i].base, ram_banks[i].size);
85 /* No need to use the remaining banks. */
91 ram_addr_t used_size = memory_region_size(ram) - size_left;
92 GString *s = g_string_new(NULL);
94 for (i = 0; sdram_bank_sizes[i]; i++) {
95 g_string_append_printf(s, "%" PRIi64 "%s",
96 sdram_bank_sizes[i] / MiB,
97 sdram_bank_sizes[i + 1] ? ", " : "");
99 error_setg(errp, "Invalid SDRAM banks");
100 error_append_hint(errp, "at most %d bank%s of %s MiB each supported\n",
101 nr_banks, nr_banks == 1 ? "" : "s", s->str);
102 error_append_hint(errp, "Possible valid RAM size: %" PRIi64 " MiB\n",
103 used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
105 g_string_free(s, true);
111 static void sdram_bank_map(Ppc4xxSdramBank *bank)
113 trace_ppc4xx_sdram_map(bank->base, bank->size);
114 memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
115 memory_region_add_subregion(&bank->container, 0, &bank->ram);
116 memory_region_add_subregion(get_system_memory(), bank->base,
120 static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
122 trace_ppc4xx_sdram_unmap(bank->base, bank->size);
123 memory_region_del_subregion(get_system_memory(), &bank->container);
124 memory_region_del_subregion(&bank->container, &bank->ram);
125 object_unparent(OBJECT(&bank->container));
128 static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr,
129 hwaddr base, hwaddr size, int enabled)
131 if (memory_region_is_mapped(&bank->container)) {
132 sdram_bank_unmap(bank);
137 if (enabled && (bcr & 1)) {
138 sdram_bank_map(bank);
143 SDRAM0_CFGADDR = 0x010,
144 SDRAM0_CFGDATA = 0x011,
147 /*****************************************************************************/
148 /* DDR SDRAM controller */
149 #define SDRAM_DDR_BCR_MASK 0xFFDEE001
151 static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
178 qemu_log_mask(LOG_GUEST_ERROR,
179 "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
183 bcr |= ram_base & 0xFF800000;
189 static inline hwaddr sdram_ddr_base(uint32_t bcr)
191 return bcr & 0xFF800000;
194 static hwaddr sdram_ddr_size(uint32_t bcr)
196 int sh = (bcr >> 17) & 0x7;
202 return (4 * MiB) << sh;
205 static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
207 Ppc4xxSdramDdrState *s = opaque;
216 case 0x00: /* SDRAM_BESR0 */
219 case 0x08: /* SDRAM_BESR1 */
222 case 0x10: /* SDRAM_BEAR */
225 case 0x20: /* SDRAM_CFG */
228 case 0x24: /* SDRAM_STATUS */
231 case 0x30: /* SDRAM_RTR */
234 case 0x34: /* SDRAM_PMIT */
237 case 0x40: /* SDRAM_B0CR */
238 ret = s->bank[0].bcr;
240 case 0x44: /* SDRAM_B1CR */
241 ret = s->bank[1].bcr;
243 case 0x48: /* SDRAM_B2CR */
244 ret = s->bank[2].bcr;
246 case 0x4C: /* SDRAM_B3CR */
247 ret = s->bank[3].bcr;
249 case 0x80: /* SDRAM_TR */
252 case 0x94: /* SDRAM_ECCCFG */
255 case 0x98: /* SDRAM_ECCESR */
264 /* Avoid gcc warning */
272 static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
274 Ppc4xxSdramDdrState *s = opaque;
283 case 0x00: /* SDRAM_BESR0 */
286 case 0x08: /* SDRAM_BESR1 */
289 case 0x10: /* SDRAM_BEAR */
292 case 0x20: /* SDRAM_CFG */
294 if (!(s->cfg & 0x80000000) && (val & 0x80000000)) {
295 trace_ppc4xx_sdram_enable("enable");
296 /* validate all RAM mappings */
297 for (i = 0; i < s->nbanks; i++) {
298 if (s->bank[i].size) {
299 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
300 s->bank[i].base, s->bank[i].size,
304 s->status &= ~0x80000000;
305 } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) {
306 trace_ppc4xx_sdram_enable("disable");
307 /* invalidate all RAM mappings */
308 for (i = 0; i < s->nbanks; i++) {
309 if (s->bank[i].size) {
310 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
311 s->bank[i].base, s->bank[i].size,
315 s->status |= 0x80000000;
317 if (!(s->cfg & 0x40000000) && (val & 0x40000000)) {
318 s->status |= 0x40000000;
319 } else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) {
320 s->status &= ~0x40000000;
324 case 0x24: /* SDRAM_STATUS */
325 /* Read-only register */
327 case 0x30: /* SDRAM_RTR */
328 s->rtr = val & 0x3FF80000;
330 case 0x34: /* SDRAM_PMIT */
331 s->pmit = (val & 0xF8000000) | 0x07C00000;
333 case 0x40: /* SDRAM_B0CR */
334 case 0x44: /* SDRAM_B1CR */
335 case 0x48: /* SDRAM_B2CR */
336 case 0x4C: /* SDRAM_B3CR */
337 i = (s->addr - 0x40) / 4;
338 val &= SDRAM_DDR_BCR_MASK;
339 if (s->bank[i].size) {
340 sdram_bank_set_bcr(&s->bank[i], val,
341 sdram_ddr_base(val), sdram_ddr_size(val),
342 s->cfg & 0x80000000);
345 case 0x80: /* SDRAM_TR */
346 s->tr = val & 0x018FC01F;
348 case 0x94: /* SDRAM_ECCCFG */
349 s->ecccfg = val & 0x00F00000;
351 case 0x98: /* SDRAM_ECCESR */
353 if (s->eccesr == 0 && val != 0) {
354 qemu_irq_raise(s->irq);
355 } else if (s->eccesr != 0 && val == 0) {
356 qemu_irq_lower(s->irq);
367 static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
369 Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
373 s->besr0 = 0; /* No error */
374 s->besr1 = 0; /* No error */
376 s->ecccfg = 0; /* No ECC */
377 s->eccesr = 0; /* No error */
378 s->pmit = 0x07C00000;
381 /* We pre-initialize RAM banks */
386 static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
388 Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
389 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
390 const ram_addr_t valid_bank_sizes[] = {
391 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
395 if (s->nbanks < 1 || s->nbanks > 4) {
396 error_setg(errp, "Invalid number of RAM banks");
400 error_setg(errp, "Missing dram memory region");
403 if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
404 valid_bank_sizes, errp)) {
407 for (i = 0; i < s->nbanks; i++) {
408 if (s->bank[i].size) {
409 s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);
410 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
411 s->bank[i].base, s->bank[i].size, 0);
413 sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
415 trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr),
416 sdram_ddr_size(s->bank[i].bcr),
420 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
422 ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
423 s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
424 ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
425 s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
428 static Property ppc4xx_sdram_ddr_props[] = {
429 DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
431 DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
432 DEFINE_PROP_END_OF_LIST(),
435 static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
437 DeviceClass *dc = DEVICE_CLASS(oc);
439 dc->realize = ppc4xx_sdram_ddr_realize;
440 dc->reset = ppc4xx_sdram_ddr_reset;
441 /* Reason: only works as function of a ppc4xx SoC */
442 dc->user_creatable = false;
443 device_class_set_props(dc, ppc4xx_sdram_ddr_props);
446 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
448 sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
449 sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
452 /*****************************************************************************/
453 /* DDR2 SDRAM controller */
454 #define SDRAM_DDR2_BCR_MASK 0xffe0ffc1
461 SDRAM_CONF1HB = 0x45,
462 SDRAM_PLBADDULL = 0x4a,
463 SDRAM_CONF1LL = 0x4b,
464 SDRAM_CONFPATHB = 0x4f,
465 SDRAM_PLBADDUHB = 0x50,
468 static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
504 error_report("invalid RAM size " HWADDR_FMT_plx, ram_size);
507 bcr |= ram_base >> 2 & 0xffe00000;
513 static inline hwaddr sdram_ddr2_base(uint32_t bcr)
515 return (bcr & 0xffe00000) << 2;
518 static hwaddr sdram_ddr2_size(uint32_t bcr)
522 sh = 1024 - ((bcr >> 6) & 0x3ff);
526 static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
528 Ppc4xxSdramDdr2State *s = opaque;
536 if (s->bank[dcrn - SDRAM_R0BAS].size) {
537 ret = sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base,
538 s->bank[dcrn - SDRAM_R0BAS].size);
543 case SDRAM_CONFPATHB:
544 case SDRAM_PLBADDULL:
545 case SDRAM_PLBADDUHB:
552 case 0x14: /* SDRAM_MCSTAT (405EX) */
556 case 0x21: /* SDRAM_MCOPT2 */
559 case 0x40: /* SDRAM_MB0CF */
562 case 0x7A: /* SDRAM_DLCR */
565 case 0xE1: /* SDR0_DDR0 */
566 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
579 #define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
581 static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
583 Ppc4xxSdramDdr2State *s = opaque;
593 case SDRAM_CONFPATHB:
594 case SDRAM_PLBADDULL:
595 case SDRAM_PLBADDUHB:
602 case 0x00: /* B0CR */
604 case 0x21: /* SDRAM_MCOPT2 */
605 if (!(s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
606 (val & SDRAM_DDR2_MCOPT2_DCEN)) {
607 trace_ppc4xx_sdram_enable("enable");
608 /* validate all RAM mappings */
609 for (i = 0; i < s->nbanks; i++) {
610 if (s->bank[i].size) {
611 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
612 s->bank[i].base, s->bank[i].size,
616 s->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
617 } else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
618 !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
619 trace_ppc4xx_sdram_enable("disable");
620 /* invalidate all RAM mappings */
621 for (i = 0; i < s->nbanks; i++) {
622 if (s->bank[i].size) {
623 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
624 s->bank[i].base, s->bank[i].size,
628 s->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
640 static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
642 Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
648 static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
650 Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
651 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
653 * SoC also has 4 GiB but that causes problem with 32 bit
654 * builds (4*GiB overflows the 32 bit ram_addr_t).
656 const ram_addr_t valid_bank_sizes[] = {
657 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB,
658 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
662 if (s->nbanks < 1 || s->nbanks > 4) {
663 error_setg(errp, "Invalid number of RAM banks");
667 error_setg(errp, "Missing dram memory region");
670 if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
671 valid_bank_sizes, errp)) {
674 for (i = 0; i < s->nbanks; i++) {
675 if (s->bank[i].size) {
676 s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);
677 s->bank[i].bcr &= SDRAM_DDR2_BCR_MASK;
678 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
679 s->bank[i].base, s->bank[i].size, 0);
681 sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
683 trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr),
684 sdram_ddr2_size(s->bank[i].bcr),
688 ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
689 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
690 ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
691 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
693 ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
694 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
695 ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
696 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
697 ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
698 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
699 ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
700 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
701 ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
702 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
703 ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
704 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
705 ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
706 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
707 ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
708 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
709 ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
710 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
713 static Property ppc4xx_sdram_ddr2_props[] = {
714 DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
716 DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
717 DEFINE_PROP_END_OF_LIST(),
720 static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
722 DeviceClass *dc = DEVICE_CLASS(oc);
724 dc->realize = ppc4xx_sdram_ddr2_realize;
725 dc->reset = ppc4xx_sdram_ddr2_reset;
726 /* Reason: only works as function of a ppc4xx SoC */
727 dc->user_creatable = false;
728 device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
731 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
733 sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
734 sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
737 static const TypeInfo ppc4xx_sdram_types[] = {
739 .name = TYPE_PPC4xx_SDRAM_DDR,
740 .parent = TYPE_PPC4xx_DCR_DEVICE,
741 .instance_size = sizeof(Ppc4xxSdramDdrState),
742 .class_init = ppc4xx_sdram_ddr_class_init,
744 .name = TYPE_PPC4xx_SDRAM_DDR2,
745 .parent = TYPE_PPC4xx_DCR_DEVICE,
746 .instance_size = sizeof(Ppc4xxSdramDdr2State),
747 .class_init = ppc4xx_sdram_ddr2_class_init,
751 DEFINE_TYPES(ppc4xx_sdram_types)