hw/riscv/sifive_u.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017 SiFive, Inc.
   6  * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
   7  *
   8  * Provides a board compatible with the SiFive Freedom U SDK:
   9  *
  10  * 0) UART
  11  * 1) CLINT (Core Level Interruptor)
  12  * 2) PLIC (Platform Level Interrupt Controller)
  13  * 3) PRCI (Power, Reset, Clock, Interrupt)
  14  * 4) GPIO (General Purpose Input/Output Controller)
  15  * 5) OTP (One-Time Programmable) memory with stored serial number
  16  * 6) GEM (Gigabit Ethernet Controller) and management block
  17  * 7) DMA (Direct Memory Access Controller)
  18  * 8) SPI0 connected to an SPI flash
  19  * 9) SPI2 connected to an SD card
  20  * 10) PWM0 and PWM1
  21  *
  22  * This board currently generates devicetree dynamically that indicates at least
  23  * two harts and up to five harts.
  24  *
  25  * This program is free software; you can redistribute it and/or modify it
  26  * under the terms and conditions of the GNU General Public License,
  27  * version 2 or later, as published by the Free Software Foundation.
  28  *
  29  * This program is distributed in the hope it will be useful, but WITHOUT
  30  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  31  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  32  * more details.
  33  *
  34  * You should have received a copy of the GNU General Public License along with
  35  * this program.  If not, see <http://www.gnu.org/licenses/>.
  36  */
  37
  38 #include "qemu/osdep.h"
  39 #include "qemu/error-report.h"
  40 #include "qapi/error.h"
  41 #include "qapi/visitor.h"
  42 #include "hw/boards.h"
  43 #include "hw/irq.h"
  44 #include "hw/loader.h"
  45 #include "hw/sysbus.h"
  46 #include "hw/char/serial.h"
  47 #include "hw/cpu/cluster.h"
  48 #include "hw/misc/unimp.h"
  49 #include "hw/sd/sd.h"
  50 #include "hw/ssi/ssi.h"
  51 #include "target/riscv/cpu.h"
  52 #include "hw/riscv/riscv_hart.h"
  53 #include "hw/riscv/sifive_u.h"
  54 #include "hw/riscv/boot.h"
  55 #include "hw/char/sifive_uart.h"
  56 #include "hw/intc/riscv_aclint.h"
  57 #include "hw/intc/sifive_plic.h"
  58 #include "chardev/char.h"
  59 #include "net/eth.h"
  60 #include "sysemu/device_tree.h"
  61 #include "sysemu/runstate.h"
  62 #include "sysemu/sysemu.h"
  63
  64 #include <libfdt.h>
  65
  66 /* CLINT timebase frequency */
  67 #define CLINT_TIMEBASE_FREQ 1000000
  68
  69 static const MemMapEntry sifive_u_memmap[] = {
  70     [SIFIVE_U_DEV_DEBUG] =    {        0x0,      0x100 },
  71     [SIFIVE_U_DEV_MROM] =     {     0x1000,     0xf000 },
  72     [SIFIVE_U_DEV_CLINT] =    {  0x2000000,    0x10000 },
  73     [SIFIVE_U_DEV_L2CC] =     {  0x2010000,     0x1000 },
  74     [SIFIVE_U_DEV_PDMA] =     {  0x3000000,   0x100000 },
  75     [SIFIVE_U_DEV_L2LIM] =    {  0x8000000,  0x2000000 },
  76     [SIFIVE_U_DEV_PLIC] =     {  0xc000000,  0x4000000 },
  77     [SIFIVE_U_DEV_PRCI] =     { 0x10000000,     0x1000 },
  78     [SIFIVE_U_DEV_UART0] =    { 0x10010000,     0x1000 },
  79     [SIFIVE_U_DEV_UART1] =    { 0x10011000,     0x1000 },
  80     [SIFIVE_U_DEV_PWM0] =     { 0x10020000,     0x1000 },
  81     [SIFIVE_U_DEV_PWM1] =     { 0x10021000,     0x1000 },
  82     [SIFIVE_U_DEV_QSPI0] =    { 0x10040000,     0x1000 },
  83     [SIFIVE_U_DEV_QSPI2] =    { 0x10050000,     0x1000 },
  84     [SIFIVE_U_DEV_GPIO] =     { 0x10060000,     0x1000 },
  85     [SIFIVE_U_DEV_OTP] =      { 0x10070000,     0x1000 },
  86     [SIFIVE_U_DEV_GEM] =      { 0x10090000,     0x2000 },
  87     [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000,     0x1000 },
  88     [SIFIVE_U_DEV_DMC] =      { 0x100b0000,    0x10000 },
  89     [SIFIVE_U_DEV_FLASH0] =   { 0x20000000, 0x10000000 },
  90     [SIFIVE_U_DEV_DRAM] =     { 0x80000000,        0x0 },
  91 };
  92
  93 #define OTP_SERIAL          1
  94 #define GEM_REVISION        0x10070109
  95
  96 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
  97                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
  98 {
  99     MachineState *ms = MACHINE(qdev_get_machine());
 100     void *fdt;
 101     int cpu, fdt_size;
 102     uint32_t *cells;
 103     char *nodename;
 104     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
 105     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
 106     static const char * const ethclk_names[2] = { "pclk", "hclk" };
 107     static const char * const clint_compat[2] = {
 108         "sifive,clint0", "riscv,clint0"
 109     };
 110     static const char * const plic_compat[2] = {
 111         "sifive,plic-1.0.0", "riscv,plic0"
 112     };
 113
 114     if (ms->dtb) {
 115         fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
 116         if (!fdt) {
 117             error_report("load_device_tree() failed");
 118             exit(1);
 119         }
 120     } else {
 121         fdt = ms->fdt = create_device_tree(&fdt_size);
 122         if (!fdt) {
 123             error_report("create_device_tree() failed");
 124             exit(1);
 125         }
 126     }
 127
 128     qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
 129     qemu_fdt_setprop_string(fdt, "/", "compatible",
 130                             "sifive,hifive-unleashed-a00");
 131     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 132     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 133
 134     qemu_fdt_add_subnode(fdt, "/soc");
 135     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 136     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 137     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 138     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 139
 140     hfclk_phandle = phandle++;
 141     nodename = g_strdup_printf("/hfclk");
 142     qemu_fdt_add_subnode(fdt, nodename);
 143     qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
 144     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
 145     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 146         SIFIVE_U_HFCLK_FREQ);
 147     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 148     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 149     g_free(nodename);
 150
 151     rtcclk_phandle = phandle++;
 152     nodename = g_strdup_printf("/rtcclk");
 153     qemu_fdt_add_subnode(fdt, nodename);
 154     qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
 155     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
 156     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 157         SIFIVE_U_RTCCLK_FREQ);
 158     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 159     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 160     g_free(nodename);
 161
 162     nodename = g_strdup_printf("/memory@%lx",
 163         (long)memmap[SIFIVE_U_DEV_DRAM].base);
 164     qemu_fdt_add_subnode(fdt, nodename);
 165     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 166         memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
 167         mem_size >> 32, mem_size);
 168     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 169     g_free(nodename);
 170
 171     qemu_fdt_add_subnode(fdt, "/cpus");
 172     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 173         CLINT_TIMEBASE_FREQ);
 174     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 175     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 176
 177     for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
 178         int cpu_phandle = phandle++;
 179         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 180         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 181         char *isa;
 182         qemu_fdt_add_subnode(fdt, nodename);
 183         /* cpu 0 is the management hart that does not have mmu */
 184         if (cpu != 0) {
 185             if (is_32_bit) {
 186                 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
 187             } else {
 188                 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 189             }
 190             isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
 191         } else {
 192             isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
 193         }
 194         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 195         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 196         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 197         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 198         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 199         qemu_fdt_add_subnode(fdt, intc);
 200         qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
 201         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 202         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 203         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 204         g_free(isa);
 205         g_free(intc);
 206         g_free(nodename);
 207     }
 208
 209     cells =  g_new0(uint32_t, ms->smp.cpus * 4);
 210     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 211         nodename =
 212             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 213         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 214         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 215         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 216         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 217         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 218         g_free(nodename);
 219     }
 220     nodename = g_strdup_printf("/soc/clint@%lx",
 221         (long)memmap[SIFIVE_U_DEV_CLINT].base);
 222     qemu_fdt_add_subnode(fdt, nodename);
 223     qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
 224         (char **)&clint_compat, ARRAY_SIZE(clint_compat));
 225     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 226         0x0, memmap[SIFIVE_U_DEV_CLINT].base,
 227         0x0, memmap[SIFIVE_U_DEV_CLINT].size);
 228     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 229         cells, ms->smp.cpus * sizeof(uint32_t) * 4);
 230     g_free(cells);
 231     g_free(nodename);
 232
 233     nodename = g_strdup_printf("/soc/otp@%lx",
 234         (long)memmap[SIFIVE_U_DEV_OTP].base);
 235     qemu_fdt_add_subnode(fdt, nodename);
 236     qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
 237     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 238         0x0, memmap[SIFIVE_U_DEV_OTP].base,
 239         0x0, memmap[SIFIVE_U_DEV_OTP].size);
 240     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 241         "sifive,fu540-c000-otp");
 242     g_free(nodename);
 243
 244     prci_phandle = phandle++;
 245     nodename = g_strdup_printf("/soc/clock-controller@%lx",
 246         (long)memmap[SIFIVE_U_DEV_PRCI].base);
 247     qemu_fdt_add_subnode(fdt, nodename);
 248     qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
 249     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
 250     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 251         hfclk_phandle, rtcclk_phandle);
 252     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 253         0x0, memmap[SIFIVE_U_DEV_PRCI].base,
 254         0x0, memmap[SIFIVE_U_DEV_PRCI].size);
 255     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 256         "sifive,fu540-c000-prci");
 257     g_free(nodename);
 258
 259     plic_phandle = phandle++;
 260     cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
 261     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 262         nodename =
 263             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 264         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 265         /* cpu 0 is the management hart that does not have S-mode */
 266         if (cpu == 0) {
 267             cells[0] = cpu_to_be32(intc_phandle);
 268             cells[1] = cpu_to_be32(IRQ_M_EXT);
 269         } else {
 270             cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
 271             cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
 272             cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 273             cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
 274         }
 275         g_free(nodename);
 276     }
 277     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 278         (long)memmap[SIFIVE_U_DEV_PLIC].base);
 279     qemu_fdt_add_subnode(fdt, nodename);
 280     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 281     qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
 282         (char **)&plic_compat, ARRAY_SIZE(plic_compat));
 283     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 284     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 285         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
 286     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 287         0x0, memmap[SIFIVE_U_DEV_PLIC].base,
 288         0x0, memmap[SIFIVE_U_DEV_PLIC].size);
 289     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
 290                           SIFIVE_U_PLIC_NUM_SOURCES - 1);
 291     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 292     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 293     g_free(cells);
 294     g_free(nodename);
 295
 296     gpio_phandle = phandle++;
 297     nodename = g_strdup_printf("/soc/gpio@%lx",
 298         (long)memmap[SIFIVE_U_DEV_GPIO].base);
 299     qemu_fdt_add_subnode(fdt, nodename);
 300     qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
 301     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 302         prci_phandle, PRCI_CLK_TLCLK);
 303     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
 304     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 305     qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
 306     qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
 307     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 308         0x0, memmap[SIFIVE_U_DEV_GPIO].base,
 309         0x0, memmap[SIFIVE_U_DEV_GPIO].size);
 310     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
 311         SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
 312         SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
 313         SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
 314         SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
 315         SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
 316     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 317     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
 318     g_free(nodename);
 319
 320     nodename = g_strdup_printf("/gpio-restart");
 321     qemu_fdt_add_subnode(fdt, nodename);
 322     qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
 323     qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
 324     g_free(nodename);
 325
 326     nodename = g_strdup_printf("/soc/dma@%lx",
 327         (long)memmap[SIFIVE_U_DEV_PDMA].base);
 328     qemu_fdt_add_subnode(fdt, nodename);
 329     qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
 330     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
 331         SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
 332         SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
 333         SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
 334     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 335     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 336         0x0, memmap[SIFIVE_U_DEV_PDMA].base,
 337         0x0, memmap[SIFIVE_U_DEV_PDMA].size);
 338     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 339                             "sifive,fu540-c000-pdma");
 340     g_free(nodename);
 341
 342     nodename = g_strdup_printf("/soc/cache-controller@%lx",
 343         (long)memmap[SIFIVE_U_DEV_L2CC].base);
 344     qemu_fdt_add_subnode(fdt, nodename);
 345     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 346         0x0, memmap[SIFIVE_U_DEV_L2CC].base,
 347         0x0, memmap[SIFIVE_U_DEV_L2CC].size);
 348     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
 349         SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
 350     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 351     qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
 352     qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
 353     qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
 354     qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
 355     qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
 356     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 357                             "sifive,fu540-c000-ccache");
 358     g_free(nodename);
 359
 360     nodename = g_strdup_printf("/soc/spi@%lx",
 361         (long)memmap[SIFIVE_U_DEV_QSPI2].base);
 362     qemu_fdt_add_subnode(fdt, nodename);
 363     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 364     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 365     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 366         prci_phandle, PRCI_CLK_TLCLK);
 367     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
 368     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 369     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 370         0x0, memmap[SIFIVE_U_DEV_QSPI2].base,
 371         0x0, memmap[SIFIVE_U_DEV_QSPI2].size);
 372     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
 373     g_free(nodename);
 374
 375     nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
 376         (long)memmap[SIFIVE_U_DEV_QSPI2].base);
 377     qemu_fdt_add_subnode(fdt, nodename);
 378     qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
 379     qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
 380     qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
 381     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
 382     qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
 383     g_free(nodename);
 384
 385     nodename = g_strdup_printf("/soc/spi@%lx",
 386         (long)memmap[SIFIVE_U_DEV_QSPI0].base);
 387     qemu_fdt_add_subnode(fdt, nodename);
 388     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 389     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 390     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 391         prci_phandle, PRCI_CLK_TLCLK);
 392     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
 393     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 394     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 395         0x0, memmap[SIFIVE_U_DEV_QSPI0].base,
 396         0x0, memmap[SIFIVE_U_DEV_QSPI0].size);
 397     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
 398     g_free(nodename);
 399
 400     nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
 401         (long)memmap[SIFIVE_U_DEV_QSPI0].base);
 402     qemu_fdt_add_subnode(fdt, nodename);
 403     qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
 404     qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
 405     qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
 406     qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
 407     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
 408     qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
 409     g_free(nodename);
 410
 411     phy_phandle = phandle++;
 412     nodename = g_strdup_printf("/soc/ethernet@%lx",
 413         (long)memmap[SIFIVE_U_DEV_GEM].base);
 414     qemu_fdt_add_subnode(fdt, nodename);
 415     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 416         "sifive,fu540-c000-gem");
 417     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 418         0x0, memmap[SIFIVE_U_DEV_GEM].base,
 419         0x0, memmap[SIFIVE_U_DEV_GEM].size,
 420         0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
 421         0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
 422     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 423     qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
 424     qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
 425     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 426     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 427     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 428         prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
 429     qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
 430         (char **)&ethclk_names, ARRAY_SIZE(ethclk_names));
 431     qemu_fdt_setprop(fdt, nodename, "local-mac-address",
 432         s->soc.gem.conf.macaddr.a, ETH_ALEN);
 433     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 434     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 435
 436     qemu_fdt_add_subnode(fdt, "/aliases");
 437     qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
 438
 439     g_free(nodename);
 440
 441     nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 442         (long)memmap[SIFIVE_U_DEV_GEM].base);
 443     qemu_fdt_add_subnode(fdt, nodename);
 444     qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
 445     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 446     g_free(nodename);
 447
 448     nodename = g_strdup_printf("/soc/pwm@%lx",
 449         (long)memmap[SIFIVE_U_DEV_PWM0].base);
 450     qemu_fdt_add_subnode(fdt, nodename);
 451     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
 452     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 453         0x0, memmap[SIFIVE_U_DEV_PWM0].base,
 454         0x0, memmap[SIFIVE_U_DEV_PWM0].size);
 455     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 456     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
 457                            SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
 458                            SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
 459     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 460                            prci_phandle, PRCI_CLK_TLCLK);
 461     qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
 462     g_free(nodename);
 463
 464     nodename = g_strdup_printf("/soc/pwm@%lx",
 465         (long)memmap[SIFIVE_U_DEV_PWM1].base);
 466     qemu_fdt_add_subnode(fdt, nodename);
 467     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
 468     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 469         0x0, memmap[SIFIVE_U_DEV_PWM1].base,
 470         0x0, memmap[SIFIVE_U_DEV_PWM1].size);
 471     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 472     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
 473                            SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1,
 474                            SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3);
 475     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 476                            prci_phandle, PRCI_CLK_TLCLK);
 477     qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
 478     g_free(nodename);
 479
 480     nodename = g_strdup_printf("/soc/serial@%lx",
 481         (long)memmap[SIFIVE_U_DEV_UART1].base);
 482     qemu_fdt_add_subnode(fdt, nodename);
 483     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 484     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 485         0x0, memmap[SIFIVE_U_DEV_UART1].base,
 486         0x0, memmap[SIFIVE_U_DEV_UART1].size);
 487     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 488         prci_phandle, PRCI_CLK_TLCLK);
 489     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 490     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
 491
 492     qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
 493     g_free(nodename);
 494
 495     nodename = g_strdup_printf("/soc/serial@%lx",
 496         (long)memmap[SIFIVE_U_DEV_UART0].base);
 497     qemu_fdt_add_subnode(fdt, nodename);
 498     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 499     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 500         0x0, memmap[SIFIVE_U_DEV_UART0].base,
 501         0x0, memmap[SIFIVE_U_DEV_UART0].size);
 502     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 503         prci_phandle, PRCI_CLK_TLCLK);
 504     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 505     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 506
 507     qemu_fdt_add_subnode(fdt, "/chosen");
 508     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 509     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 510
 511     g_free(nodename);
 512 }
 513
 514 static void sifive_u_machine_reset(void *opaque, int n, int level)
 515 {
 516     /* gpio pin active low triggers reset */
 517     if (!level) {
 518         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 519     }
 520 }
 521
 522 static void sifive_u_machine_init(MachineState *machine)
 523 {
 524     const MemMapEntry *memmap = sifive_u_memmap;
 525     SiFiveUState *s = RISCV_U_MACHINE(machine);
 526     MemoryRegion *system_memory = get_system_memory();
 527     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
 528     target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
 529     target_ulong firmware_end_addr, kernel_start_addr;
 530     const char *firmware_name;
 531     uint32_t start_addr_hi32 = 0x00000000;
 532     int i;
 533     uint32_t fdt_load_addr;
 534     uint64_t kernel_entry;
 535     DriveInfo *dinfo;
 536     BlockBackend *blk;
 537     DeviceState *flash_dev, *sd_dev, *card_dev;
 538     qemu_irq flash_cs, sd_cs;
 539
 540     /* Initialize SoC */
 541     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
 542     object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
 543                              &error_abort);
 544     object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
 545                              &error_abort);
 546     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
 547
 548     /* register RAM */
 549     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
 550                                 machine->ram);
 551
 552     /* register QSPI0 Flash */
 553     memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
 554                            memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
 555     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
 556                                 flash0);
 557
 558     /* register gpio-restart */
 559     qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
 560                           qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
 561
 562     /* create device tree */
 563     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 564                riscv_is_32bit(&s->soc.u_cpus));
 565
 566     if (s->start_in_flash) {
 567         /*
 568          * If start_in_flash property is given, assign s->msel to a value
 569          * that representing booting from QSPI0 memory-mapped flash.
 570          *
 571          * This also means that when both start_in_flash and msel properties
 572          * are given, start_in_flash takes the precedence over msel.
 573          *
 574          * Note this is to keep backward compatibility not to break existing
 575          * users that use start_in_flash property.
 576          */
 577         s->msel = MSEL_MEMMAP_QSPI0_FLASH;
 578     }
 579
 580     switch (s->msel) {
 581     case MSEL_MEMMAP_QSPI0_FLASH:
 582         start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
 583         break;
 584     case MSEL_L2LIM_QSPI0_FLASH:
 585     case MSEL_L2LIM_QSPI2_SD:
 586         start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
 587         break;
 588     default:
 589         start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
 590         break;
 591     }
 592
 593     firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
 594     firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
 595                                                      start_addr, NULL);
 596
 597     if (machine->kernel_filename) {
 598         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
 599                                                          firmware_end_addr);
 600
 601         kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
 602
 603         if (machine->initrd_filename) {
 604             riscv_load_initrd(machine, kernel_entry);
 605         }
 606
 607         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 608             qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
 609                                     machine->kernel_cmdline);
 610         }
 611     } else {
 612        /*
 613         * If dynamic firmware is used, it doesn't know where is the next mode
 614         * if kernel argument is not set.
 615         */
 616         kernel_entry = 0;
 617     }
 618
 619     /* Compute the fdt load address in dram */
 620     fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
 621                                    machine->ram_size, machine->fdt);
 622     if (!riscv_is_32bit(&s->soc.u_cpus)) {
 623         start_addr_hi32 = (uint64_t)start_addr >> 32;
 624     }
 625
 626     /* reset vector */
 627     uint32_t reset_vec[12] = {
 628         s->msel,                       /* MSEL pin state */
 629         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
 630         0x02c28613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
 631         0xf1402573,                    /*     csrr   a0, mhartid  */
 632         0,
 633         0,
 634         0x00028067,                    /*     jr     t0 */
 635         start_addr,                    /* start: .dword */
 636         start_addr_hi32,
 637         fdt_load_addr,                 /* fdt_laddr: .dword */
 638         0x00000000,
 639         0x00000000,
 640                                        /* fw_dyn: */
 641     };
 642     if (riscv_is_32bit(&s->soc.u_cpus)) {
 643         reset_vec[4] = 0x0202a583;     /*     lw     a1, 32(t0) */
 644         reset_vec[5] = 0x0182a283;     /*     lw     t0, 24(t0) */
 645     } else {
 646         reset_vec[4] = 0x0202b583;     /*     ld     a1, 32(t0) */
 647         reset_vec[5] = 0x0182b283;     /*     ld     t0, 24(t0) */
 648     }
 649
 650
 651     /* copy in the reset vector in little_endian byte order */
 652     for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
 653         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 654     }
 655     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 656                           memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
 657
 658     riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
 659                                  memmap[SIFIVE_U_DEV_MROM].size,
 660                                  sizeof(reset_vec), kernel_entry);
 661
 662     /* Connect an SPI flash to SPI0 */
 663     flash_dev = qdev_new("is25wp256");
 664     dinfo = drive_get(IF_MTD, 0, 0);
 665     if (dinfo) {
 666         qdev_prop_set_drive_err(flash_dev, "drive",
 667                                 blk_by_legacy_dinfo(dinfo),
 668                                 &error_fatal);
 669     }
 670     qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
 671
 672     flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 673     sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
 674
 675     /* Connect an SD card to SPI2 */
 676     sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
 677
 678     sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
 679     sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
 680
 681     dinfo = drive_get(IF_SD, 0, 0);
 682     blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
 683     card_dev = qdev_new(TYPE_SD_CARD);
 684     qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal);
 685     qdev_prop_set_bit(card_dev, "spi", true);
 686     qdev_realize_and_unref(card_dev,
 687                            qdev_get_child_bus(sd_dev, "sd-bus"),
 688                            &error_fatal);
 689 }
 690
 691 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
 692 {
 693     SiFiveUState *s = RISCV_U_MACHINE(obj);
 694
 695     return s->start_in_flash;
 696 }
 697
 698 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
 699 {
 700     SiFiveUState *s = RISCV_U_MACHINE(obj);
 701
 702     s->start_in_flash = value;
 703 }
 704
 705 static void sifive_u_machine_instance_init(Object *obj)
 706 {
 707     SiFiveUState *s = RISCV_U_MACHINE(obj);
 708
 709     s->start_in_flash = false;
 710     s->msel = 0;
 711     object_property_add_uint32_ptr(obj, "msel", &s->msel,
 712                                    OBJ_PROP_FLAG_READWRITE);
 713     object_property_set_description(obj, "msel",
 714                                     "Mode Select (MSEL[3:0]) pin state");
 715
 716     s->serial = OTP_SERIAL;
 717     object_property_add_uint32_ptr(obj, "serial", &s->serial,
 718                                    OBJ_PROP_FLAG_READWRITE);
 719     object_property_set_description(obj, "serial", "Board serial number");
 720 }
 721
 722 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
 723 {
 724     MachineClass *mc = MACHINE_CLASS(oc);
 725
 726     mc->desc = "RISC-V Board compatible with SiFive U SDK";
 727     mc->init = sifive_u_machine_init;
 728     mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
 729     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
 730     mc->default_cpu_type = SIFIVE_U_CPU;
 731     mc->default_cpus = mc->min_cpus;
 732     mc->default_ram_id = "riscv.sifive.u.ram";
 733
 734     object_class_property_add_bool(oc, "start-in-flash",
 735                                    sifive_u_machine_get_start_in_flash,
 736                                    sifive_u_machine_set_start_in_flash);
 737     object_class_property_set_description(oc, "start-in-flash",
 738                                           "Set on to tell QEMU's ROM to jump to "
 739                                           "flash. Otherwise QEMU will jump to DRAM "
 740                                           "or L2LIM depending on the msel value");
 741 }
 742
 743 static const TypeInfo sifive_u_machine_typeinfo = {
 744     .name       = MACHINE_TYPE_NAME("sifive_u"),
 745     .parent     = TYPE_MACHINE,
 746     .class_init = sifive_u_machine_class_init,
 747     .instance_init = sifive_u_machine_instance_init,
 748     .instance_size = sizeof(SiFiveUState),
 749 };
 750
 751 static void sifive_u_machine_init_register_types(void)
 752 {
 753     type_register_static(&sifive_u_machine_typeinfo);
 754 }
 755
 756 type_init(sifive_u_machine_init_register_types)
 757
 758 static void sifive_u_soc_instance_init(Object *obj)
 759 {
 760     SiFiveUSoCState *s = RISCV_U_SOC(obj);
 761
 762     object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
 763     qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
 764
 765     object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
 766                             TYPE_RISCV_HART_ARRAY);
 767     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
 768     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
 769     qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
 770     qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
 771
 772     object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
 773     qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
 774
 775     object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
 776                             TYPE_RISCV_HART_ARRAY);
 777
 778     object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
 779     object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
 780     object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
 781     object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
 782     object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
 783     object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
 784     object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
 785     object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM);
 786     object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM);
 787 }
 788
 789 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
 790 {
 791     MachineState *ms = MACHINE(qdev_get_machine());
 792     SiFiveUSoCState *s = RISCV_U_SOC(dev);
 793     const MemMapEntry *memmap = sifive_u_memmap;
 794     MemoryRegion *system_memory = get_system_memory();
 795     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 796     MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
 797     char *plic_hart_config;
 798     int i, j;
 799     NICInfo *nd = &nd_table[0];
 800
 801     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
 802     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 803     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
 804     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
 805
 806     sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
 807     sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
 808     /*
 809      * The cluster must be realized after the RISC-V hart array container,
 810      * as the container's CPU object is only created on realize, and the
 811      * CPU must exist and have been parented into the cluster before the
 812      * cluster is realized.
 813      */
 814     qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
 815     qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
 816
 817     /* boot rom */
 818     memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
 819                            memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
 820     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
 821                                 mask_rom);
 822
 823     /*
 824      * Add L2-LIM at reset size.
 825      * This should be reduced in size as the L2 Cache Controller WayEnable
 826      * register is incremented. Unfortunately I don't see a nice (or any) way
 827      * to handle reducing or blocking out the L2 LIM while still allowing it
 828      * be re returned to all enabled after a reset. For the time being, just
 829      * leave it enabled all the time. This won't break anything, but will be
 830      * too generous to misbehaving guests.
 831      */
 832     memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
 833                            memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
 834     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
 835                                 l2lim_mem);
 836
 837     /* create PLIC hart topology configuration string */
 838     plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
 839
 840     /* MMIO */
 841     s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
 842         plic_hart_config, ms->smp.cpus, 0,
 843         SIFIVE_U_PLIC_NUM_SOURCES,
 844         SIFIVE_U_PLIC_NUM_PRIORITIES,
 845         SIFIVE_U_PLIC_PRIORITY_BASE,
 846         SIFIVE_U_PLIC_PENDING_BASE,
 847         SIFIVE_U_PLIC_ENABLE_BASE,
 848         SIFIVE_U_PLIC_ENABLE_STRIDE,
 849         SIFIVE_U_PLIC_CONTEXT_BASE,
 850         SIFIVE_U_PLIC_CONTEXT_STRIDE,
 851         memmap[SIFIVE_U_DEV_PLIC].size);
 852     g_free(plic_hart_config);
 853     sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
 854         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
 855     sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
 856         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
 857     riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0,
 858         ms->smp.cpus, false);
 859     riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base +
 860             RISCV_ACLINT_SWI_SIZE,
 861         RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
 862         RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 863         CLINT_TIMEBASE_FREQ, false);
 864
 865     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
 866         return;
 867     }
 868     sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
 869
 870     qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
 871     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
 872         return;
 873     }
 874     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
 875
 876     /* Pass all GPIOs to the SOC layer so they are available to the board */
 877     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
 878
 879     /* Connect GPIO interrupts to the PLIC */
 880     for (i = 0; i < 16; i++) {
 881         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
 882                            qdev_get_gpio_in(DEVICE(s->plic),
 883                                             SIFIVE_U_GPIO_IRQ0 + i));
 884     }
 885
 886     /* PDMA */
 887     sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
 888     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
 889
 890     /* Connect PDMA interrupts to the PLIC */
 891     for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
 892         sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
 893                            qdev_get_gpio_in(DEVICE(s->plic),
 894                                             SIFIVE_U_PDMA_IRQ0 + i));
 895     }
 896
 897     qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
 898     if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
 899         return;
 900     }
 901     sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
 902
 903     /* FIXME use qdev NIC properties instead of nd_table[] */
 904     if (nd->used) {
 905         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 906         qdev_set_nic_properties(DEVICE(&s->gem), nd);
 907     }
 908     object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
 909                             &error_abort);
 910     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
 911         return;
 912     }
 913     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
 914     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
 915                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
 916
 917     /* PWM */
 918     for (i = 0; i < 2; i++) {
 919         if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) {
 920             return;
 921         }
 922         sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0,
 923                                 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i));
 924
 925         /* Connect PWM interrupts to the PLIC */
 926         for (j = 0; j < SIFIVE_PWM_IRQS; j++) {
 927             sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j,
 928                                qdev_get_gpio_in(DEVICE(s->plic),
 929                                         SIFIVE_U_PWM0_IRQ0 + (i * 4) + j));
 930         }
 931     }
 932
 933     create_unimplemented_device("riscv.sifive.u.gem-mgmt",
 934         memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
 935
 936     create_unimplemented_device("riscv.sifive.u.dmc",
 937         memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
 938
 939     create_unimplemented_device("riscv.sifive.u.l2cc",
 940         memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
 941
 942     sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
 943     sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
 944                     memmap[SIFIVE_U_DEV_QSPI0].base);
 945     sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
 946                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));
 947     sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
 948     sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
 949                     memmap[SIFIVE_U_DEV_QSPI2].base);
 950     sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
 951                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
 952 }
 953
 954 static Property sifive_u_soc_props[] = {
 955     DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
 956     DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
 957     DEFINE_PROP_END_OF_LIST()
 958 };
 959
 960 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
 961 {
 962     DeviceClass *dc = DEVICE_CLASS(oc);
 963
 964     device_class_set_props(dc, sifive_u_soc_props);
 965     dc->realize = sifive_u_soc_realize;
 966     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 967     dc->user_creatable = false;
 968 }
 969
 970 static const TypeInfo sifive_u_soc_type_info = {
 971     .name = TYPE_RISCV_U_SOC,
 972     .parent = TYPE_DEVICE,
 973     .instance_size = sizeof(SiFiveUSoCState),
 974     .instance_init = sifive_u_soc_instance_init,
 975     .class_init = sifive_u_soc_class_init,
 976 };
 977
 978 static void sifive_u_soc_register_types(void)
 979 {
 980     type_register_static(&sifive_u_soc_type_info);
 981 }
 982
 983 type_init(sifive_u_soc_register_types)