hw/riscv/sifive_u.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017 SiFive, Inc.
   6  * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
   7  *
   8  * Provides a board compatible with the SiFive Freedom U SDK:
   9  *
  10  * 0) UART
  11  * 1) CLINT (Core Level Interruptor)
  12  * 2) PLIC (Platform Level Interrupt Controller)
  13  * 3) PRCI (Power, Reset, Clock, Interrupt)
  14  * 4) GPIO (General Purpose Input/Output Controller)
  15  * 5) OTP (One-Time Programmable) memory with stored serial number
  16  * 6) GEM (Gigabit Ethernet Controller) and management block
  17  * 7) DMA (Direct Memory Access Controller)
  18  * 8) SPI0 connected to an SPI flash
  19  * 9) SPI2 connected to an SD card
  20  *
  21  * This board currently generates devicetree dynamically that indicates at least
  22  * two harts and up to five harts.
  23  *
  24  * This program is free software; you can redistribute it and/or modify it
  25  * under the terms and conditions of the GNU General Public License,
  26  * version 2 or later, as published by the Free Software Foundation.
  27  *
  28  * This program is distributed in the hope it will be useful, but WITHOUT
  29  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  30  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  31  * more details.
  32  *
  33  * You should have received a copy of the GNU General Public License along with
  34  * this program.  If not, see <http://www.gnu.org/licenses/>.
  35  */
  36
  37 #include "qemu/osdep.h"
  38 #include "qemu/error-report.h"
  39 #include "qapi/error.h"
  40 #include "qapi/visitor.h"
  41 #include "hw/boards.h"
  42 #include "hw/irq.h"
  43 #include "hw/loader.h"
  44 #include "hw/sysbus.h"
  45 #include "hw/char/serial.h"
  46 #include "hw/cpu/cluster.h"
  47 #include "hw/misc/unimp.h"
  48 #include "hw/ssi/ssi.h"
  49 #include "target/riscv/cpu.h"
  50 #include "hw/riscv/riscv_hart.h"
  51 #include "hw/riscv/sifive_u.h"
  52 #include "hw/riscv/boot.h"
  53 #include "hw/char/sifive_uart.h"
  54 #include "hw/intc/sifive_clint.h"
  55 #include "hw/intc/sifive_plic.h"
  56 #include "chardev/char.h"
  57 #include "net/eth.h"
  58 #include "sysemu/arch_init.h"
  59 #include "sysemu/device_tree.h"
  60 #include "sysemu/runstate.h"
  61 #include "sysemu/sysemu.h"
  62
  63 #include <libfdt.h>
  64
  65 static const MemMapEntry sifive_u_memmap[] = {
  66     [SIFIVE_U_DEV_DEBUG] =    {        0x0,      0x100 },
  67     [SIFIVE_U_DEV_MROM] =     {     0x1000,     0xf000 },
  68     [SIFIVE_U_DEV_CLINT] =    {  0x2000000,    0x10000 },
  69     [SIFIVE_U_DEV_L2CC] =     {  0x2010000,     0x1000 },
  70     [SIFIVE_U_DEV_PDMA] =     {  0x3000000,   0x100000 },
  71     [SIFIVE_U_DEV_L2LIM] =    {  0x8000000,  0x2000000 },
  72     [SIFIVE_U_DEV_PLIC] =     {  0xc000000,  0x4000000 },
  73     [SIFIVE_U_DEV_PRCI] =     { 0x10000000,     0x1000 },
  74     [SIFIVE_U_DEV_UART0] =    { 0x10010000,     0x1000 },
  75     [SIFIVE_U_DEV_UART1] =    { 0x10011000,     0x1000 },
  76     [SIFIVE_U_DEV_QSPI0] =    { 0x10040000,     0x1000 },
  77     [SIFIVE_U_DEV_QSPI2] =    { 0x10050000,     0x1000 },
  78     [SIFIVE_U_DEV_GPIO] =     { 0x10060000,     0x1000 },
  79     [SIFIVE_U_DEV_OTP] =      { 0x10070000,     0x1000 },
  80     [SIFIVE_U_DEV_GEM] =      { 0x10090000,     0x2000 },
  81     [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000,     0x1000 },
  82     [SIFIVE_U_DEV_DMC] =      { 0x100b0000,    0x10000 },
  83     [SIFIVE_U_DEV_FLASH0] =   { 0x20000000, 0x10000000 },
  84     [SIFIVE_U_DEV_DRAM] =     { 0x80000000,        0x0 },
  85 };
  86
  87 #define OTP_SERIAL          1
  88 #define GEM_REVISION        0x10070109
  89
  90 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
  91                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
  92 {
  93     MachineState *ms = MACHINE(qdev_get_machine());
  94     void *fdt;
  95     int cpu;
  96     uint32_t *cells;
  97     char *nodename;
  98     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
  99     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
 100     static const char * const ethclk_names[2] = { "pclk", "hclk" };
 101     static const char * const clint_compat[2] = {
 102         "sifive,clint0", "riscv,clint0"
 103     };
 104
 105     if (ms->dtb) {
 106         fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
 107         if (!fdt) {
 108             error_report("load_device_tree() failed");
 109             exit(1);
 110         }
 111         goto update_bootargs;
 112     } else {
 113         fdt = s->fdt = create_device_tree(&s->fdt_size);
 114         if (!fdt) {
 115             error_report("create_device_tree() failed");
 116             exit(1);
 117         }
 118     }
 119
 120     qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
 121     qemu_fdt_setprop_string(fdt, "/", "compatible",
 122                             "sifive,hifive-unleashed-a00");
 123     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 124     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 125
 126     qemu_fdt_add_subnode(fdt, "/soc");
 127     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 128     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 129     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 130     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 131
 132     hfclk_phandle = phandle++;
 133     nodename = g_strdup_printf("/hfclk");
 134     qemu_fdt_add_subnode(fdt, nodename);
 135     qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
 136     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
 137     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 138         SIFIVE_U_HFCLK_FREQ);
 139     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 140     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 141     g_free(nodename);
 142
 143     rtcclk_phandle = phandle++;
 144     nodename = g_strdup_printf("/rtcclk");
 145     qemu_fdt_add_subnode(fdt, nodename);
 146     qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
 147     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
 148     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 149         SIFIVE_U_RTCCLK_FREQ);
 150     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 151     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 152     g_free(nodename);
 153
 154     nodename = g_strdup_printf("/memory@%lx",
 155         (long)memmap[SIFIVE_U_DEV_DRAM].base);
 156     qemu_fdt_add_subnode(fdt, nodename);
 157     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 158         memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
 159         mem_size >> 32, mem_size);
 160     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 161     g_free(nodename);
 162
 163     qemu_fdt_add_subnode(fdt, "/cpus");
 164     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 165         SIFIVE_CLINT_TIMEBASE_FREQ);
 166     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 167     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 168
 169     for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
 170         int cpu_phandle = phandle++;
 171         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 172         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 173         char *isa;
 174         qemu_fdt_add_subnode(fdt, nodename);
 175         /* cpu 0 is the management hart that does not have mmu */
 176         if (cpu != 0) {
 177             if (is_32_bit) {
 178                 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
 179             } else {
 180                 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 181             }
 182             isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
 183         } else {
 184             isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
 185         }
 186         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 187         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 188         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 189         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 190         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 191         qemu_fdt_add_subnode(fdt, intc);
 192         qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
 193         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 194         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 195         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 196         g_free(isa);
 197         g_free(intc);
 198         g_free(nodename);
 199     }
 200
 201     cells =  g_new0(uint32_t, ms->smp.cpus * 4);
 202     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 203         nodename =
 204             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 205         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 206         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 207         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 208         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 209         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 210         g_free(nodename);
 211     }
 212     nodename = g_strdup_printf("/soc/clint@%lx",
 213         (long)memmap[SIFIVE_U_DEV_CLINT].base);
 214     qemu_fdt_add_subnode(fdt, nodename);
 215     qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
 216         (char **)&clint_compat, ARRAY_SIZE(clint_compat));
 217     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 218         0x0, memmap[SIFIVE_U_DEV_CLINT].base,
 219         0x0, memmap[SIFIVE_U_DEV_CLINT].size);
 220     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 221         cells, ms->smp.cpus * sizeof(uint32_t) * 4);
 222     g_free(cells);
 223     g_free(nodename);
 224
 225     nodename = g_strdup_printf("/soc/otp@%lx",
 226         (long)memmap[SIFIVE_U_DEV_OTP].base);
 227     qemu_fdt_add_subnode(fdt, nodename);
 228     qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
 229     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 230         0x0, memmap[SIFIVE_U_DEV_OTP].base,
 231         0x0, memmap[SIFIVE_U_DEV_OTP].size);
 232     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 233         "sifive,fu540-c000-otp");
 234     g_free(nodename);
 235
 236     prci_phandle = phandle++;
 237     nodename = g_strdup_printf("/soc/clock-controller@%lx",
 238         (long)memmap[SIFIVE_U_DEV_PRCI].base);
 239     qemu_fdt_add_subnode(fdt, nodename);
 240     qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
 241     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
 242     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 243         hfclk_phandle, rtcclk_phandle);
 244     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 245         0x0, memmap[SIFIVE_U_DEV_PRCI].base,
 246         0x0, memmap[SIFIVE_U_DEV_PRCI].size);
 247     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 248         "sifive,fu540-c000-prci");
 249     g_free(nodename);
 250
 251     plic_phandle = phandle++;
 252     cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
 253     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 254         nodename =
 255             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 256         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 257         /* cpu 0 is the management hart that does not have S-mode */
 258         if (cpu == 0) {
 259             cells[0] = cpu_to_be32(intc_phandle);
 260             cells[1] = cpu_to_be32(IRQ_M_EXT);
 261         } else {
 262             cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
 263             cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
 264             cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 265             cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
 266         }
 267         g_free(nodename);
 268     }
 269     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 270         (long)memmap[SIFIVE_U_DEV_PLIC].base);
 271     qemu_fdt_add_subnode(fdt, nodename);
 272     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 273     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 274     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 275     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 276         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
 277     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 278         0x0, memmap[SIFIVE_U_DEV_PLIC].base,
 279         0x0, memmap[SIFIVE_U_DEV_PLIC].size);
 280     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 281     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 282     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 283     g_free(cells);
 284     g_free(nodename);
 285
 286     gpio_phandle = phandle++;
 287     nodename = g_strdup_printf("/soc/gpio@%lx",
 288         (long)memmap[SIFIVE_U_DEV_GPIO].base);
 289     qemu_fdt_add_subnode(fdt, nodename);
 290     qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
 291     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 292         prci_phandle, PRCI_CLK_TLCLK);
 293     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
 294     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 295     qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
 296     qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
 297     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 298         0x0, memmap[SIFIVE_U_DEV_GPIO].base,
 299         0x0, memmap[SIFIVE_U_DEV_GPIO].size);
 300     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
 301         SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
 302         SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
 303         SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
 304         SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
 305         SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
 306     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 307     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
 308     g_free(nodename);
 309
 310     nodename = g_strdup_printf("/gpio-restart");
 311     qemu_fdt_add_subnode(fdt, nodename);
 312     qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
 313     qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
 314     g_free(nodename);
 315
 316     nodename = g_strdup_printf("/soc/dma@%lx",
 317         (long)memmap[SIFIVE_U_DEV_PDMA].base);
 318     qemu_fdt_add_subnode(fdt, nodename);
 319     qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
 320     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
 321         SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
 322         SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
 323         SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
 324     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 325     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 326         0x0, memmap[SIFIVE_U_DEV_PDMA].base,
 327         0x0, memmap[SIFIVE_U_DEV_PDMA].size);
 328     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 329                             "sifive,fu540-c000-pdma");
 330     g_free(nodename);
 331
 332     nodename = g_strdup_printf("/soc/cache-controller@%lx",
 333         (long)memmap[SIFIVE_U_DEV_L2CC].base);
 334     qemu_fdt_add_subnode(fdt, nodename);
 335     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 336         0x0, memmap[SIFIVE_U_DEV_L2CC].base,
 337         0x0, memmap[SIFIVE_U_DEV_L2CC].size);
 338     qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
 339         SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
 340     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 341     qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
 342     qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
 343     qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
 344     qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
 345     qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
 346     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 347                             "sifive,fu540-c000-ccache");
 348     g_free(nodename);
 349
 350     nodename = g_strdup_printf("/soc/spi@%lx",
 351         (long)memmap[SIFIVE_U_DEV_QSPI2].base);
 352     qemu_fdt_add_subnode(fdt, nodename);
 353     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 354     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 355     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 356         prci_phandle, PRCI_CLK_TLCLK);
 357     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
 358     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 359     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 360         0x0, memmap[SIFIVE_U_DEV_QSPI2].base,
 361         0x0, memmap[SIFIVE_U_DEV_QSPI2].size);
 362     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
 363     g_free(nodename);
 364
 365     nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
 366         (long)memmap[SIFIVE_U_DEV_QSPI2].base);
 367     qemu_fdt_add_subnode(fdt, nodename);
 368     qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
 369     qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
 370     qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
 371     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
 372     qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
 373     g_free(nodename);
 374
 375     nodename = g_strdup_printf("/soc/spi@%lx",
 376         (long)memmap[SIFIVE_U_DEV_QSPI0].base);
 377     qemu_fdt_add_subnode(fdt, nodename);
 378     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 379     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 380     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 381         prci_phandle, PRCI_CLK_TLCLK);
 382     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
 383     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 384     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 385         0x0, memmap[SIFIVE_U_DEV_QSPI0].base,
 386         0x0, memmap[SIFIVE_U_DEV_QSPI0].size);
 387     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
 388     g_free(nodename);
 389
 390     nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
 391         (long)memmap[SIFIVE_U_DEV_QSPI0].base);
 392     qemu_fdt_add_subnode(fdt, nodename);
 393     qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
 394     qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
 395     qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
 396     qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
 397     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
 398     qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
 399     g_free(nodename);
 400
 401     phy_phandle = phandle++;
 402     nodename = g_strdup_printf("/soc/ethernet@%lx",
 403         (long)memmap[SIFIVE_U_DEV_GEM].base);
 404     qemu_fdt_add_subnode(fdt, nodename);
 405     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 406         "sifive,fu540-c000-gem");
 407     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 408         0x0, memmap[SIFIVE_U_DEV_GEM].base,
 409         0x0, memmap[SIFIVE_U_DEV_GEM].size,
 410         0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
 411         0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
 412     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 413     qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
 414     qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
 415     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 416     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 417     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 418         prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
 419     qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
 420         (char **)&ethclk_names, ARRAY_SIZE(ethclk_names));
 421     qemu_fdt_setprop(fdt, nodename, "local-mac-address",
 422         s->soc.gem.conf.macaddr.a, ETH_ALEN);
 423     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 424     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 425
 426     qemu_fdt_add_subnode(fdt, "/aliases");
 427     qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
 428
 429     g_free(nodename);
 430
 431     nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 432         (long)memmap[SIFIVE_U_DEV_GEM].base);
 433     qemu_fdt_add_subnode(fdt, nodename);
 434     qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
 435     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 436     g_free(nodename);
 437
 438     nodename = g_strdup_printf("/soc/serial@%lx",
 439         (long)memmap[SIFIVE_U_DEV_UART1].base);
 440     qemu_fdt_add_subnode(fdt, nodename);
 441     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 442     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 443         0x0, memmap[SIFIVE_U_DEV_UART1].base,
 444         0x0, memmap[SIFIVE_U_DEV_UART1].size);
 445     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 446         prci_phandle, PRCI_CLK_TLCLK);
 447     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 448     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
 449
 450     qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
 451     g_free(nodename);
 452
 453     nodename = g_strdup_printf("/soc/serial@%lx",
 454         (long)memmap[SIFIVE_U_DEV_UART0].base);
 455     qemu_fdt_add_subnode(fdt, nodename);
 456     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 457     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 458         0x0, memmap[SIFIVE_U_DEV_UART0].base,
 459         0x0, memmap[SIFIVE_U_DEV_UART0].size);
 460     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 461         prci_phandle, PRCI_CLK_TLCLK);
 462     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 463     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 464
 465     qemu_fdt_add_subnode(fdt, "/chosen");
 466     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 467     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 468
 469     g_free(nodename);
 470
 471 update_bootargs:
 472     if (cmdline) {
 473         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 474     }
 475 }
 476
 477 static void sifive_u_machine_reset(void *opaque, int n, int level)
 478 {
 479     /* gpio pin active low triggers reset */
 480     if (!level) {
 481         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 482     }
 483 }
 484
 485 static void sifive_u_machine_init(MachineState *machine)
 486 {
 487     const MemMapEntry *memmap = sifive_u_memmap;
 488     SiFiveUState *s = RISCV_U_MACHINE(machine);
 489     MemoryRegion *system_memory = get_system_memory();
 490     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 491     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
 492     target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
 493     target_ulong firmware_end_addr, kernel_start_addr;
 494     uint32_t start_addr_hi32 = 0x00000000;
 495     int i;
 496     uint32_t fdt_load_addr;
 497     uint64_t kernel_entry;
 498     DriveInfo *dinfo;
 499     DeviceState *flash_dev, *sd_dev;
 500     qemu_irq flash_cs, sd_cs;
 501
 502     /* Initialize SoC */
 503     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
 504     object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
 505                              &error_abort);
 506     object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
 507                              &error_abort);
 508     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 509
 510     /* register RAM */
 511     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
 512                            machine->ram_size, &error_fatal);
 513     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
 514                                 main_mem);
 515
 516     /* register QSPI0 Flash */
 517     memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
 518                            memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
 519     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
 520                                 flash0);
 521
 522     /* register gpio-restart */
 523     qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
 524                           qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
 525
 526     /* create device tree */
 527     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 528                riscv_is_32bit(&s->soc.u_cpus));
 529
 530     if (s->start_in_flash) {
 531         /*
 532          * If start_in_flash property is given, assign s->msel to a value
 533          * that representing booting from QSPI0 memory-mapped flash.
 534          *
 535          * This also means that when both start_in_flash and msel properties
 536          * are given, start_in_flash takes the precedence over msel.
 537          *
 538          * Note this is to keep backward compatibility not to break existing
 539          * users that use start_in_flash property.
 540          */
 541         s->msel = MSEL_MEMMAP_QSPI0_FLASH;
 542     }
 543
 544     switch (s->msel) {
 545     case MSEL_MEMMAP_QSPI0_FLASH:
 546         start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
 547         break;
 548     case MSEL_L2LIM_QSPI0_FLASH:
 549     case MSEL_L2LIM_QSPI2_SD:
 550         start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
 551         break;
 552     default:
 553         start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
 554         break;
 555     }
 556
 557     if (riscv_is_32bit(&s->soc.u_cpus)) {
 558         firmware_end_addr = riscv_find_and_load_firmware(machine,
 559                                     "opensbi-riscv32-generic-fw_dynamic.bin",
 560                                     start_addr, NULL);
 561     } else {
 562         firmware_end_addr = riscv_find_and_load_firmware(machine,
 563                                     "opensbi-riscv64-generic-fw_dynamic.bin",
 564                                     start_addr, NULL);
 565     }
 566
 567     if (machine->kernel_filename) {
 568         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
 569                                                          firmware_end_addr);
 570
 571         kernel_entry = riscv_load_kernel(machine->kernel_filename,
 572                                          kernel_start_addr, NULL);
 573
 574         if (machine->initrd_filename) {
 575             hwaddr start;
 576             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 577                                            machine->ram_size, kernel_entry,
 578                                            &start);
 579             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 580                                   "linux,initrd-start", start);
 581             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 582                                   end);
 583         }
 584     } else {
 585        /*
 586         * If dynamic firmware is used, it doesn't know where is the next mode
 587         * if kernel argument is not set.
 588         */
 589         kernel_entry = 0;
 590     }
 591
 592     /* Compute the fdt load address in dram */
 593     fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
 594                                    machine->ram_size, s->fdt);
 595     if (!riscv_is_32bit(&s->soc.u_cpus)) {
 596         start_addr_hi32 = (uint64_t)start_addr >> 32;
 597     }
 598
 599     /* reset vector */
 600     uint32_t reset_vec[11] = {
 601         s->msel,                       /* MSEL pin state */
 602         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
 603         0x02828613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
 604         0xf1402573,                    /*     csrr   a0, mhartid  */
 605         0,
 606         0,
 607         0x00028067,                    /*     jr     t0 */
 608         start_addr,                    /* start: .dword */
 609         start_addr_hi32,
 610         fdt_load_addr,                 /* fdt_laddr: .dword */
 611         0x00000000,
 612                                        /* fw_dyn: */
 613     };
 614     if (riscv_is_32bit(&s->soc.u_cpus)) {
 615         reset_vec[4] = 0x0202a583;     /*     lw     a1, 32(t0) */
 616         reset_vec[5] = 0x0182a283;     /*     lw     t0, 24(t0) */
 617     } else {
 618         reset_vec[4] = 0x0202b583;     /*     ld     a1, 32(t0) */
 619         reset_vec[5] = 0x0182b283;     /*     ld     t0, 24(t0) */
 620     }
 621
 622
 623     /* copy in the reset vector in little_endian byte order */
 624     for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
 625         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 626     }
 627     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 628                           memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
 629
 630     riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
 631                                  memmap[SIFIVE_U_DEV_MROM].size,
 632                                  sizeof(reset_vec), kernel_entry);
 633
 634     /* Connect an SPI flash to SPI0 */
 635     flash_dev = qdev_new("is25wp256");
 636     dinfo = drive_get_next(IF_MTD);
 637     if (dinfo) {
 638         qdev_prop_set_drive_err(flash_dev, "drive",
 639                                 blk_by_legacy_dinfo(dinfo),
 640                                 &error_fatal);
 641     }
 642     qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
 643
 644     flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 645     sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
 646
 647     /* Connect an SD card to SPI2 */
 648     sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
 649
 650     sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
 651     sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
 652 }
 653
 654 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
 655 {
 656     SiFiveUState *s = RISCV_U_MACHINE(obj);
 657
 658     return s->start_in_flash;
 659 }
 660
 661 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
 662 {
 663     SiFiveUState *s = RISCV_U_MACHINE(obj);
 664
 665     s->start_in_flash = value;
 666 }
 667
 668 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
 669                                              const char *name, void *opaque,
 670                                              Error **errp)
 671 {
 672     visit_type_uint32(v, name, (uint32_t *)opaque, errp);
 673 }
 674
 675 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
 676                                              const char *name, void *opaque,
 677                                              Error **errp)
 678 {
 679     visit_type_uint32(v, name, (uint32_t *)opaque, errp);
 680 }
 681
 682 static void sifive_u_machine_instance_init(Object *obj)
 683 {
 684     SiFiveUState *s = RISCV_U_MACHINE(obj);
 685
 686     s->start_in_flash = false;
 687     s->msel = 0;
 688     object_property_add(obj, "msel", "uint32",
 689                         sifive_u_machine_get_uint32_prop,
 690                         sifive_u_machine_set_uint32_prop, NULL, &s->msel);
 691     object_property_set_description(obj, "msel",
 692                                     "Mode Select (MSEL[3:0]) pin state");
 693
 694     s->serial = OTP_SERIAL;
 695     object_property_add(obj, "serial", "uint32",
 696                         sifive_u_machine_get_uint32_prop,
 697                         sifive_u_machine_set_uint32_prop, NULL, &s->serial);
 698     object_property_set_description(obj, "serial", "Board serial number");
 699 }
 700
 701 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
 702 {
 703     MachineClass *mc = MACHINE_CLASS(oc);
 704
 705     mc->desc = "RISC-V Board compatible with SiFive U SDK";
 706     mc->init = sifive_u_machine_init;
 707     mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
 708     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
 709     mc->default_cpu_type = SIFIVE_U_CPU;
 710     mc->default_cpus = mc->min_cpus;
 711
 712     object_class_property_add_bool(oc, "start-in-flash",
 713                                    sifive_u_machine_get_start_in_flash,
 714                                    sifive_u_machine_set_start_in_flash);
 715     object_class_property_set_description(oc, "start-in-flash",
 716                                           "Set on to tell QEMU's ROM to jump to "
 717                                           "flash. Otherwise QEMU will jump to DRAM "
 718                                           "or L2LIM depending on the msel value");
 719 }
 720
 721 static const TypeInfo sifive_u_machine_typeinfo = {
 722     .name       = MACHINE_TYPE_NAME("sifive_u"),
 723     .parent     = TYPE_MACHINE,
 724     .class_init = sifive_u_machine_class_init,
 725     .instance_init = sifive_u_machine_instance_init,
 726     .instance_size = sizeof(SiFiveUState),
 727 };
 728
 729 static void sifive_u_machine_init_register_types(void)
 730 {
 731     type_register_static(&sifive_u_machine_typeinfo);
 732 }
 733
 734 type_init(sifive_u_machine_init_register_types)
 735
 736 static void sifive_u_soc_instance_init(Object *obj)
 737 {
 738     SiFiveUSoCState *s = RISCV_U_SOC(obj);
 739
 740     object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
 741     qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
 742
 743     object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
 744                             TYPE_RISCV_HART_ARRAY);
 745     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
 746     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
 747     qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
 748     qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
 749
 750     object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
 751     qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
 752
 753     object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
 754                             TYPE_RISCV_HART_ARRAY);
 755
 756     object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
 757     object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
 758     object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
 759     object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
 760     object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
 761     object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
 762     object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
 763 }
 764
 765 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
 766 {
 767     MachineState *ms = MACHINE(qdev_get_machine());
 768     SiFiveUSoCState *s = RISCV_U_SOC(dev);
 769     const MemMapEntry *memmap = sifive_u_memmap;
 770     MemoryRegion *system_memory = get_system_memory();
 771     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 772     MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
 773     char *plic_hart_config;
 774     size_t plic_hart_config_len;
 775     int i;
 776     NICInfo *nd = &nd_table[0];
 777
 778     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
 779     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 780     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
 781     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
 782
 783     sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
 784     sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
 785     /*
 786      * The cluster must be realized after the RISC-V hart array container,
 787      * as the container's CPU object is only created on realize, and the
 788      * CPU must exist and have been parented into the cluster before the
 789      * cluster is realized.
 790      */
 791     qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
 792     qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
 793
 794     /* boot rom */
 795     memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
 796                            memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
 797     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
 798                                 mask_rom);
 799
 800     /*
 801      * Add L2-LIM at reset size.
 802      * This should be reduced in size as the L2 Cache Controller WayEnable
 803      * register is incremented. Unfortunately I don't see a nice (or any) way
 804      * to handle reducing or blocking out the L2 LIM while still allowing it
 805      * be re returned to all enabled after a reset. For the time being, just
 806      * leave it enabled all the time. This won't break anything, but will be
 807      * too generous to misbehaving guests.
 808      */
 809     memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
 810                            memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
 811     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
 812                                 l2lim_mem);
 813
 814     /* create PLIC hart topology configuration string */
 815     plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
 816                            ms->smp.cpus;
 817     plic_hart_config = g_malloc0(plic_hart_config_len);
 818     for (i = 0; i < ms->smp.cpus; i++) {
 819         if (i != 0) {
 820             strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
 821                     plic_hart_config_len);
 822         } else {
 823             strncat(plic_hart_config, "M", plic_hart_config_len);
 824         }
 825         plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
 826     }
 827
 828     /* MMIO */
 829     s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
 830         plic_hart_config, 0,
 831         SIFIVE_U_PLIC_NUM_SOURCES,
 832         SIFIVE_U_PLIC_NUM_PRIORITIES,
 833         SIFIVE_U_PLIC_PRIORITY_BASE,
 834         SIFIVE_U_PLIC_PENDING_BASE,
 835         SIFIVE_U_PLIC_ENABLE_BASE,
 836         SIFIVE_U_PLIC_ENABLE_STRIDE,
 837         SIFIVE_U_PLIC_CONTEXT_BASE,
 838         SIFIVE_U_PLIC_CONTEXT_STRIDE,
 839         memmap[SIFIVE_U_DEV_PLIC].size);
 840     g_free(plic_hart_config);
 841     sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
 842         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
 843     sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
 844         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
 845     sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
 846         memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
 847         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 848         SIFIVE_CLINT_TIMEBASE_FREQ, false);
 849
 850     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
 851         return;
 852     }
 853     sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
 854
 855     qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
 856     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
 857         return;
 858     }
 859     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
 860
 861     /* Pass all GPIOs to the SOC layer so they are available to the board */
 862     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
 863
 864     /* Connect GPIO interrupts to the PLIC */
 865     for (i = 0; i < 16; i++) {
 866         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
 867                            qdev_get_gpio_in(DEVICE(s->plic),
 868                                             SIFIVE_U_GPIO_IRQ0 + i));
 869     }
 870
 871     /* PDMA */
 872     sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
 873     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
 874
 875     /* Connect PDMA interrupts to the PLIC */
 876     for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
 877         sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
 878                            qdev_get_gpio_in(DEVICE(s->plic),
 879                                             SIFIVE_U_PDMA_IRQ0 + i));
 880     }
 881
 882     qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
 883     if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
 884         return;
 885     }
 886     sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
 887
 888     /* FIXME use qdev NIC properties instead of nd_table[] */
 889     if (nd->used) {
 890         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 891         qdev_set_nic_properties(DEVICE(&s->gem), nd);
 892     }
 893     object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
 894                             &error_abort);
 895     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
 896         return;
 897     }
 898     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
 899     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
 900                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
 901
 902     create_unimplemented_device("riscv.sifive.u.gem-mgmt",
 903         memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
 904
 905     create_unimplemented_device("riscv.sifive.u.dmc",
 906         memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
 907
 908     create_unimplemented_device("riscv.sifive.u.l2cc",
 909         memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
 910
 911     sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
 912     sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
 913                     memmap[SIFIVE_U_DEV_QSPI0].base);
 914     sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
 915                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));
 916     sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
 917     sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
 918                     memmap[SIFIVE_U_DEV_QSPI2].base);
 919     sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
 920                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
 921 }
 922
 923 static Property sifive_u_soc_props[] = {
 924     DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
 925     DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
 926     DEFINE_PROP_END_OF_LIST()
 927 };
 928
 929 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
 930 {
 931     DeviceClass *dc = DEVICE_CLASS(oc);
 932
 933     device_class_set_props(dc, sifive_u_soc_props);
 934     dc->realize = sifive_u_soc_realize;
 935     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 936     dc->user_creatable = false;
 937 }
 938
 939 static const TypeInfo sifive_u_soc_type_info = {
 940     .name = TYPE_RISCV_U_SOC,
 941     .parent = TYPE_DEVICE,
 942     .instance_size = sizeof(SiFiveUSoCState),
 943     .instance_init = sifive_u_soc_instance_init,
 944     .class_init = sifive_u_soc_class_init,
 945 };
 946
 947 static void sifive_u_soc_register_types(void)
 948 {
 949     type_register_static(&sifive_u_soc_type_info);
 950 }
 951
 952 type_init(sifive_u_soc_register_types)