2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
8 * Provides a board compatible with the SiFive Freedom U SDK:
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 * 7) DMA (Direct Memory Access Controller)
18 * 8) SPI0 connected to an SPI flash
19 * 9) SPI2 connected to an SD card
21 * This board currently generates devicetree dynamically that indicates at least
22 * two harts and up to five harts.
24 * This program is free software; you can redistribute it and/or modify it
25 * under the terms and conditions of the GNU General Public License,
26 * version 2 or later, as published by the Free Software Foundation.
28 * This program is distributed in the hope it will be useful, but WITHOUT
29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
33 * You should have received a copy of the GNU General Public License along with
34 * this program. If not, see <http://www.gnu.org/licenses/>.
37 #include "qemu/osdep.h"
38 #include "qemu/error-report.h"
39 #include "qapi/error.h"
40 #include "qapi/visitor.h"
41 #include "hw/boards.h"
43 #include "hw/loader.h"
44 #include "hw/sysbus.h"
45 #include "hw/char/serial.h"
46 #include "hw/cpu/cluster.h"
47 #include "hw/misc/unimp.h"
48 #include "hw/ssi/ssi.h"
49 #include "target/riscv/cpu.h"
50 #include "hw/riscv/riscv_hart.h"
51 #include "hw/riscv/sifive_u.h"
52 #include "hw/riscv/boot.h"
53 #include "hw/char/sifive_uart.h"
54 #include "hw/intc/sifive_clint.h"
55 #include "hw/intc/sifive_plic.h"
56 #include "chardev/char.h"
58 #include "sysemu/arch_init.h"
59 #include "sysemu/device_tree.h"
60 #include "sysemu/runstate.h"
61 #include "sysemu/sysemu.h"
65 static const MemMapEntry sifive_u_memmap[] = {
66 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
67 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
68 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
69 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
70 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
71 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
72 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
73 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
74 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
75 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
76 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
77 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },
78 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
79 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
80 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
81 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
82 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
83 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
84 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
88 #define GEM_REVISION 0x10070109
90 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
91 uint64_t mem_size, const char *cmdline, bool is_32_bit)
93 MachineState *ms = MACHINE(qdev_get_machine());
98 char ethclk_names[] = "pclk\0hclk";
99 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
100 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
103 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
105 error_report("load_device_tree() failed");
108 goto update_bootargs;
110 fdt = s->fdt = create_device_tree(&s->fdt_size);
112 error_report("create_device_tree() failed");
117 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
118 qemu_fdt_setprop_string(fdt, "/", "compatible",
119 "sifive,hifive-unleashed-a00");
120 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
121 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
123 qemu_fdt_add_subnode(fdt, "/soc");
124 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
125 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
126 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
127 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
129 hfclk_phandle = phandle++;
130 nodename = g_strdup_printf("/hfclk");
131 qemu_fdt_add_subnode(fdt, nodename);
132 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
133 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
134 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
135 SIFIVE_U_HFCLK_FREQ);
136 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
137 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
140 rtcclk_phandle = phandle++;
141 nodename = g_strdup_printf("/rtcclk");
142 qemu_fdt_add_subnode(fdt, nodename);
143 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
144 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
145 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
146 SIFIVE_U_RTCCLK_FREQ);
147 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
148 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
151 nodename = g_strdup_printf("/memory@%lx",
152 (long)memmap[SIFIVE_U_DEV_DRAM].base);
153 qemu_fdt_add_subnode(fdt, nodename);
154 qemu_fdt_setprop_cells(fdt, nodename, "reg",
155 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
156 mem_size >> 32, mem_size);
157 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
160 qemu_fdt_add_subnode(fdt, "/cpus");
161 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
162 SIFIVE_CLINT_TIMEBASE_FREQ);
163 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
164 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
166 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
167 int cpu_phandle = phandle++;
168 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
169 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
171 qemu_fdt_add_subnode(fdt, nodename);
172 /* cpu 0 is the management hart that does not have mmu */
175 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
177 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
179 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
181 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
183 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
184 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
185 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
186 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
187 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
188 qemu_fdt_add_subnode(fdt, intc);
189 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
190 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
191 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
192 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
198 cells = g_new0(uint32_t, ms->smp.cpus * 4);
199 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
201 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
202 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
203 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
204 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
205 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
206 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
209 nodename = g_strdup_printf("/soc/clint@%lx",
210 (long)memmap[SIFIVE_U_DEV_CLINT].base);
211 qemu_fdt_add_subnode(fdt, nodename);
212 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
213 qemu_fdt_setprop_cells(fdt, nodename, "reg",
214 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
215 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
216 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
217 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
221 nodename = g_strdup_printf("/soc/otp@%lx",
222 (long)memmap[SIFIVE_U_DEV_OTP].base);
223 qemu_fdt_add_subnode(fdt, nodename);
224 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
225 qemu_fdt_setprop_cells(fdt, nodename, "reg",
226 0x0, memmap[SIFIVE_U_DEV_OTP].base,
227 0x0, memmap[SIFIVE_U_DEV_OTP].size);
228 qemu_fdt_setprop_string(fdt, nodename, "compatible",
229 "sifive,fu540-c000-otp");
232 prci_phandle = phandle++;
233 nodename = g_strdup_printf("/soc/clock-controller@%lx",
234 (long)memmap[SIFIVE_U_DEV_PRCI].base);
235 qemu_fdt_add_subnode(fdt, nodename);
236 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
237 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
238 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
239 hfclk_phandle, rtcclk_phandle);
240 qemu_fdt_setprop_cells(fdt, nodename, "reg",
241 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
242 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
243 qemu_fdt_setprop_string(fdt, nodename, "compatible",
244 "sifive,fu540-c000-prci");
247 plic_phandle = phandle++;
248 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
249 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
251 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
252 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
253 /* cpu 0 is the management hart that does not have S-mode */
255 cells[0] = cpu_to_be32(intc_phandle);
256 cells[1] = cpu_to_be32(IRQ_M_EXT);
258 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
259 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
260 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
261 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
265 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
266 (long)memmap[SIFIVE_U_DEV_PLIC].base);
267 qemu_fdt_add_subnode(fdt, nodename);
268 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
269 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
270 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
271 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
272 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
273 qemu_fdt_setprop_cells(fdt, nodename, "reg",
274 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
275 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
276 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
277 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
278 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
282 gpio_phandle = phandle++;
283 nodename = g_strdup_printf("/soc/gpio@%lx",
284 (long)memmap[SIFIVE_U_DEV_GPIO].base);
285 qemu_fdt_add_subnode(fdt, nodename);
286 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
287 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
288 prci_phandle, PRCI_CLK_TLCLK);
289 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
290 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
291 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
292 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
293 qemu_fdt_setprop_cells(fdt, nodename, "reg",
294 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
295 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
296 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
297 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
298 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
299 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
300 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
301 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
302 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
303 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
306 nodename = g_strdup_printf("/gpio-restart");
307 qemu_fdt_add_subnode(fdt, nodename);
308 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
309 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
312 nodename = g_strdup_printf("/soc/dma@%lx",
313 (long)memmap[SIFIVE_U_DEV_PDMA].base);
314 qemu_fdt_add_subnode(fdt, nodename);
315 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
316 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
317 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
318 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
319 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
320 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
321 qemu_fdt_setprop_cells(fdt, nodename, "reg",
322 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
323 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
324 qemu_fdt_setprop_string(fdt, nodename, "compatible",
325 "sifive,fu540-c000-pdma");
328 nodename = g_strdup_printf("/soc/cache-controller@%lx",
329 (long)memmap[SIFIVE_U_DEV_L2CC].base);
330 qemu_fdt_add_subnode(fdt, nodename);
331 qemu_fdt_setprop_cells(fdt, nodename, "reg",
332 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
333 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
334 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
335 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
336 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
337 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
338 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
339 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
340 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
341 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
342 qemu_fdt_setprop_string(fdt, nodename, "compatible",
343 "sifive,fu540-c000-ccache");
346 nodename = g_strdup_printf("/soc/spi@%lx",
347 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
348 qemu_fdt_add_subnode(fdt, nodename);
349 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
350 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
351 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
352 prci_phandle, PRCI_CLK_TLCLK);
353 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
354 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
355 qemu_fdt_setprop_cells(fdt, nodename, "reg",
356 0x0, memmap[SIFIVE_U_DEV_QSPI2].base,
357 0x0, memmap[SIFIVE_U_DEV_QSPI2].size);
358 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
361 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
362 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
363 qemu_fdt_add_subnode(fdt, nodename);
364 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
365 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
366 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
367 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
368 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
371 nodename = g_strdup_printf("/soc/spi@%lx",
372 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
373 qemu_fdt_add_subnode(fdt, nodename);
374 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
375 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
376 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
377 prci_phandle, PRCI_CLK_TLCLK);
378 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
379 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
380 qemu_fdt_setprop_cells(fdt, nodename, "reg",
381 0x0, memmap[SIFIVE_U_DEV_QSPI0].base,
382 0x0, memmap[SIFIVE_U_DEV_QSPI0].size);
383 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
386 nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
387 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
388 qemu_fdt_add_subnode(fdt, nodename);
389 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
390 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
391 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
392 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
393 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
394 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
397 phy_phandle = phandle++;
398 nodename = g_strdup_printf("/soc/ethernet@%lx",
399 (long)memmap[SIFIVE_U_DEV_GEM].base);
400 qemu_fdt_add_subnode(fdt, nodename);
401 qemu_fdt_setprop_string(fdt, nodename, "compatible",
402 "sifive,fu540-c000-gem");
403 qemu_fdt_setprop_cells(fdt, nodename, "reg",
404 0x0, memmap[SIFIVE_U_DEV_GEM].base,
405 0x0, memmap[SIFIVE_U_DEV_GEM].size,
406 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
407 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
408 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
409 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
410 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
411 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
412 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
413 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
414 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
415 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
416 sizeof(ethclk_names));
417 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
418 s->soc.gem.conf.macaddr.a, ETH_ALEN);
419 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
420 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
422 qemu_fdt_add_subnode(fdt, "/aliases");
423 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
427 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
428 (long)memmap[SIFIVE_U_DEV_GEM].base);
429 qemu_fdt_add_subnode(fdt, nodename);
430 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
431 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
434 nodename = g_strdup_printf("/soc/serial@%lx",
435 (long)memmap[SIFIVE_U_DEV_UART1].base);
436 qemu_fdt_add_subnode(fdt, nodename);
437 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
438 qemu_fdt_setprop_cells(fdt, nodename, "reg",
439 0x0, memmap[SIFIVE_U_DEV_UART1].base,
440 0x0, memmap[SIFIVE_U_DEV_UART1].size);
441 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
442 prci_phandle, PRCI_CLK_TLCLK);
443 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
444 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
446 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
449 nodename = g_strdup_printf("/soc/serial@%lx",
450 (long)memmap[SIFIVE_U_DEV_UART0].base);
451 qemu_fdt_add_subnode(fdt, nodename);
452 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
453 qemu_fdt_setprop_cells(fdt, nodename, "reg",
454 0x0, memmap[SIFIVE_U_DEV_UART0].base,
455 0x0, memmap[SIFIVE_U_DEV_UART0].size);
456 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
457 prci_phandle, PRCI_CLK_TLCLK);
458 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
459 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
461 qemu_fdt_add_subnode(fdt, "/chosen");
462 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
463 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
469 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
473 static void sifive_u_machine_reset(void *opaque, int n, int level)
475 /* gpio pin active low triggers reset */
477 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
481 static void sifive_u_machine_init(MachineState *machine)
483 const MemMapEntry *memmap = sifive_u_memmap;
484 SiFiveUState *s = RISCV_U_MACHINE(machine);
485 MemoryRegion *system_memory = get_system_memory();
486 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
487 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
488 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
489 target_ulong firmware_end_addr, kernel_start_addr;
490 uint32_t start_addr_hi32 = 0x00000000;
492 uint32_t fdt_load_addr;
493 uint64_t kernel_entry;
495 DeviceState *flash_dev, *sd_dev;
496 qemu_irq flash_cs, sd_cs;
499 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
500 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
502 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
504 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
507 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
508 machine->ram_size, &error_fatal);
509 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
512 /* register QSPI0 Flash */
513 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
514 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
515 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
518 /* register gpio-restart */
519 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
520 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
522 /* create device tree */
523 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
524 riscv_is_32bit(&s->soc.u_cpus));
526 if (s->start_in_flash) {
528 * If start_in_flash property is given, assign s->msel to a value
529 * that representing booting from QSPI0 memory-mapped flash.
531 * This also means that when both start_in_flash and msel properties
532 * are given, start_in_flash takes the precedence over msel.
534 * Note this is to keep backward compatibility not to break existing
535 * users that use start_in_flash property.
537 s->msel = MSEL_MEMMAP_QSPI0_FLASH;
541 case MSEL_MEMMAP_QSPI0_FLASH:
542 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
544 case MSEL_L2LIM_QSPI0_FLASH:
545 case MSEL_L2LIM_QSPI2_SD:
546 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
549 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
553 if (riscv_is_32bit(&s->soc.u_cpus)) {
554 firmware_end_addr = riscv_find_and_load_firmware(machine,
555 "opensbi-riscv32-generic-fw_dynamic.bin",
558 firmware_end_addr = riscv_find_and_load_firmware(machine,
559 "opensbi-riscv64-generic-fw_dynamic.bin",
563 if (machine->kernel_filename) {
564 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
567 kernel_entry = riscv_load_kernel(machine->kernel_filename,
568 kernel_start_addr, NULL);
570 if (machine->initrd_filename) {
572 hwaddr end = riscv_load_initrd(machine->initrd_filename,
573 machine->ram_size, kernel_entry,
575 qemu_fdt_setprop_cell(s->fdt, "/chosen",
576 "linux,initrd-start", start);
577 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
582 * If dynamic firmware is used, it doesn't know where is the next mode
583 * if kernel argument is not set.
588 /* Compute the fdt load address in dram */
589 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
590 machine->ram_size, s->fdt);
591 if (!riscv_is_32bit(&s->soc.u_cpus)) {
592 start_addr_hi32 = (uint64_t)start_addr >> 32;
596 uint32_t reset_vec[11] = {
597 s->msel, /* MSEL pin state */
598 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
599 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
600 0xf1402573, /* csrr a0, mhartid */
603 0x00028067, /* jr t0 */
604 start_addr, /* start: .dword */
606 fdt_load_addr, /* fdt_laddr: .dword */
610 if (riscv_is_32bit(&s->soc.u_cpus)) {
611 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
612 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
614 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
615 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
619 /* copy in the reset vector in little_endian byte order */
620 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
621 reset_vec[i] = cpu_to_le32(reset_vec[i]);
623 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
624 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
626 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
627 memmap[SIFIVE_U_DEV_MROM].size,
628 sizeof(reset_vec), kernel_entry);
630 /* Connect an SPI flash to SPI0 */
631 flash_dev = qdev_new("is25wp256");
632 dinfo = drive_get_next(IF_MTD);
634 qdev_prop_set_drive_err(flash_dev, "drive",
635 blk_by_legacy_dinfo(dinfo),
638 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
640 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
641 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
643 /* Connect an SD card to SPI2 */
644 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
646 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
647 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
650 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
652 SiFiveUState *s = RISCV_U_MACHINE(obj);
654 return s->start_in_flash;
657 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
659 SiFiveUState *s = RISCV_U_MACHINE(obj);
661 s->start_in_flash = value;
664 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
665 const char *name, void *opaque,
668 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
671 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
672 const char *name, void *opaque,
675 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
678 static void sifive_u_machine_instance_init(Object *obj)
680 SiFiveUState *s = RISCV_U_MACHINE(obj);
682 s->start_in_flash = false;
684 object_property_add(obj, "msel", "uint32",
685 sifive_u_machine_get_uint32_prop,
686 sifive_u_machine_set_uint32_prop, NULL, &s->msel);
687 object_property_set_description(obj, "msel",
688 "Mode Select (MSEL[3:0]) pin state");
690 s->serial = OTP_SERIAL;
691 object_property_add(obj, "serial", "uint32",
692 sifive_u_machine_get_uint32_prop,
693 sifive_u_machine_set_uint32_prop, NULL, &s->serial);
694 object_property_set_description(obj, "serial", "Board serial number");
697 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
699 MachineClass *mc = MACHINE_CLASS(oc);
701 mc->desc = "RISC-V Board compatible with SiFive U SDK";
702 mc->init = sifive_u_machine_init;
703 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
704 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
705 mc->default_cpu_type = SIFIVE_U_CPU;
706 mc->default_cpus = mc->min_cpus;
708 object_class_property_add_bool(oc, "start-in-flash",
709 sifive_u_machine_get_start_in_flash,
710 sifive_u_machine_set_start_in_flash);
711 object_class_property_set_description(oc, "start-in-flash",
712 "Set on to tell QEMU's ROM to jump to "
713 "flash. Otherwise QEMU will jump to DRAM "
714 "or L2LIM depending on the msel value");
717 static const TypeInfo sifive_u_machine_typeinfo = {
718 .name = MACHINE_TYPE_NAME("sifive_u"),
719 .parent = TYPE_MACHINE,
720 .class_init = sifive_u_machine_class_init,
721 .instance_init = sifive_u_machine_instance_init,
722 .instance_size = sizeof(SiFiveUState),
725 static void sifive_u_machine_init_register_types(void)
727 type_register_static(&sifive_u_machine_typeinfo);
730 type_init(sifive_u_machine_init_register_types)
732 static void sifive_u_soc_instance_init(Object *obj)
734 SiFiveUSoCState *s = RISCV_U_SOC(obj);
736 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
737 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
739 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
740 TYPE_RISCV_HART_ARRAY);
741 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
742 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
743 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
744 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
746 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
747 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
749 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
750 TYPE_RISCV_HART_ARRAY);
752 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
753 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
754 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
755 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
756 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
757 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
758 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
761 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
763 MachineState *ms = MACHINE(qdev_get_machine());
764 SiFiveUSoCState *s = RISCV_U_SOC(dev);
765 const MemMapEntry *memmap = sifive_u_memmap;
766 MemoryRegion *system_memory = get_system_memory();
767 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
768 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
769 char *plic_hart_config;
770 size_t plic_hart_config_len;
772 NICInfo *nd = &nd_table[0];
774 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
775 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
776 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
777 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
779 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
780 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
782 * The cluster must be realized after the RISC-V hart array container,
783 * as the container's CPU object is only created on realize, and the
784 * CPU must exist and have been parented into the cluster before the
785 * cluster is realized.
787 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
788 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
791 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
792 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
793 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
797 * Add L2-LIM at reset size.
798 * This should be reduced in size as the L2 Cache Controller WayEnable
799 * register is incremented. Unfortunately I don't see a nice (or any) way
800 * to handle reducing or blocking out the L2 LIM while still allowing it
801 * be re returned to all enabled after a reset. For the time being, just
802 * leave it enabled all the time. This won't break anything, but will be
803 * too generous to misbehaving guests.
805 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
806 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
807 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
810 /* create PLIC hart topology configuration string */
811 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
813 plic_hart_config = g_malloc0(plic_hart_config_len);
814 for (i = 0; i < ms->smp.cpus; i++) {
816 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
817 plic_hart_config_len);
819 strncat(plic_hart_config, "M", plic_hart_config_len);
821 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
825 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
827 SIFIVE_U_PLIC_NUM_SOURCES,
828 SIFIVE_U_PLIC_NUM_PRIORITIES,
829 SIFIVE_U_PLIC_PRIORITY_BASE,
830 SIFIVE_U_PLIC_PENDING_BASE,
831 SIFIVE_U_PLIC_ENABLE_BASE,
832 SIFIVE_U_PLIC_ENABLE_STRIDE,
833 SIFIVE_U_PLIC_CONTEXT_BASE,
834 SIFIVE_U_PLIC_CONTEXT_STRIDE,
835 memmap[SIFIVE_U_DEV_PLIC].size);
836 g_free(plic_hart_config);
837 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
838 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
839 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
840 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
841 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
842 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
843 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
844 SIFIVE_CLINT_TIMEBASE_FREQ, false);
846 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
849 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
851 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
852 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
855 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
857 /* Pass all GPIOs to the SOC layer so they are available to the board */
858 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
860 /* Connect GPIO interrupts to the PLIC */
861 for (i = 0; i < 16; i++) {
862 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
863 qdev_get_gpio_in(DEVICE(s->plic),
864 SIFIVE_U_GPIO_IRQ0 + i));
868 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
869 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
871 /* Connect PDMA interrupts to the PLIC */
872 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
873 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
874 qdev_get_gpio_in(DEVICE(s->plic),
875 SIFIVE_U_PDMA_IRQ0 + i));
878 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
879 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
882 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
884 /* FIXME use qdev NIC properties instead of nd_table[] */
886 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
887 qdev_set_nic_properties(DEVICE(&s->gem), nd);
889 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
891 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
894 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
895 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
896 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
898 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
899 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
901 create_unimplemented_device("riscv.sifive.u.dmc",
902 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
904 create_unimplemented_device("riscv.sifive.u.l2cc",
905 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
907 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
908 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
909 memmap[SIFIVE_U_DEV_QSPI0].base);
910 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
911 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));
912 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
913 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
914 memmap[SIFIVE_U_DEV_QSPI2].base);
915 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
916 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
919 static Property sifive_u_soc_props[] = {
920 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
921 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
922 DEFINE_PROP_END_OF_LIST()
925 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
927 DeviceClass *dc = DEVICE_CLASS(oc);
929 device_class_set_props(dc, sifive_u_soc_props);
930 dc->realize = sifive_u_soc_realize;
931 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
932 dc->user_creatable = false;
935 static const TypeInfo sifive_u_soc_type_info = {
936 .name = TYPE_RISCV_U_SOC,
937 .parent = TYPE_DEVICE,
938 .instance_size = sizeof(SiFiveUSoCState),
939 .instance_init = sifive_u_soc_instance_init,
940 .class_init = sifive_u_soc_class_init,
943 static void sifive_u_soc_register_types(void)
945 type_register_static(&sifive_u_soc_type_info);
948 type_init(sifive_u_soc_register_types)