2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
8 * Provides a board compatible with the SiFive Freedom U SDK:
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 * 7) DMA (Direct Memory Access Controller)
18 * 8) SPI0 connected to an SPI flash
19 * 9) SPI2 connected to an SD card
21 * This board currently generates devicetree dynamically that indicates at least
22 * two harts and up to five harts.
24 * This program is free software; you can redistribute it and/or modify it
25 * under the terms and conditions of the GNU General Public License,
26 * version 2 or later, as published by the Free Software Foundation.
28 * This program is distributed in the hope it will be useful, but WITHOUT
29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
33 * You should have received a copy of the GNU General Public License along with
34 * this program. If not, see <http://www.gnu.org/licenses/>.
37 #include "qemu/osdep.h"
38 #include "qemu/error-report.h"
39 #include "qapi/error.h"
40 #include "qapi/visitor.h"
41 #include "hw/boards.h"
43 #include "hw/loader.h"
44 #include "hw/sysbus.h"
45 #include "hw/char/serial.h"
46 #include "hw/cpu/cluster.h"
47 #include "hw/misc/unimp.h"
48 #include "hw/ssi/ssi.h"
49 #include "target/riscv/cpu.h"
50 #include "hw/riscv/riscv_hart.h"
51 #include "hw/riscv/sifive_u.h"
52 #include "hw/riscv/boot.h"
53 #include "hw/char/sifive_uart.h"
54 #include "hw/intc/sifive_clint.h"
55 #include "hw/intc/sifive_plic.h"
56 #include "chardev/char.h"
58 #include "sysemu/device_tree.h"
59 #include "sysemu/runstate.h"
60 #include "sysemu/sysemu.h"
64 /* CLINT timebase frequency */
65 #define CLINT_TIMEBASE_FREQ 1000000
67 static const MemMapEntry sifive_u_memmap[] = {
68 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
69 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
70 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
71 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
72 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
73 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
74 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
75 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
76 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
77 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
78 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
79 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },
80 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
81 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
82 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
83 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
84 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
85 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
86 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
90 #define GEM_REVISION 0x10070109
92 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
93 uint64_t mem_size, const char *cmdline, bool is_32_bit)
95 MachineState *ms = MACHINE(qdev_get_machine());
100 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
101 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
102 static const char * const ethclk_names[2] = { "pclk", "hclk" };
103 static const char * const clint_compat[2] = {
104 "sifive,clint0", "riscv,clint0"
106 static const char * const plic_compat[2] = {
107 "sifive,plic-1.0.0", "riscv,plic0"
111 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
113 error_report("load_device_tree() failed");
116 goto update_bootargs;
118 fdt = s->fdt = create_device_tree(&s->fdt_size);
120 error_report("create_device_tree() failed");
125 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
126 qemu_fdt_setprop_string(fdt, "/", "compatible",
127 "sifive,hifive-unleashed-a00");
128 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
129 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
131 qemu_fdt_add_subnode(fdt, "/soc");
132 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
133 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
134 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
135 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
137 hfclk_phandle = phandle++;
138 nodename = g_strdup_printf("/hfclk");
139 qemu_fdt_add_subnode(fdt, nodename);
140 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
141 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
142 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
143 SIFIVE_U_HFCLK_FREQ);
144 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
145 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
148 rtcclk_phandle = phandle++;
149 nodename = g_strdup_printf("/rtcclk");
150 qemu_fdt_add_subnode(fdt, nodename);
151 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
152 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
153 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
154 SIFIVE_U_RTCCLK_FREQ);
155 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
156 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
159 nodename = g_strdup_printf("/memory@%lx",
160 (long)memmap[SIFIVE_U_DEV_DRAM].base);
161 qemu_fdt_add_subnode(fdt, nodename);
162 qemu_fdt_setprop_cells(fdt, nodename, "reg",
163 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
164 mem_size >> 32, mem_size);
165 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
168 qemu_fdt_add_subnode(fdt, "/cpus");
169 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
170 CLINT_TIMEBASE_FREQ);
171 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
172 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
174 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
175 int cpu_phandle = phandle++;
176 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
177 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
179 qemu_fdt_add_subnode(fdt, nodename);
180 /* cpu 0 is the management hart that does not have mmu */
183 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
185 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
187 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
189 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
191 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
192 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
193 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
194 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
195 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
196 qemu_fdt_add_subnode(fdt, intc);
197 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
198 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
199 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
200 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
206 cells = g_new0(uint32_t, ms->smp.cpus * 4);
207 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
209 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
210 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
211 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
212 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
213 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
214 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
217 nodename = g_strdup_printf("/soc/clint@%lx",
218 (long)memmap[SIFIVE_U_DEV_CLINT].base);
219 qemu_fdt_add_subnode(fdt, nodename);
220 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
221 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
222 qemu_fdt_setprop_cells(fdt, nodename, "reg",
223 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
224 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
225 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
226 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
230 nodename = g_strdup_printf("/soc/otp@%lx",
231 (long)memmap[SIFIVE_U_DEV_OTP].base);
232 qemu_fdt_add_subnode(fdt, nodename);
233 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
234 qemu_fdt_setprop_cells(fdt, nodename, "reg",
235 0x0, memmap[SIFIVE_U_DEV_OTP].base,
236 0x0, memmap[SIFIVE_U_DEV_OTP].size);
237 qemu_fdt_setprop_string(fdt, nodename, "compatible",
238 "sifive,fu540-c000-otp");
241 prci_phandle = phandle++;
242 nodename = g_strdup_printf("/soc/clock-controller@%lx",
243 (long)memmap[SIFIVE_U_DEV_PRCI].base);
244 qemu_fdt_add_subnode(fdt, nodename);
245 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
246 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
247 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
248 hfclk_phandle, rtcclk_phandle);
249 qemu_fdt_setprop_cells(fdt, nodename, "reg",
250 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
251 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
252 qemu_fdt_setprop_string(fdt, nodename, "compatible",
253 "sifive,fu540-c000-prci");
256 plic_phandle = phandle++;
257 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
258 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
260 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
261 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
262 /* cpu 0 is the management hart that does not have S-mode */
264 cells[0] = cpu_to_be32(intc_phandle);
265 cells[1] = cpu_to_be32(IRQ_M_EXT);
267 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
268 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
269 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
270 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
274 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
275 (long)memmap[SIFIVE_U_DEV_PLIC].base);
276 qemu_fdt_add_subnode(fdt, nodename);
277 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
278 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
279 (char **)&plic_compat, ARRAY_SIZE(plic_compat));
280 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
281 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
282 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
283 qemu_fdt_setprop_cells(fdt, nodename, "reg",
284 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
285 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
286 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
287 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
288 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
292 gpio_phandle = phandle++;
293 nodename = g_strdup_printf("/soc/gpio@%lx",
294 (long)memmap[SIFIVE_U_DEV_GPIO].base);
295 qemu_fdt_add_subnode(fdt, nodename);
296 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
297 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
298 prci_phandle, PRCI_CLK_TLCLK);
299 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
300 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
301 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
302 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
303 qemu_fdt_setprop_cells(fdt, nodename, "reg",
304 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
305 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
306 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
307 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
308 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
309 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
310 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
311 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
312 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
313 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
316 nodename = g_strdup_printf("/gpio-restart");
317 qemu_fdt_add_subnode(fdt, nodename);
318 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
319 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
322 nodename = g_strdup_printf("/soc/dma@%lx",
323 (long)memmap[SIFIVE_U_DEV_PDMA].base);
324 qemu_fdt_add_subnode(fdt, nodename);
325 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
326 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
327 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
328 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
329 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
330 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
331 qemu_fdt_setprop_cells(fdt, nodename, "reg",
332 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
333 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
334 qemu_fdt_setprop_string(fdt, nodename, "compatible",
335 "sifive,fu540-c000-pdma");
338 nodename = g_strdup_printf("/soc/cache-controller@%lx",
339 (long)memmap[SIFIVE_U_DEV_L2CC].base);
340 qemu_fdt_add_subnode(fdt, nodename);
341 qemu_fdt_setprop_cells(fdt, nodename, "reg",
342 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
343 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
344 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
345 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
346 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
347 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
348 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
349 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
350 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
351 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
352 qemu_fdt_setprop_string(fdt, nodename, "compatible",
353 "sifive,fu540-c000-ccache");
356 nodename = g_strdup_printf("/soc/spi@%lx",
357 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
358 qemu_fdt_add_subnode(fdt, nodename);
359 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
360 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
361 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
362 prci_phandle, PRCI_CLK_TLCLK);
363 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
364 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
365 qemu_fdt_setprop_cells(fdt, nodename, "reg",
366 0x0, memmap[SIFIVE_U_DEV_QSPI2].base,
367 0x0, memmap[SIFIVE_U_DEV_QSPI2].size);
368 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
371 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
372 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
373 qemu_fdt_add_subnode(fdt, nodename);
374 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
375 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
376 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
377 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
378 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
381 nodename = g_strdup_printf("/soc/spi@%lx",
382 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
383 qemu_fdt_add_subnode(fdt, nodename);
384 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
385 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
386 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
387 prci_phandle, PRCI_CLK_TLCLK);
388 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
389 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
390 qemu_fdt_setprop_cells(fdt, nodename, "reg",
391 0x0, memmap[SIFIVE_U_DEV_QSPI0].base,
392 0x0, memmap[SIFIVE_U_DEV_QSPI0].size);
393 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
396 nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
397 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
398 qemu_fdt_add_subnode(fdt, nodename);
399 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
400 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
401 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
402 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
403 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
404 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
407 phy_phandle = phandle++;
408 nodename = g_strdup_printf("/soc/ethernet@%lx",
409 (long)memmap[SIFIVE_U_DEV_GEM].base);
410 qemu_fdt_add_subnode(fdt, nodename);
411 qemu_fdt_setprop_string(fdt, nodename, "compatible",
412 "sifive,fu540-c000-gem");
413 qemu_fdt_setprop_cells(fdt, nodename, "reg",
414 0x0, memmap[SIFIVE_U_DEV_GEM].base,
415 0x0, memmap[SIFIVE_U_DEV_GEM].size,
416 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
417 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
418 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
419 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
420 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
421 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
422 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
423 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
424 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
425 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
426 (char **)ðclk_names, ARRAY_SIZE(ethclk_names));
427 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
428 s->soc.gem.conf.macaddr.a, ETH_ALEN);
429 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
430 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
432 qemu_fdt_add_subnode(fdt, "/aliases");
433 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
437 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
438 (long)memmap[SIFIVE_U_DEV_GEM].base);
439 qemu_fdt_add_subnode(fdt, nodename);
440 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
441 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
444 nodename = g_strdup_printf("/soc/serial@%lx",
445 (long)memmap[SIFIVE_U_DEV_UART1].base);
446 qemu_fdt_add_subnode(fdt, nodename);
447 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
448 qemu_fdt_setprop_cells(fdt, nodename, "reg",
449 0x0, memmap[SIFIVE_U_DEV_UART1].base,
450 0x0, memmap[SIFIVE_U_DEV_UART1].size);
451 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
452 prci_phandle, PRCI_CLK_TLCLK);
453 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
454 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
456 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
459 nodename = g_strdup_printf("/soc/serial@%lx",
460 (long)memmap[SIFIVE_U_DEV_UART0].base);
461 qemu_fdt_add_subnode(fdt, nodename);
462 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
463 qemu_fdt_setprop_cells(fdt, nodename, "reg",
464 0x0, memmap[SIFIVE_U_DEV_UART0].base,
465 0x0, memmap[SIFIVE_U_DEV_UART0].size);
466 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
467 prci_phandle, PRCI_CLK_TLCLK);
468 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
469 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
471 qemu_fdt_add_subnode(fdt, "/chosen");
472 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
473 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
479 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
483 static void sifive_u_machine_reset(void *opaque, int n, int level)
485 /* gpio pin active low triggers reset */
487 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
491 static void sifive_u_machine_init(MachineState *machine)
493 const MemMapEntry *memmap = sifive_u_memmap;
494 SiFiveUState *s = RISCV_U_MACHINE(machine);
495 MemoryRegion *system_memory = get_system_memory();
496 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
497 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
498 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
499 target_ulong firmware_end_addr, kernel_start_addr;
500 uint32_t start_addr_hi32 = 0x00000000;
502 uint32_t fdt_load_addr;
503 uint64_t kernel_entry;
505 DeviceState *flash_dev, *sd_dev;
506 qemu_irq flash_cs, sd_cs;
509 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
510 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
512 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
514 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
517 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
518 machine->ram_size, &error_fatal);
519 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
522 /* register QSPI0 Flash */
523 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
524 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
525 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
528 /* register gpio-restart */
529 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
530 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
532 /* create device tree */
533 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
534 riscv_is_32bit(&s->soc.u_cpus));
536 if (s->start_in_flash) {
538 * If start_in_flash property is given, assign s->msel to a value
539 * that representing booting from QSPI0 memory-mapped flash.
541 * This also means that when both start_in_flash and msel properties
542 * are given, start_in_flash takes the precedence over msel.
544 * Note this is to keep backward compatibility not to break existing
545 * users that use start_in_flash property.
547 s->msel = MSEL_MEMMAP_QSPI0_FLASH;
551 case MSEL_MEMMAP_QSPI0_FLASH:
552 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
554 case MSEL_L2LIM_QSPI0_FLASH:
555 case MSEL_L2LIM_QSPI2_SD:
556 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
559 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
563 if (riscv_is_32bit(&s->soc.u_cpus)) {
564 firmware_end_addr = riscv_find_and_load_firmware(machine,
565 RISCV32_BIOS_BIN, start_addr, NULL);
567 firmware_end_addr = riscv_find_and_load_firmware(machine,
568 RISCV64_BIOS_BIN, start_addr, NULL);
571 if (machine->kernel_filename) {
572 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
575 kernel_entry = riscv_load_kernel(machine->kernel_filename,
576 kernel_start_addr, NULL);
578 if (machine->initrd_filename) {
580 hwaddr end = riscv_load_initrd(machine->initrd_filename,
581 machine->ram_size, kernel_entry,
583 qemu_fdt_setprop_cell(s->fdt, "/chosen",
584 "linux,initrd-start", start);
585 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
590 * If dynamic firmware is used, it doesn't know where is the next mode
591 * if kernel argument is not set.
596 /* Compute the fdt load address in dram */
597 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
598 machine->ram_size, s->fdt);
599 if (!riscv_is_32bit(&s->soc.u_cpus)) {
600 start_addr_hi32 = (uint64_t)start_addr >> 32;
604 uint32_t reset_vec[12] = {
605 s->msel, /* MSEL pin state */
606 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
607 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
608 0xf1402573, /* csrr a0, mhartid */
611 0x00028067, /* jr t0 */
612 start_addr, /* start: .dword */
614 fdt_load_addr, /* fdt_laddr: .dword */
619 if (riscv_is_32bit(&s->soc.u_cpus)) {
620 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
621 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
623 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
624 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
628 /* copy in the reset vector in little_endian byte order */
629 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
630 reset_vec[i] = cpu_to_le32(reset_vec[i]);
632 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
633 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
635 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
636 memmap[SIFIVE_U_DEV_MROM].size,
637 sizeof(reset_vec), kernel_entry);
639 /* Connect an SPI flash to SPI0 */
640 flash_dev = qdev_new("is25wp256");
641 dinfo = drive_get_next(IF_MTD);
643 qdev_prop_set_drive_err(flash_dev, "drive",
644 blk_by_legacy_dinfo(dinfo),
647 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
649 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
650 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
652 /* Connect an SD card to SPI2 */
653 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
655 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
656 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
659 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
661 SiFiveUState *s = RISCV_U_MACHINE(obj);
663 return s->start_in_flash;
666 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
668 SiFiveUState *s = RISCV_U_MACHINE(obj);
670 s->start_in_flash = value;
673 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
674 const char *name, void *opaque,
677 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
680 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
681 const char *name, void *opaque,
684 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
687 static void sifive_u_machine_instance_init(Object *obj)
689 SiFiveUState *s = RISCV_U_MACHINE(obj);
691 s->start_in_flash = false;
693 object_property_add(obj, "msel", "uint32",
694 sifive_u_machine_get_uint32_prop,
695 sifive_u_machine_set_uint32_prop, NULL, &s->msel);
696 object_property_set_description(obj, "msel",
697 "Mode Select (MSEL[3:0]) pin state");
699 s->serial = OTP_SERIAL;
700 object_property_add(obj, "serial", "uint32",
701 sifive_u_machine_get_uint32_prop,
702 sifive_u_machine_set_uint32_prop, NULL, &s->serial);
703 object_property_set_description(obj, "serial", "Board serial number");
706 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
708 MachineClass *mc = MACHINE_CLASS(oc);
710 mc->desc = "RISC-V Board compatible with SiFive U SDK";
711 mc->init = sifive_u_machine_init;
712 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
713 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
714 mc->default_cpu_type = SIFIVE_U_CPU;
715 mc->default_cpus = mc->min_cpus;
717 object_class_property_add_bool(oc, "start-in-flash",
718 sifive_u_machine_get_start_in_flash,
719 sifive_u_machine_set_start_in_flash);
720 object_class_property_set_description(oc, "start-in-flash",
721 "Set on to tell QEMU's ROM to jump to "
722 "flash. Otherwise QEMU will jump to DRAM "
723 "or L2LIM depending on the msel value");
726 static const TypeInfo sifive_u_machine_typeinfo = {
727 .name = MACHINE_TYPE_NAME("sifive_u"),
728 .parent = TYPE_MACHINE,
729 .class_init = sifive_u_machine_class_init,
730 .instance_init = sifive_u_machine_instance_init,
731 .instance_size = sizeof(SiFiveUState),
734 static void sifive_u_machine_init_register_types(void)
736 type_register_static(&sifive_u_machine_typeinfo);
739 type_init(sifive_u_machine_init_register_types)
741 static void sifive_u_soc_instance_init(Object *obj)
743 SiFiveUSoCState *s = RISCV_U_SOC(obj);
745 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
746 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
748 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
749 TYPE_RISCV_HART_ARRAY);
750 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
751 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
752 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
753 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
755 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
756 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
758 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
759 TYPE_RISCV_HART_ARRAY);
761 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
762 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
763 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
764 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
765 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
766 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
767 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
770 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
772 MachineState *ms = MACHINE(qdev_get_machine());
773 SiFiveUSoCState *s = RISCV_U_SOC(dev);
774 const MemMapEntry *memmap = sifive_u_memmap;
775 MemoryRegion *system_memory = get_system_memory();
776 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
777 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
778 char *plic_hart_config;
779 size_t plic_hart_config_len;
781 NICInfo *nd = &nd_table[0];
783 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
784 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
785 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
786 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
788 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
789 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
791 * The cluster must be realized after the RISC-V hart array container,
792 * as the container's CPU object is only created on realize, and the
793 * CPU must exist and have been parented into the cluster before the
794 * cluster is realized.
796 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
797 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
800 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
801 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
802 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
806 * Add L2-LIM at reset size.
807 * This should be reduced in size as the L2 Cache Controller WayEnable
808 * register is incremented. Unfortunately I don't see a nice (or any) way
809 * to handle reducing or blocking out the L2 LIM while still allowing it
810 * be re returned to all enabled after a reset. For the time being, just
811 * leave it enabled all the time. This won't break anything, but will be
812 * too generous to misbehaving guests.
814 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
815 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
816 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
819 /* create PLIC hart topology configuration string */
820 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
822 plic_hart_config = g_malloc0(plic_hart_config_len);
823 for (i = 0; i < ms->smp.cpus; i++) {
825 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
826 plic_hart_config_len);
828 strncat(plic_hart_config, "M", plic_hart_config_len);
830 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
834 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
835 plic_hart_config, ms->smp.cpus, 0,
836 SIFIVE_U_PLIC_NUM_SOURCES,
837 SIFIVE_U_PLIC_NUM_PRIORITIES,
838 SIFIVE_U_PLIC_PRIORITY_BASE,
839 SIFIVE_U_PLIC_PENDING_BASE,
840 SIFIVE_U_PLIC_ENABLE_BASE,
841 SIFIVE_U_PLIC_ENABLE_STRIDE,
842 SIFIVE_U_PLIC_CONTEXT_BASE,
843 SIFIVE_U_PLIC_CONTEXT_STRIDE,
844 memmap[SIFIVE_U_DEV_PLIC].size);
845 g_free(plic_hart_config);
846 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
847 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
848 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
849 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
850 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
851 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
852 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
853 CLINT_TIMEBASE_FREQ, false);
855 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
858 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
860 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
861 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
864 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
866 /* Pass all GPIOs to the SOC layer so they are available to the board */
867 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
869 /* Connect GPIO interrupts to the PLIC */
870 for (i = 0; i < 16; i++) {
871 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
872 qdev_get_gpio_in(DEVICE(s->plic),
873 SIFIVE_U_GPIO_IRQ0 + i));
877 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
878 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
880 /* Connect PDMA interrupts to the PLIC */
881 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
882 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
883 qdev_get_gpio_in(DEVICE(s->plic),
884 SIFIVE_U_PDMA_IRQ0 + i));
887 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
888 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
891 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
893 /* FIXME use qdev NIC properties instead of nd_table[] */
895 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
896 qdev_set_nic_properties(DEVICE(&s->gem), nd);
898 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
900 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
903 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
904 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
905 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
907 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
908 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
910 create_unimplemented_device("riscv.sifive.u.dmc",
911 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
913 create_unimplemented_device("riscv.sifive.u.l2cc",
914 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
916 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
917 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
918 memmap[SIFIVE_U_DEV_QSPI0].base);
919 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
920 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));
921 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
922 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
923 memmap[SIFIVE_U_DEV_QSPI2].base);
924 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
925 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
928 static Property sifive_u_soc_props[] = {
929 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
930 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
931 DEFINE_PROP_END_OF_LIST()
934 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
936 DeviceClass *dc = DEVICE_CLASS(oc);
938 device_class_set_props(dc, sifive_u_soc_props);
939 dc->realize = sifive_u_soc_realize;
940 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
941 dc->user_creatable = false;
944 static const TypeInfo sifive_u_soc_type_info = {
945 .name = TYPE_RISCV_U_SOC,
946 .parent = TYPE_DEVICE,
947 .instance_size = sizeof(SiFiveUSoCState),
948 .instance_init = sifive_u_soc_instance_init,
949 .class_init = sifive_u_soc_class_init,
952 static void sifive_u_soc_register_types(void)
954 type_register_static(&sifive_u_soc_type_info);
957 type_init(sifive_u_soc_register_types)