2 * OMAP on-chip MMC/SD host emulation.
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "hw/arm/omap.h"
51 uint16_t blen_counter;
53 uint16_t nblk_counter;
68 static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
70 qemu_set_irq(s->irq, !!(s->status & s->mask));
73 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
75 if (!host->transfer && !host->fifo_len) {
76 host->status &= 0xf3ff;
80 if (host->fifo_len > host->af_level && host->ddir) {
82 host->status &= 0xfbff;
83 qemu_irq_raise(host->dma[1]);
85 host->status |= 0x0400;
87 host->status &= 0xfbff;
88 qemu_irq_lower(host->dma[1]);
91 if (host->fifo_len < host->ae_level && !host->ddir) {
93 host->status &= 0xf7ff;
94 qemu_irq_raise(host->dma[0]);
96 host->status |= 0x0800;
98 qemu_irq_lower(host->dma[0]);
99 host->status &= 0xf7ff;
104 sd_nore = 0, /* no response */
105 sd_r1, /* normal response command */
106 sd_r2, /* CID, CSD registers */
107 sd_r3, /* OCR register */
108 sd_r6 = 6, /* Published RCA response */
112 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
113 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
115 uint32_t rspstatus, mask;
118 uint8_t response[16];
120 if (init && cmd == 0) {
121 host->status |= 0x0001;
125 if (resptype == sd_r1 && busy)
128 if (type == sd_adtc) {
129 host->fifo_start = 0;
140 request.arg = host->arg;
141 request.crc = 0; /* FIXME */
143 rsplen = sd_do_command(host->card, &request, response);
145 /* TODO: validate CRCs */
159 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
160 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
161 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
162 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
164 if (host->sdio & (1 << 13))
165 mask |= AKE_SEQ_ERROR;
166 rspstatus = ldl_be_p(response);
184 rspstatus = ldl_be_p(response);
185 if (rspstatus & 0x80000000)
186 host->status &= 0xe000;
188 host->status |= 0x1000;
198 mask = 0xe000 | AKE_SEQ_ERROR;
199 rspstatus = (response[2] << 8) | (response[3] << 0);
202 if (rspstatus & mask)
203 host->status |= 0x4000;
205 host->status &= 0xb000;
208 for (rsplen = 0; rsplen < 8; rsplen ++)
209 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
210 (response[(rsplen << 1) | 0] << 8);
213 host->status |= 0x0080;
215 host->status |= 0x0005; /* Makes it more real */
217 host->status |= 0x0001;
220 static void omap_mmc_transfer(struct omap_mmc_s *host)
229 if (host->fifo_len > host->af_level)
232 value = sd_read_data(host->card);
233 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
234 if (-- host->blen_counter) {
235 value = sd_read_data(host->card);
236 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
238 host->blen_counter --;
246 value = host->fifo[host->fifo_start] & 0xff;
247 sd_write_data(host->card, value);
248 if (-- host->blen_counter) {
249 value = host->fifo[host->fifo_start] >> 8;
250 sd_write_data(host->card, value);
251 host->blen_counter --;
256 host->fifo_start &= 31;
259 if (host->blen_counter == 0) {
260 host->nblk_counter --;
261 host->blen_counter = host->blen;
263 if (host->nblk_counter == 0) {
264 host->nblk_counter = host->nblk;
266 host->status |= 0x0008;
273 static void omap_mmc_update(void *opaque)
275 struct omap_mmc_s *s = opaque;
276 omap_mmc_transfer(s);
277 omap_mmc_fifolevel_update(s);
278 omap_mmc_interrupts_update(s);
281 void omap_mmc_reset(struct omap_mmc_s *host)
284 memset(host->rsp, 0, sizeof(host->rsp));
295 host->blen_counter = 0;
297 host->nblk_counter = 0;
300 host->ae_level = 0x00;
301 host->af_level = 0x1f;
303 host->cdet_wakeup = 0;
304 host->cdet_enable = 0;
305 qemu_set_irq(host->coverswitch, host->cdet_state);
308 /* Since we're still using the legacy SD API the card is not plugged
309 * into any bus, and we must reset it manually. When omap_mmc is
310 * QOMified this must move into the QOM reset function.
312 device_reset(DEVICE(host->card));
315 static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
319 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
322 return omap_badwidth_read16(opaque, offset);
326 case 0x00: /* MMC_CMD */
329 case 0x04: /* MMC_ARGL */
330 return s->arg & 0x0000ffff;
332 case 0x08: /* MMC_ARGH */
335 case 0x0c: /* MMC_CON */
336 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
337 (s->be << 10) | s->clkdiv;
339 case 0x10: /* MMC_STAT */
342 case 0x14: /* MMC_IE */
345 case 0x18: /* MMC_CTO */
348 case 0x1c: /* MMC_DTO */
351 case 0x20: /* MMC_DATA */
352 /* TODO: support 8-bit access */
353 i = s->fifo[s->fifo_start];
354 if (s->fifo_len == 0) {
355 printf("MMC: FIFO underrun\n");
361 omap_mmc_transfer(s);
362 omap_mmc_fifolevel_update(s);
363 omap_mmc_interrupts_update(s);
366 case 0x24: /* MMC_BLEN */
367 return s->blen_counter;
369 case 0x28: /* MMC_NBLK */
370 return s->nblk_counter;
372 case 0x2c: /* MMC_BUF */
373 return (s->rx_dma << 15) | (s->af_level << 8) |
374 (s->tx_dma << 7) | s->ae_level;
376 case 0x30: /* MMC_SPI */
378 case 0x34: /* MMC_SDIO */
379 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
380 case 0x38: /* MMC_SYST */
383 case 0x3c: /* MMC_REV */
386 case 0x40: /* MMC_RSP0 */
387 case 0x44: /* MMC_RSP1 */
388 case 0x48: /* MMC_RSP2 */
389 case 0x4c: /* MMC_RSP3 */
390 case 0x50: /* MMC_RSP4 */
391 case 0x54: /* MMC_RSP5 */
392 case 0x58: /* MMC_RSP6 */
393 case 0x5c: /* MMC_RSP7 */
394 return s->rsp[(offset - 0x40) >> 2];
397 case 0x60: /* MMC_IOSR */
398 case 0x64: /* MMC_SYSC */
400 case 0x68: /* MMC_SYSS */
404 OMAP_BAD_REG(offset);
408 static void omap_mmc_write(void *opaque, hwaddr offset,
409 uint64_t value, unsigned size)
412 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
415 omap_badwidth_write16(opaque, offset, value);
420 case 0x00: /* MMC_CMD */
425 for (i = 0; i < 8; i ++)
427 omap_mmc_command(s, value & 63, (value >> 15) & 1,
428 (sd_cmd_type_t) ((value >> 12) & 3),
430 (sd_rsp_type_t) ((value >> 8) & 7),
435 case 0x04: /* MMC_ARGL */
436 s->arg &= 0xffff0000;
437 s->arg |= 0x0000ffff & value;
440 case 0x08: /* MMC_ARGH */
441 s->arg &= 0x0000ffff;
442 s->arg |= value << 16;
445 case 0x0c: /* MMC_CON */
446 s->dw = (value >> 15) & 1;
447 s->mode = (value >> 12) & 3;
448 s->enable = (value >> 11) & 1;
449 s->be = (value >> 10) & 1;
450 s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
452 qemu_log_mask(LOG_UNIMP,
453 "omap_mmc_wr: mode #%i unimplemented\n", s->mode);
456 qemu_log_mask(LOG_UNIMP,
457 "omap_mmc_wr: Big Endian not implemented\n");
459 if (s->dw != 0 && s->lines < 4)
460 printf("4-bit SD bus enabled\n");
465 case 0x10: /* MMC_STAT */
467 omap_mmc_interrupts_update(s);
470 case 0x14: /* MMC_IE */
471 s->mask = value & 0x7fff;
472 omap_mmc_interrupts_update(s);
475 case 0x18: /* MMC_CTO */
476 s->cto = value & 0xff;
477 if (s->cto > 0xfd && s->rev <= 1)
478 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
481 case 0x1c: /* MMC_DTO */
482 s->dto = value & 0xffff;
485 case 0x20: /* MMC_DATA */
486 /* TODO: support 8-bit access */
487 if (s->fifo_len == 32)
489 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
491 omap_mmc_transfer(s);
492 omap_mmc_fifolevel_update(s);
493 omap_mmc_interrupts_update(s);
496 case 0x24: /* MMC_BLEN */
497 s->blen = (value & 0x07ff) + 1;
498 s->blen_counter = s->blen;
501 case 0x28: /* MMC_NBLK */
502 s->nblk = (value & 0x07ff) + 1;
503 s->nblk_counter = s->nblk;
504 s->blen_counter = s->blen;
507 case 0x2c: /* MMC_BUF */
508 s->rx_dma = (value >> 15) & 1;
509 s->af_level = (value >> 8) & 0x1f;
510 s->tx_dma = (value >> 7) & 1;
511 s->ae_level = value & 0x1f;
517 omap_mmc_fifolevel_update(s);
518 omap_mmc_interrupts_update(s);
521 /* SPI, SDIO and TEST modes unimplemented */
522 case 0x30: /* MMC_SPI (OMAP1 only) */
524 case 0x34: /* MMC_SDIO */
525 s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
526 s->cdet_wakeup = (value >> 9) & 1;
527 s->cdet_enable = (value >> 2) & 1;
529 case 0x38: /* MMC_SYST */
532 case 0x3c: /* MMC_REV */
533 case 0x40: /* MMC_RSP0 */
534 case 0x44: /* MMC_RSP1 */
535 case 0x48: /* MMC_RSP2 */
536 case 0x4c: /* MMC_RSP3 */
537 case 0x50: /* MMC_RSP4 */
538 case 0x54: /* MMC_RSP5 */
539 case 0x58: /* MMC_RSP6 */
540 case 0x5c: /* MMC_RSP7 */
545 case 0x60: /* MMC_IOSR */
547 printf("MMC: SDIO bits used!\n");
549 case 0x64: /* MMC_SYSC */
550 if (value & (1 << 2)) /* SRTS */
553 case 0x68: /* MMC_SYSS */
558 OMAP_BAD_REG(offset);
562 static const MemoryRegionOps omap_mmc_ops = {
563 .read = omap_mmc_read,
564 .write = omap_mmc_write,
565 .endianness = DEVICE_NATIVE_ENDIAN,
568 static void omap_mmc_cover_cb(void *opaque, int line, int level)
570 struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
572 if (!host->cdet_state && level) {
573 host->status |= 0x0002;
574 omap_mmc_interrupts_update(host);
575 if (host->cdet_wakeup) {
576 /* TODO: Assert wake-up */
580 if (host->cdet_state != level) {
581 qemu_set_irq(host->coverswitch, level);
582 host->cdet_state = level;
586 struct omap_mmc_s *omap_mmc_init(hwaddr base,
587 MemoryRegion *sysmem,
589 qemu_irq irq, qemu_irq dma[], omap_clk clk)
591 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
596 s->lines = 1; /* TODO: needs to be settable per-board */
599 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
600 memory_region_add_subregion(sysmem, base, &s->iomem);
602 /* Instantiate the storage */
603 s->card = sd_init(blk, false);
604 if (s->card == NULL) {
613 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
614 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
615 omap_clk fclk, omap_clk iclk)
617 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
625 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
626 omap_l4_region_size(ta, 0));
627 omap_l4_attach(ta, 0, &s->iomem);
629 /* Instantiate the storage */
630 s->card = sd_init(blk, false);
631 if (s->card == NULL) {
635 s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
636 sd_set_cb(s->card, NULL, s->cdet);
643 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
646 sd_set_cb(s->card, ro, s->cdet);
647 s->coverswitch = cover;
648 qemu_set_irq(cover, s->cdet_state);
650 sd_set_cb(s->card, ro, cover);
653 void omap_mmc_enable(struct omap_mmc_s *s, int enable)
655 sd_enable(s->card, enable);