i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <assert.h>
  10 #include <errno.h>
  11 #include <i915_drm.h>
  12 #include <stdbool.h>
  13 #include <stdio.h>
  14 #include <string.h>
  15 #include <sys/mman.h>
  16 #include <unistd.h>
  17 #include <xf86drm.h>
  18
  19 #include "drv_priv.h"
  20 #include "helpers.h"
  21 #include "util.h"
  22
  23 #define I915_CACHELINE_SIZE 64
  24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  25
  26 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR16161616F, DRM_FORMAT_ABGR2101010,
  27                                                   DRM_FORMAT_ABGR8888,      DRM_FORMAT_ARGB1555,
  28                                                   DRM_FORMAT_ARGB2101010,   DRM_FORMAT_ARGB8888,
  29                                                   DRM_FORMAT_RGB565,        DRM_FORMAT_XBGR2101010,
  30                                                   DRM_FORMAT_XBGR8888,      DRM_FORMAT_XRGB1555,
  31                                                   DRM_FORMAT_XRGB2101010,   DRM_FORMAT_XRGB8888 };
  32
  33 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
  34                                                             DRM_FORMAT_UYVY, DRM_FORMAT_YUYV };
  35
  36 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID,
  37                                                    DRM_FORMAT_NV12, DRM_FORMAT_P010 };
  38
  39 struct i915_device {
  40         uint32_t gen;
  41         int32_t has_llc;
  42 };
  43
  44 static uint32_t i915_get_gen(int device_id)
  45 {
  46         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  47                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  48         unsigned i;
  49         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  50                 if (gen3_ids[i] == device_id)
  51                         return 3;
  52
  53         return 4;
  54 }
  55
  56 /*
  57  * We allow allocation of ARGB formats for SCANOUT if the corresponding XRGB
  58  * formats supports it. It's up to the caller (chrome ozone) to ultimately not
  59  * scan out ARGB if the display controller only supports XRGB, but we'll allow
  60  * the allocation of the bo here.
  61  */
  62 static bool format_compatible(const struct combination *combo, uint32_t format)
  63 {
  64         if (combo->format == format)
  65                 return true;
  66
  67         switch (format) {
  68         case DRM_FORMAT_XRGB8888:
  69                 return combo->format == DRM_FORMAT_ARGB8888;
  70         case DRM_FORMAT_XBGR8888:
  71                 return combo->format == DRM_FORMAT_ABGR8888;
  72         case DRM_FORMAT_RGBX8888:
  73                 return combo->format == DRM_FORMAT_RGBA8888;
  74         case DRM_FORMAT_BGRX8888:
  75                 return combo->format == DRM_FORMAT_BGRA8888;
  76         case DRM_FORMAT_XRGB2101010:
  77                 return combo->format == DRM_FORMAT_ARGB2101010;
  78         case DRM_FORMAT_XBGR2101010:
  79                 return combo->format == DRM_FORMAT_ABGR2101010;
  80         default:
  81                 return false;
  82         }
  83 }
  84
  85 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
  86 {
  87         uint32_t i;
  88         struct combination *combo;
  89
  90         /*
  91          * Older hardware can't scanout Y-tiled formats. Newer devices can, and
  92          * report this functionality via format modifiers.
  93          */
  94         for (i = 0; i < drv_array_size(drv->combos); i++) {
  95                 combo = (struct combination *)drv_array_at_idx(drv->combos, i);
  96                 if (!format_compatible(combo, item->format))
  97                         continue;
  98
  99                 if (item->modifier == DRM_FORMAT_MOD_LINEAR &&
 100                     combo->metadata.tiling == I915_TILING_X) {
 101                         /*
 102                          * FIXME: drv_query_kms() does not report the available modifiers
 103                          * yet, but we know that all hardware can scanout from X-tiled
 104                          * buffers, so let's add this to our combinations, except for
 105                          * cursor, which must not be tiled.
 106                          */
 107                         combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
 108                 }
 109
 110                 /* If we can scanout NV12, we support all tiling modes. */
 111                 if (item->format == DRM_FORMAT_NV12)
 112                         combo->use_flags |= item->use_flags;
 113
 114                 if (combo->metadata.modifier == item->modifier)
 115                         combo->use_flags |= item->use_flags;
 116         }
 117
 118         return 0;
 119 }
 120
 121 static int i915_add_combinations(struct driver *drv)
 122 {
 123         int ret;
 124         uint32_t i;
 125         struct drv_array *kms_items;
 126         struct format_metadata metadata;
 127         uint64_t render_use_flags, texture_use_flags;
 128
 129         render_use_flags = BO_USE_RENDER_MASK;
 130         texture_use_flags = BO_USE_TEXTURE_MASK;
 131
 132         metadata.tiling = I915_TILING_NONE;
 133         metadata.priority = 1;
 134         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 135
 136         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 137                              &metadata, render_use_flags);
 138
 139         drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 140                              &metadata, texture_use_flags);
 141
 142         drv_add_combinations(drv, tileable_texture_source_formats,
 143                              ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 144                              texture_use_flags);
 145
 146         /*
 147          * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
 148          * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
 149          */
 150         drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
 151         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 152                                BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER);
 153
 154         /* Android CTS tests require this. */
 155         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
 156
 157         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 158         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 159
 160         /* IPU3 camera ISP supports only NV12 output. */
 161         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 162                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 163         /*
 164          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 165          * from camera.
 166          */
 167         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 168                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 169
 170         render_use_flags &= ~BO_USE_RENDERSCRIPT;
 171         render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 172         render_use_flags &= ~BO_USE_SW_READ_OFTEN;
 173         render_use_flags &= ~BO_USE_LINEAR;
 174         render_use_flags &= ~BO_USE_PROTECTED;
 175
 176         texture_use_flags &= ~BO_USE_RENDERSCRIPT;
 177         texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 178         texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
 179         texture_use_flags &= ~BO_USE_LINEAR;
 180         texture_use_flags &= ~BO_USE_PROTECTED;
 181
 182         metadata.tiling = I915_TILING_X;
 183         metadata.priority = 2;
 184         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 185
 186         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 187                              &metadata, render_use_flags);
 188
 189         drv_add_combinations(drv, tileable_texture_source_formats,
 190                              ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 191                              texture_use_flags);
 192
 193         metadata.tiling = I915_TILING_Y;
 194         metadata.priority = 3;
 195         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 196
 197         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 198                              &metadata, render_use_flags);
 199
 200         drv_add_combinations(drv, tileable_texture_source_formats,
 201                              ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 202                              texture_use_flags);
 203
 204         /* Support y-tiled NV12 and P010 for libva */
 205         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 206                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 207         drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
 208                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 209
 210         kms_items = drv_query_kms(drv);
 211         if (!kms_items)
 212                 return 0;
 213
 214         for (i = 0; i < drv_array_size(kms_items); i++) {
 215                 ret = i915_add_kms_item(drv, (struct kms_item *)drv_array_at_idx(kms_items, i));
 216                 if (ret) {
 217                         drv_array_destroy(kms_items);
 218                         return ret;
 219                 }
 220         }
 221
 222         drv_array_destroy(kms_items);
 223         return 0;
 224 }
 225
 226 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 227                                  uint32_t *aligned_height)
 228 {
 229         struct i915_device *i915 = bo->drv->priv;
 230         uint32_t horizontal_alignment;
 231         uint32_t vertical_alignment;
 232
 233         switch (tiling) {
 234         default:
 235         case I915_TILING_NONE:
 236                 /*
 237                  * The Intel GPU doesn't need any alignment in linear mode,
 238                  * but libva requires the allocation stride to be aligned to
 239                  * 16 bytes and height to 4 rows. Further, we round up the
 240                  * horizontal alignment so that row start on a cache line (64
 241                  * bytes).
 242                  */
 243                 horizontal_alignment = 64;
 244                 vertical_alignment = 4;
 245                 break;
 246
 247         case I915_TILING_X:
 248                 horizontal_alignment = 512;
 249                 vertical_alignment = 8;
 250                 break;
 251
 252         case I915_TILING_Y:
 253                 if (i915->gen == 3) {
 254                         horizontal_alignment = 512;
 255                         vertical_alignment = 8;
 256                 } else {
 257                         horizontal_alignment = 128;
 258                         vertical_alignment = 32;
 259                 }
 260                 break;
 261         }
 262
 263         *aligned_height = ALIGN(*aligned_height, vertical_alignment);
 264         if (i915->gen > 3) {
 265                 *stride = ALIGN(*stride, horizontal_alignment);
 266         } else {
 267                 while (*stride > horizontal_alignment)
 268                         horizontal_alignment <<= 1;
 269
 270                 *stride = horizontal_alignment;
 271         }
 272
 273         if (i915->gen <= 3 && *stride > 8192)
 274                 return -EINVAL;
 275
 276         return 0;
 277 }
 278
 279 static void i915_clflush(void *start, size_t size)
 280 {
 281         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 282         void *end = (void *)((uintptr_t)start + size);
 283
 284         __builtin_ia32_mfence();
 285         while (p < end) {
 286                 __builtin_ia32_clflush(p);
 287                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 288         }
 289 }
 290
 291 static int i915_init(struct driver *drv)
 292 {
 293         int ret;
 294         int device_id;
 295         struct i915_device *i915;
 296         drm_i915_getparam_t get_param;
 297
 298         i915 = calloc(1, sizeof(*i915));
 299         if (!i915)
 300                 return -ENOMEM;
 301
 302         memset(&get_param, 0, sizeof(get_param));
 303         get_param.param = I915_PARAM_CHIPSET_ID;
 304         get_param.value = &device_id;
 305         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 306         if (ret) {
 307                 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
 308                 free(i915);
 309                 return -EINVAL;
 310         }
 311
 312         i915->gen = i915_get_gen(device_id);
 313
 314         memset(&get_param, 0, sizeof(get_param));
 315         get_param.param = I915_PARAM_HAS_LLC;
 316         get_param.value = &i915->has_llc;
 317         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 318         if (ret) {
 319                 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
 320                 free(i915);
 321                 return -EINVAL;
 322         }
 323
 324         drv->priv = i915;
 325
 326         return i915_add_combinations(drv);
 327 }
 328
 329 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
 330 {
 331         uint32_t offset;
 332         size_t plane;
 333         int ret, pagesize;
 334
 335         offset = 0;
 336         pagesize = getpagesize();
 337         for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
 338                 uint32_t stride = drv_stride_from_format(format, width, plane);
 339                 uint32_t plane_height = drv_height_from_format(format, height, plane);
 340
 341                 if (bo->meta.tiling != I915_TILING_NONE)
 342                         assert(IS_ALIGNED(offset, pagesize));
 343
 344                 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
 345                 if (ret)
 346                         return ret;
 347
 348                 bo->meta.strides[plane] = stride;
 349                 bo->meta.sizes[plane] = stride * plane_height;
 350                 bo->meta.offsets[plane] = offset;
 351                 offset += bo->meta.sizes[plane];
 352         }
 353
 354         bo->meta.total_size = ALIGN(offset, pagesize);
 355
 356         return 0;
 357 }
 358
 359 static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
 360                                        uint32_t format, uint64_t modifier)
 361 {
 362         int ret;
 363         size_t plane;
 364         struct drm_i915_gem_create gem_create;
 365         struct drm_i915_gem_set_tiling gem_set_tiling;
 366
 367         switch (modifier) {
 368         case DRM_FORMAT_MOD_LINEAR:
 369                 bo->meta.tiling = I915_TILING_NONE;
 370                 break;
 371         case I915_FORMAT_MOD_X_TILED:
 372                 bo->meta.tiling = I915_TILING_X;
 373                 break;
 374         case I915_FORMAT_MOD_Y_TILED:
 375                 bo->meta.tiling = I915_TILING_Y;
 376                 break;
 377         }
 378
 379         bo->meta.format_modifiers[0] = modifier;
 380
 381         if (format == DRM_FORMAT_YVU420_ANDROID) {
 382                 /*
 383                  * We only need to be able to use this as a linear texture,
 384                  * which doesn't put any HW restrictions on how we lay it
 385                  * out. The Android format does require the stride to be a
 386                  * multiple of 16 and expects the Cr and Cb stride to be
 387                  * ALIGN(Y_stride / 2, 16), which we can make happen by
 388                  * aligning to 32 bytes here.
 389                  */
 390                 uint32_t stride = ALIGN(width, 32);
 391                 drv_bo_from_format(bo, stride, height, format);
 392         } else {
 393                 i915_bo_from_format(bo, width, height, format);
 394         }
 395
 396         memset(&gem_create, 0, sizeof(gem_create));
 397         gem_create.size = bo->meta.total_size;
 398
 399         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 400         if (ret) {
 401                 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
 402                 return -errno;
 403         }
 404
 405         for (plane = 0; plane < bo->meta.num_planes; plane++)
 406                 bo->handles[plane].u32 = gem_create.handle;
 407
 408         memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
 409         gem_set_tiling.handle = bo->handles[0].u32;
 410         gem_set_tiling.tiling_mode = bo->meta.tiling;
 411         gem_set_tiling.stride = bo->meta.strides[0];
 412
 413         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 414         if (ret) {
 415                 struct drm_gem_close gem_close;
 416                 memset(&gem_close, 0, sizeof(gem_close));
 417                 gem_close.handle = bo->handles[0].u32;
 418                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 419
 420                 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
 421                 return -errno;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 428                           uint64_t use_flags)
 429 {
 430         struct combination *combo;
 431
 432         combo = drv_get_combination(bo->drv, format, use_flags);
 433         if (!combo)
 434                 return -EINVAL;
 435
 436         return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
 437 }
 438
 439 static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
 440                                          uint32_t format, const uint64_t *modifiers, uint32_t count)
 441 {
 442         static const uint64_t modifier_order[] = {
 443                 I915_FORMAT_MOD_Y_TILED,
 444                 I915_FORMAT_MOD_X_TILED,
 445                 DRM_FORMAT_MOD_LINEAR,
 446         };
 447         uint64_t modifier;
 448
 449         modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
 450
 451         return i915_bo_create_for_modifier(bo, width, height, format, modifier);
 452 }
 453
 454 static void i915_close(struct driver *drv)
 455 {
 456         free(drv->priv);
 457         drv->priv = NULL;
 458 }
 459
 460 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 461 {
 462         int ret;
 463         struct drm_i915_gem_get_tiling gem_get_tiling;
 464
 465         ret = drv_prime_bo_import(bo, data);
 466         if (ret)
 467                 return ret;
 468
 469         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 470         memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
 471         gem_get_tiling.handle = bo->handles[0].u32;
 472
 473         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 474         if (ret) {
 475                 drv_gem_bo_destroy(bo);
 476                 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
 477                 return ret;
 478         }
 479
 480         bo->meta.tiling = gem_get_tiling.tiling_mode;
 481         return 0;
 482 }
 483
 484 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 485 {
 486         int ret;
 487         void *addr;
 488
 489         if (bo->meta.tiling == I915_TILING_NONE) {
 490                 struct drm_i915_gem_mmap gem_map;
 491                 memset(&gem_map, 0, sizeof(gem_map));
 492
 493                 /* TODO(b/118799155): We don't seem to have a good way to
 494                  * detect the use cases for which WC mapping is really needed.
 495                  * The current heuristic seems overly coarse and may be slowing
 496                  * down some other use cases unnecessarily.
 497                  *
 498                  * For now, care must be taken not to use WC mappings for
 499                  * Renderscript and camera use cases, as they're
 500                  * performance-sensitive. */
 501                 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
 502                     !(bo->meta.use_flags &
 503                       (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
 504                         gem_map.flags = I915_MMAP_WC;
 505
 506                 gem_map.handle = bo->handles[0].u32;
 507                 gem_map.offset = 0;
 508                 gem_map.size = bo->meta.total_size;
 509
 510                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 511                 if (ret) {
 512                         drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
 513                         return MAP_FAILED;
 514                 }
 515
 516                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 517         } else {
 518                 struct drm_i915_gem_mmap_gtt gem_map;
 519                 memset(&gem_map, 0, sizeof(gem_map));
 520
 521                 gem_map.handle = bo->handles[0].u32;
 522
 523                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 524                 if (ret) {
 525                         drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 526                         return MAP_FAILED;
 527                 }
 528
 529                 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
 530                             bo->drv->fd, gem_map.offset);
 531         }
 532
 533         if (addr == MAP_FAILED) {
 534                 drv_log("i915 GEM mmap failed\n");
 535                 return addr;
 536         }
 537
 538         vma->length = bo->meta.total_size;
 539         return addr;
 540 }
 541
 542 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
 543 {
 544         int ret;
 545         struct drm_i915_gem_set_domain set_domain;
 546
 547         memset(&set_domain, 0, sizeof(set_domain));
 548         set_domain.handle = bo->handles[0].u32;
 549         if (bo->meta.tiling == I915_TILING_NONE) {
 550                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 551                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 552                         set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 553         } else {
 554                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 555                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 556                         set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 557         }
 558
 559         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 560         if (ret) {
 561                 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
 562                 return ret;
 563         }
 564
 565         return 0;
 566 }
 567
 568 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
 569 {
 570         struct i915_device *i915 = bo->drv->priv;
 571         if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
 572                 i915_clflush(mapping->vma->addr, mapping->vma->length);
 573
 574         return 0;
 575 }
 576
 577 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 578 {
 579         switch (format) {
 580         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 581                 /* KBL camera subsystem requires NV12. */
 582                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 583                         return DRM_FORMAT_NV12;
 584                 /*HACK: See b/28671744 */
 585                 return DRM_FORMAT_XBGR8888;
 586         case DRM_FORMAT_FLEX_YCbCr_420_888:
 587                 /*
 588                  * KBL camera subsystem requires NV12. Our other use cases
 589                  * don't care:
 590                  * - Hardware video supports NV12,
 591                  * - USB Camera HALv3 supports NV12,
 592                  * - USB Camera HALv1 doesn't use this format.
 593                  * Moreover, NV12 is preferred for video, due to overlay
 594                  * support on SKL+.
 595                  */
 596                 return DRM_FORMAT_NV12;
 597         default:
 598                 return format;
 599         }
 600 }
 601
 602 const struct backend backend_i915 = {
 603         .name = "i915",
 604         .init = i915_init,
 605         .close = i915_close,
 606         .bo_create = i915_bo_create,
 607         .bo_create_with_modifiers = i915_bo_create_with_modifiers,
 608         .bo_destroy = drv_gem_bo_destroy,
 609         .bo_import = i915_bo_import,
 610         .bo_map = i915_bo_map,
 611         .bo_unmap = drv_bo_munmap,
 612         .bo_invalidate = i915_bo_invalidate,
 613         .bo_flush = i915_bo_flush,
 614         .resolve_format = i915_resolve_format,
 615 };
 616
 617 #endif