2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
19 #include "i915_private.h"
21 #define I915_CACHELINE_SIZE 64
22 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
24 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB1555,
25 DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
26 DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888,
27 DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB2101010,
28 DRM_FORMAT_XRGB8888 };
30 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12,
31 DRM_FORMAT_R8, DRM_FORMAT_UYVY,
32 DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, DRM_FORMAT_VYUY };
34 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
39 uint64_t cursor_width;
40 uint64_t cursor_height;
43 static uint32_t i915_get_gen(int device_id)
45 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
46 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
48 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
49 if (gen3_ids[i] == device_id)
55 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
58 struct combination *combo;
61 * Older hardware can't scanout Y-tiled formats. Newer devices can, and
62 * report this functionality via format modifiers.
64 for (i = 0; i < drv->combos.size; i++) {
65 combo = &drv->combos.data[i];
66 if (combo->format != item->format)
69 if (item->modifier == DRM_FORMAT_MOD_INVALID &&
70 combo->metadata.tiling == I915_TILING_X) {
72 * FIXME: drv_query_kms() does not report the available modifiers
73 * yet, but we know that all hardware can scanout from X-tiled
74 * buffers, so let's add this to our combinations, except for
75 * cursor, which must not be tiled.
77 combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
80 if (combo->metadata.modifier == item->modifier)
81 combo->use_flags |= item->use_flags;
87 static int i915_add_combinations(struct driver *drv)
90 uint32_t i, num_items;
91 struct kms_item *items;
92 struct format_metadata metadata;
93 uint64_t render_use_flags, texture_use_flags;
95 render_use_flags = BO_USE_RENDER_MASK;
96 texture_use_flags = BO_USE_TEXTURE_MASK;
98 metadata.tiling = I915_TILING_NONE;
99 metadata.priority = 1;
100 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
102 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
103 &metadata, render_use_flags);
107 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
108 &metadata, texture_use_flags);
112 ret = drv_add_combinations(drv, tileable_texture_source_formats,
113 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
118 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
119 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
121 /* IPU3 camera ISP supports only NV12 output. */
122 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
123 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
125 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
128 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
129 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
131 render_use_flags &= ~BO_USE_RENDERSCRIPT;
132 render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
133 render_use_flags &= ~BO_USE_SW_READ_OFTEN;
134 render_use_flags &= ~BO_USE_LINEAR;
136 texture_use_flags &= ~BO_USE_RENDERSCRIPT;
137 texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
138 texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
139 texture_use_flags &= ~BO_USE_LINEAR;
141 metadata.tiling = I915_TILING_X;
142 metadata.priority = 2;
143 metadata.modifier = I915_FORMAT_MOD_X_TILED;
145 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
146 &metadata, render_use_flags);
150 ret = drv_add_combinations(drv, tileable_texture_source_formats,
151 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
156 metadata.tiling = I915_TILING_Y;
157 metadata.priority = 3;
158 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
160 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
161 &metadata, render_use_flags);
165 ret = drv_add_combinations(drv, tileable_texture_source_formats,
166 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
171 i915_private_add_combinations(drv);
173 items = drv_query_kms(drv, &num_items);
174 if (!items || !num_items)
177 for (i = 0; i < num_items; i++) {
178 ret = i915_add_kms_item(drv, &items[i]);
189 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
190 uint32_t *aligned_height)
192 struct i915_device *i915 = bo->drv->priv;
193 uint32_t horizontal_alignment = 4;
194 uint32_t vertical_alignment = 4;
198 case I915_TILING_NONE:
199 horizontal_alignment = 64;
203 horizontal_alignment = 512;
204 vertical_alignment = 8;
208 if (i915->gen == 3) {
209 horizontal_alignment = 512;
210 vertical_alignment = 8;
212 horizontal_alignment = 128;
213 vertical_alignment = 32;
219 * The alignment calculated above is based on the full size luma plane and to have chroma
220 * planes properly aligned with subsampled formats, we need to multiply luma alignment by
221 * subsampling factor.
223 switch (bo->format) {
224 case DRM_FORMAT_YVU420_ANDROID:
225 case DRM_FORMAT_YVU420:
226 horizontal_alignment *= 2;
228 case DRM_FORMAT_NV12:
229 vertical_alignment *= 2;
233 i915_private_align_dimensions(bo->format, &vertical_alignment);
235 *aligned_height = ALIGN(bo->height, vertical_alignment);
237 *stride = ALIGN(*stride, horizontal_alignment);
239 while (*stride > horizontal_alignment)
240 horizontal_alignment <<= 1;
242 *stride = horizontal_alignment;
245 if (i915->gen <= 3 && *stride > 8192)
251 static void i915_clflush(void *start, size_t size)
253 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
254 void *end = (void *)((uintptr_t)start + size);
256 __builtin_ia32_mfence();
258 __builtin_ia32_clflush(p);
259 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
263 static int i915_init(struct driver *drv)
267 struct i915_device *i915;
268 drm_i915_getparam_t get_param;
270 i915 = calloc(1, sizeof(*i915));
274 memset(&get_param, 0, sizeof(get_param));
275 get_param.param = I915_PARAM_CHIPSET_ID;
276 get_param.value = &device_id;
277 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
279 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
284 i915->gen = i915_get_gen(device_id);
286 memset(&get_param, 0, sizeof(get_param));
287 get_param.param = I915_PARAM_HAS_LLC;
288 get_param.value = &i915->has_llc;
289 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
291 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
298 i915_private_init(drv, &i915->cursor_width, &i915->cursor_height);
300 return i915_add_combinations(drv);
303 static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
304 uint32_t format, uint64_t modifier)
309 struct drm_i915_gem_create gem_create;
310 struct drm_i915_gem_set_tiling gem_set_tiling;
311 struct i915_device *i915_dev = (struct i915_device *)bo->drv->priv;
314 case DRM_FORMAT_MOD_LINEAR:
315 bo->tiling = I915_TILING_NONE;
317 case I915_FORMAT_MOD_X_TILED:
318 bo->tiling = I915_TILING_X;
320 case I915_FORMAT_MOD_Y_TILED:
321 bo->tiling = I915_TILING_Y;
325 stride = drv_stride_from_format(format, width, 0);
328 * Align cursor width and height to values expected by Intel
331 if (bo->use_flags & BO_USE_CURSOR) {
332 width = ALIGN(width, i915_dev->cursor_width);
333 height = ALIGN(height, i915_dev->cursor_height);
334 stride = drv_stride_from_format(format, width, 0);
336 ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
342 * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep
343 * total size as with aligned height to ensure enough padding space after each plane to
344 * satisfy GPU alignment requirements.
346 * We do it by first calling drv_bo_from_format() with aligned height and
347 * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates
348 * and then calling it again with requested parameters.
350 * This relies on the fact that i965 driver uses separate surfaces for each plane and
351 * contents of padding bytes is not affected, as it is only used to satisfy GPU cache
354 * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside
355 * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8.
357 if (format == DRM_FORMAT_YVU420_ANDROID) {
358 uint32_t unaligned_height = bo->height;
361 drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420);
362 total_size = bo->total_size;
363 drv_bo_from_format(bo, stride, unaligned_height, format);
364 bo->total_size = total_size;
366 drv_bo_from_format(bo, stride, height, format);
370 * Quoting Mesa ISL library:
372 * - For linear surfaces, additional padding of 64 bytes is required at
373 * the bottom of the surface. This is in addition to the padding
376 if (bo->tiling == I915_TILING_NONE)
377 bo->total_size += 64;
380 * Ensure we pass aligned width/height.
385 memset(&gem_create, 0, sizeof(gem_create));
386 gem_create.size = bo->total_size;
388 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
390 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
395 for (plane = 0; plane < bo->num_planes; plane++)
396 bo->handles[plane].u32 = gem_create.handle;
398 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
399 gem_set_tiling.handle = bo->handles[0].u32;
400 gem_set_tiling.tiling_mode = bo->tiling;
401 gem_set_tiling.stride = bo->strides[0];
403 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
405 struct drm_gem_close gem_close;
406 memset(&gem_close, 0, sizeof(gem_close));
407 gem_close.handle = bo->handles[0].u32;
408 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
410 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
417 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
420 struct combination *combo;
422 combo = drv_get_combination(bo->drv, format, use_flags);
426 return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
429 static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
430 uint32_t format, const uint64_t *modifiers, uint32_t count)
432 static const uint64_t modifier_order[] = {
433 I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR,
437 modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
439 bo->format_modifiers[0] = modifier;
441 return i915_bo_create_for_modifier(bo, width, height, format, modifier);
444 static void i915_close(struct driver *drv)
450 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
453 struct drm_i915_gem_get_tiling gem_get_tiling;
455 ret = drv_prime_bo_import(bo, data);
459 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
460 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
461 gem_get_tiling.handle = bo->handles[0].u32;
463 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
465 drv_gem_bo_destroy(bo);
466 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
470 bo->tiling = gem_get_tiling.tiling_mode;
474 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
479 if (bo->tiling == I915_TILING_NONE) {
480 struct drm_i915_gem_mmap gem_map;
481 memset(&gem_map, 0, sizeof(gem_map));
483 if ((bo->use_flags & BO_USE_SCANOUT) && !(bo->use_flags & BO_USE_RENDERSCRIPT))
484 gem_map.flags = I915_MMAP_WC;
486 gem_map.handle = bo->handles[0].u32;
488 gem_map.size = bo->total_size;
490 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
492 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
496 addr = (void *)(uintptr_t)gem_map.addr_ptr;
498 struct drm_i915_gem_mmap_gtt gem_map;
499 memset(&gem_map, 0, sizeof(gem_map));
501 gem_map.handle = bo->handles[0].u32;
503 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
505 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
509 addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
513 if (addr == MAP_FAILED) {
514 fprintf(stderr, "drv: i915 GEM mmap failed\n");
518 data->length = bo->total_size;
522 static int i915_bo_invalidate(struct bo *bo, struct map_info *data)
525 struct drm_i915_gem_set_domain set_domain;
527 memset(&set_domain, 0, sizeof(set_domain));
528 set_domain.handle = bo->handles[0].u32;
529 if (bo->tiling == I915_TILING_NONE) {
530 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
531 if (data->map_flags & BO_MAP_WRITE)
532 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
534 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
535 if (data->map_flags & BO_MAP_WRITE)
536 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
539 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
541 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
548 static int i915_bo_flush(struct bo *bo, struct map_info *data)
550 struct i915_device *i915 = bo->drv->priv;
551 if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
552 i915_clflush(data->addr, data->length);
557 static uint32_t i915_resolve_format(uint32_t format, uint64_t use_flags)
559 uint32_t resolved_format;
560 if (i915_private_resolve_format(format, use_flags, &resolved_format)) {
561 return resolved_format;
565 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
566 /* KBL camera subsystem requires NV12. */
567 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
568 return DRM_FORMAT_NV12;
569 /*HACK: See b/28671744 */
570 return DRM_FORMAT_XBGR8888;
571 case DRM_FORMAT_FLEX_YCbCr_420_888:
572 /* KBL camera subsystem requires NV12. */
573 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
574 return DRM_FORMAT_NV12;
575 return DRM_FORMAT_YVU420;
581 struct backend backend_i915 = {
585 .bo_create = i915_bo_create,
586 .bo_create_with_modifiers = i915_bo_create_with_modifiers,
587 .bo_destroy = drv_gem_bo_destroy,
588 .bo_import = i915_bo_import,
589 .bo_map = i915_bo_map,
590 .bo_unmap = drv_bo_munmap,
591 .bo_invalidate = i915_bo_invalidate,
592 .bo_flush = i915_bo_flush,
593 .resolve_format = i915_resolve_format,