i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <assert.h>
  10 #include <errno.h>
  11 #include <i915_drm.h>
  12 #include <stdbool.h>
  13 #include <stdio.h>
  14 #include <string.h>
  15 #include <sys/mman.h>
  16 #include <unistd.h>
  17 #include <xf86drm.h>
  18
  19 #include "drv_priv.h"
  20 #include "helpers.h"
  21 #include "util.h"
  22
  23 #define I915_CACHELINE_SIZE 64
  24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  25
  26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
  27                                                    DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
  28                                                    DRM_FORMAT_RGB565,      DRM_FORMAT_XBGR2101010,
  29                                                    DRM_FORMAT_XBGR8888,    DRM_FORMAT_XRGB2101010,
  30                                                    DRM_FORMAT_XRGB8888 };
  31
  32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
  33
  34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
  35                                                  DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
  36
  37 struct i915_device {
  38         uint32_t gen;
  39         int32_t has_llc;
  40 };
  41
  42 static uint32_t i915_get_gen(int device_id)
  43 {
  44         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  45                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  46         unsigned i;
  47         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  48                 if (gen3_ids[i] == device_id)
  49                         return 3;
  50
  51         return 4;
  52 }
  53
  54 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
  55 {
  56         uint64_t value = current_flags & ~mask;
  57         return value;
  58 }
  59
  60 static int i915_add_combinations(struct driver *drv)
  61 {
  62         struct format_metadata metadata;
  63         uint64_t render, scanout_and_render, texture_only;
  64
  65         scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
  66         render = BO_USE_RENDER_MASK;
  67         texture_only = BO_USE_TEXTURE_MASK;
  68         uint64_t linear_mask = BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_PROTECTED |
  69                                BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
  70
  71         metadata.tiling = I915_TILING_NONE;
  72         metadata.priority = 1;
  73         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
  74
  75         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
  76                              &metadata, scanout_and_render);
  77
  78         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
  79
  80         drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
  81                              texture_only);
  82
  83         drv_modify_linear_combinations(drv);
  84         /*
  85          * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
  86          * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
  87          */
  88         drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
  89         /* IPU3 camera ISP supports only NV12 output. */
  90         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
  91                                BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER |
  92                                    BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT);
  93
  94         /* Android CTS tests require this. */
  95         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
  96
  97         /*
  98          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
  99          * from camera.
 100          */
 101         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 102                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 103
 104         render = unset_flags(render, linear_mask);
 105         scanout_and_render = unset_flags(scanout_and_render, linear_mask);
 106
 107         metadata.tiling = I915_TILING_X;
 108         metadata.priority = 2;
 109         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 110
 111         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 112         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 113                              &metadata, scanout_and_render);
 114
 115         metadata.tiling = I915_TILING_Y;
 116         metadata.priority = 3;
 117         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 118
 119         scanout_and_render =
 120             unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
 121 /* Support y-tiled NV12 and P010 for libva */
 122 #ifdef I915_SCANOUT_Y_TILED
 123         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 124                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT);
 125 #else
 126         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 127                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 128 #endif
 129         scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
 130         drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
 131                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 132
 133         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 134         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 135                              &metadata, scanout_and_render);
 136         return 0;
 137 }
 138
 139 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 140                                  uint32_t *aligned_height)
 141 {
 142         struct i915_device *i915 = bo->drv->priv;
 143         uint32_t horizontal_alignment;
 144         uint32_t vertical_alignment;
 145
 146         switch (tiling) {
 147         default:
 148         case I915_TILING_NONE:
 149                 /*
 150                  * The Intel GPU doesn't need any alignment in linear mode,
 151                  * but libva requires the allocation stride to be aligned to
 152                  * 16 bytes and height to 4 rows. Further, we round up the
 153                  * horizontal alignment so that row start on a cache line (64
 154                  * bytes).
 155                  */
 156                 horizontal_alignment = 64;
 157                 vertical_alignment = 4;
 158                 break;
 159
 160         case I915_TILING_X:
 161                 horizontal_alignment = 512;
 162                 vertical_alignment = 8;
 163                 break;
 164
 165         case I915_TILING_Y:
 166                 if (i915->gen == 3) {
 167                         horizontal_alignment = 512;
 168                         vertical_alignment = 8;
 169                 } else {
 170                         horizontal_alignment = 128;
 171                         vertical_alignment = 32;
 172                 }
 173                 break;
 174         }
 175
 176         *aligned_height = ALIGN(*aligned_height, vertical_alignment);
 177         if (i915->gen > 3) {
 178                 *stride = ALIGN(*stride, horizontal_alignment);
 179         } else {
 180                 while (*stride > horizontal_alignment)
 181                         horizontal_alignment <<= 1;
 182
 183                 *stride = horizontal_alignment;
 184         }
 185
 186         if (i915->gen <= 3 && *stride > 8192)
 187                 return -EINVAL;
 188
 189         return 0;
 190 }
 191
 192 static void i915_clflush(void *start, size_t size)
 193 {
 194         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 195         void *end = (void *)((uintptr_t)start + size);
 196
 197         __builtin_ia32_mfence();
 198         while (p < end) {
 199                 __builtin_ia32_clflush(p);
 200                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 201         }
 202 }
 203
 204 static int i915_init(struct driver *drv)
 205 {
 206         int ret;
 207         int device_id;
 208         struct i915_device *i915;
 209         drm_i915_getparam_t get_param;
 210
 211         i915 = calloc(1, sizeof(*i915));
 212         if (!i915)
 213                 return -ENOMEM;
 214
 215         memset(&get_param, 0, sizeof(get_param));
 216         get_param.param = I915_PARAM_CHIPSET_ID;
 217         get_param.value = &device_id;
 218         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 219         if (ret) {
 220                 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
 221                 free(i915);
 222                 return -EINVAL;
 223         }
 224
 225         i915->gen = i915_get_gen(device_id);
 226
 227         memset(&get_param, 0, sizeof(get_param));
 228         get_param.param = I915_PARAM_HAS_LLC;
 229         get_param.value = &i915->has_llc;
 230         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 231         if (ret) {
 232                 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
 233                 free(i915);
 234                 return -EINVAL;
 235         }
 236
 237         drv->priv = i915;
 238
 239         return i915_add_combinations(drv);
 240 }
 241
 242 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
 243 {
 244         uint32_t offset;
 245         size_t plane;
 246         int ret, pagesize;
 247
 248         offset = 0;
 249         pagesize = getpagesize();
 250         for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
 251                 uint32_t stride = drv_stride_from_format(format, width, plane);
 252                 uint32_t plane_height = drv_height_from_format(format, height, plane);
 253
 254                 if (bo->meta.tiling != I915_TILING_NONE)
 255                         assert(IS_ALIGNED(offset, pagesize));
 256
 257                 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
 258                 if (ret)
 259                         return ret;
 260
 261                 bo->meta.strides[plane] = stride;
 262                 bo->meta.sizes[plane] = stride * plane_height;
 263                 bo->meta.offsets[plane] = offset;
 264                 offset += bo->meta.sizes[plane];
 265         }
 266
 267         bo->meta.total_size = ALIGN(offset, pagesize);
 268
 269         return 0;
 270 }
 271
 272 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 273                                     uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
 274 {
 275         static const uint64_t modifier_order[] = {
 276                 I915_FORMAT_MOD_Y_TILED,
 277                 I915_FORMAT_MOD_X_TILED,
 278                 DRM_FORMAT_MOD_LINEAR,
 279         };
 280         uint64_t modifier;
 281         struct i915_device *i915 = bo->drv->priv;
 282         bool huge_bo = (i915->gen <= 11) && (width > 4096);
 283
 284         if (modifiers) {
 285                 modifier =
 286                     drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
 287         } else {
 288                 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
 289                 if (!combo)
 290                         return -EINVAL;
 291                 modifier = combo->metadata.modifier;
 292         }
 293
 294         /*
 295          * i915 only supports linear/x-tiled above 4096 wide
 296          */
 297         if (huge_bo && modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
 298                 uint32_t i;
 299                 for (i = 0; modifiers && i < count; i++) {
 300                         if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
 301                                 break;
 302                 }
 303                 if (i == count)
 304                         modifier = DRM_FORMAT_MOD_LINEAR;
 305                 else
 306                         modifier = I915_FORMAT_MOD_X_TILED;
 307         }
 308
 309         switch (modifier) {
 310         case DRM_FORMAT_MOD_LINEAR:
 311                 bo->meta.tiling = I915_TILING_NONE;
 312                 break;
 313         case I915_FORMAT_MOD_X_TILED:
 314                 bo->meta.tiling = I915_TILING_X;
 315                 break;
 316         case I915_FORMAT_MOD_Y_TILED:
 317         case I915_FORMAT_MOD_Y_TILED_CCS:
 318                 bo->meta.tiling = I915_TILING_Y;
 319                 break;
 320         }
 321
 322         bo->meta.format_modifiers[0] = modifier;
 323
 324         if (format == DRM_FORMAT_YVU420_ANDROID) {
 325                 /*
 326                  * We only need to be able to use this as a linear texture,
 327                  * which doesn't put any HW restrictions on how we lay it
 328                  * out. The Android format does require the stride to be a
 329                  * multiple of 16 and expects the Cr and Cb stride to be
 330                  * ALIGN(Y_stride / 2, 16), which we can make happen by
 331                  * aligning to 32 bytes here.
 332                  */
 333                 uint32_t stride = ALIGN(width, 32);
 334                 drv_bo_from_format(bo, stride, height, format);
 335         } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
 336                 /*
 337                  * For compressed surfaces, we need a color control surface
 338                  * (CCS). Color compression is only supported for Y tiled
 339                  * surfaces, and for each 32x16 tiles in the main surface we
 340                  * need a tile in the control surface.  Y tiles are 128 bytes
 341                  * wide and 32 lines tall and we use that to first compute the
 342                  * width and height in tiles of the main surface. stride and
 343                  * height are already multiples of 128 and 32, respectively:
 344                  */
 345                 uint32_t stride = drv_stride_from_format(format, width, 0);
 346                 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
 347                 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
 348                 uint32_t size = width_in_tiles * height_in_tiles * 4096;
 349                 uint32_t offset = 0;
 350
 351                 bo->meta.strides[0] = width_in_tiles * 128;
 352                 bo->meta.sizes[0] = size;
 353                 bo->meta.offsets[0] = offset;
 354                 offset += size;
 355
 356                 /*
 357                  * Now, compute the width and height in tiles of the control
 358                  * surface by dividing and rounding up.
 359                  */
 360                 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
 361                 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
 362                 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
 363
 364                 /*
 365                  * With stride and height aligned to y tiles, offset is
 366                  * already a multiple of 4096, which is the required alignment
 367                  * of the CCS.
 368                  */
 369                 bo->meta.strides[1] = ccs_width_in_tiles * 128;
 370                 bo->meta.sizes[1] = ccs_size;
 371                 bo->meta.offsets[1] = offset;
 372                 offset += ccs_size;
 373
 374                 bo->meta.num_planes = 2;
 375                 bo->meta.total_size = offset;
 376         } else {
 377                 i915_bo_from_format(bo, width, height, format);
 378         }
 379         return 0;
 380 }
 381
 382 static int i915_bo_create_from_metadata(struct bo *bo)
 383 {
 384         int ret;
 385         size_t plane;
 386         struct drm_i915_gem_create gem_create;
 387         struct drm_i915_gem_set_tiling gem_set_tiling;
 388
 389         memset(&gem_create, 0, sizeof(gem_create));
 390         gem_create.size = bo->meta.total_size;
 391
 392         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 393         if (ret) {
 394                 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
 395                 return -errno;
 396         }
 397
 398         for (plane = 0; plane < bo->meta.num_planes; plane++)
 399                 bo->handles[plane].u32 = gem_create.handle;
 400
 401         memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
 402         gem_set_tiling.handle = bo->handles[0].u32;
 403         gem_set_tiling.tiling_mode = bo->meta.tiling;
 404         gem_set_tiling.stride = bo->meta.strides[0];
 405
 406         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 407         if (ret) {
 408                 struct drm_gem_close gem_close;
 409                 memset(&gem_close, 0, sizeof(gem_close));
 410                 gem_close.handle = bo->handles[0].u32;
 411                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 412
 413                 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
 414                 return -errno;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static void i915_close(struct driver *drv)
 421 {
 422         free(drv->priv);
 423         drv->priv = NULL;
 424 }
 425
 426 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 427 {
 428         int ret;
 429         struct drm_i915_gem_get_tiling gem_get_tiling;
 430
 431         ret = drv_prime_bo_import(bo, data);
 432         if (ret)
 433                 return ret;
 434
 435         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 436         memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
 437         gem_get_tiling.handle = bo->handles[0].u32;
 438
 439         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 440         if (ret) {
 441                 drv_gem_bo_destroy(bo);
 442                 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
 443                 return ret;
 444         }
 445
 446         bo->meta.tiling = gem_get_tiling.tiling_mode;
 447         return 0;
 448 }
 449
 450 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 451 {
 452         int ret;
 453         void *addr;
 454
 455         if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
 456                 return MAP_FAILED;
 457
 458         if (bo->meta.tiling == I915_TILING_NONE) {
 459                 struct drm_i915_gem_mmap gem_map;
 460                 memset(&gem_map, 0, sizeof(gem_map));
 461
 462                 /* TODO(b/118799155): We don't seem to have a good way to
 463                  * detect the use cases for which WC mapping is really needed.
 464                  * The current heuristic seems overly coarse and may be slowing
 465                  * down some other use cases unnecessarily.
 466                  *
 467                  * For now, care must be taken not to use WC mappings for
 468                  * Renderscript and camera use cases, as they're
 469                  * performance-sensitive. */
 470                 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
 471                     !(bo->meta.use_flags &
 472                       (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
 473                         gem_map.flags = I915_MMAP_WC;
 474
 475                 gem_map.handle = bo->handles[0].u32;
 476                 gem_map.offset = 0;
 477                 gem_map.size = bo->meta.total_size;
 478
 479                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 480                 if (ret) {
 481                         drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
 482                         return MAP_FAILED;
 483                 }
 484
 485                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 486         } else {
 487                 struct drm_i915_gem_mmap_gtt gem_map;
 488                 memset(&gem_map, 0, sizeof(gem_map));
 489
 490                 gem_map.handle = bo->handles[0].u32;
 491
 492                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 493                 if (ret) {
 494                         drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 495                         return MAP_FAILED;
 496                 }
 497
 498                 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
 499                             bo->drv->fd, gem_map.offset);
 500         }
 501
 502         if (addr == MAP_FAILED) {
 503                 drv_log("i915 GEM mmap failed\n");
 504                 return addr;
 505         }
 506
 507         vma->length = bo->meta.total_size;
 508         return addr;
 509 }
 510
 511 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
 512 {
 513         int ret;
 514         struct drm_i915_gem_set_domain set_domain;
 515
 516         memset(&set_domain, 0, sizeof(set_domain));
 517         set_domain.handle = bo->handles[0].u32;
 518         if (bo->meta.tiling == I915_TILING_NONE) {
 519                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 520                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 521                         set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 522         } else {
 523                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 524                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 525                         set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 526         }
 527
 528         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 529         if (ret) {
 530                 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
 531                 return ret;
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
 538 {
 539         struct i915_device *i915 = bo->drv->priv;
 540         if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
 541                 i915_clflush(mapping->vma->addr, mapping->vma->length);
 542
 543         return 0;
 544 }
 545
 546 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 547 {
 548         switch (format) {
 549         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 550                 /* KBL camera subsystem requires NV12. */
 551                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 552                         return DRM_FORMAT_NV12;
 553                 /*HACK: See b/28671744 */
 554                 return DRM_FORMAT_XBGR8888;
 555         case DRM_FORMAT_FLEX_YCbCr_420_888:
 556                 /*
 557                  * KBL camera subsystem requires NV12. Our other use cases
 558                  * don't care:
 559                  * - Hardware video supports NV12,
 560                  * - USB Camera HALv3 supports NV12,
 561                  * - USB Camera HALv1 doesn't use this format.
 562                  * Moreover, NV12 is preferred for video, due to overlay
 563                  * support on SKL+.
 564                  */
 565                 return DRM_FORMAT_NV12;
 566         default:
 567                 return format;
 568         }
 569 }
 570
 571 const struct backend backend_i915 = {
 572         .name = "i915",
 573         .init = i915_init,
 574         .close = i915_close,
 575         .bo_compute_metadata = i915_bo_compute_metadata,
 576         .bo_create_from_metadata = i915_bo_create_from_metadata,
 577         .bo_destroy = drv_gem_bo_destroy,
 578         .bo_import = i915_bo_import,
 579         .bo_map = i915_bo_map,
 580         .bo_unmap = drv_bo_munmap,
 581         .bo_invalidate = i915_bo_invalidate,
 582         .bo_flush = i915_bo_flush,
 583         .resolve_format = i915_resolve_format,
 584 };
 585
 586 #endif