2 * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
26 static int get_gen(int device_id)
28 const uint16_t gen3_ids[] = {0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
29 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011};
31 for(i = 0; i < ARRAY_SIZE(gen3_ids); i++)
32 if (gen3_ids[i] == device_id)
38 static int i915_init(struct driver *drv)
40 struct i915_device *i915_drv;
41 drm_i915_getparam_t get_param;
45 i915_drv = (struct i915_device*)malloc(sizeof(*i915_drv));
49 memset(&get_param, 0, sizeof(get_param));
50 get_param.param = I915_PARAM_CHIPSET_ID;
51 get_param.value = &device_id;
52 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
54 fprintf(stderr, "drv: DRM_IOCTL_I915_GETPARAM failed\n");
59 i915_drv->gen = get_gen(device_id);
66 static void i915_close(struct driver *drv)
72 static void i915_align_dimensions(struct driver *drv, uint32_t tiling_mode,
73 uint32_t *width, uint32_t *height, int bpp)
75 struct i915_device *i915_drv = (struct i915_device *)drv->priv;
76 uint32_t width_alignment = 4, height_alignment = 4;
78 switch (tiling_mode) {
80 case I915_TILING_NONE:
81 width_alignment = 64 / bpp;
85 width_alignment = 512 / bpp;
90 if (i915_drv->gen == 3) {
91 width_alignment = 512 / bpp;
94 width_alignment = 128 / bpp;
95 height_alignment = 32;
100 if (i915_drv->gen > 3) {
101 *width = ALIGN(*width, width_alignment);
102 *height = ALIGN(*height, height_alignment);
105 for (w = width_alignment; w < *width; w <<= 1)
108 *height = ALIGN(*height, height_alignment);
112 static int i915_verify_dimensions(struct driver *drv, uint32_t stride,
115 struct i915_device *i915_drv = (struct i915_device *)drv->priv;
116 if (i915_drv->gen <= 3 && stride > 8192)
122 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height,
123 uint32_t format, uint32_t flags)
125 struct driver *drv = bo->drv;
126 int bpp = drv_stride_from_format(format, 1, 0);
127 struct drm_i915_gem_create gem_create;
128 struct drm_i915_gem_set_tiling gem_set_tiling;
129 uint32_t tiling_mode = I915_TILING_NONE;
133 if (flags & (DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR |
134 DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN))
135 tiling_mode = I915_TILING_NONE;
136 else if (flags & DRV_BO_USE_SCANOUT)
137 tiling_mode = I915_TILING_X;
138 else if (flags & (DRV_BO_USE_RENDERING | DRV_BO_USE_SW_READ_RARELY |
139 DRV_BO_USE_SW_WRITE_RARELY))
140 tiling_mode = I915_TILING_Y;
142 i915_align_dimensions(drv, tiling_mode, &width, &height, bpp);
144 drv_bo_from_format(bo, width, height, format);
146 if (!i915_verify_dimensions(drv, bo->strides[0], height))
149 memset(&gem_create, 0, sizeof(gem_create));
150 gem_create.size = bo->total_size;
152 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
154 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed "
155 "(size=%llu)\n", gem_create.size);
159 for (plane = 0; plane < bo->num_planes; plane++)
160 bo->handles[plane].u32 = gem_create.handle;
162 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
164 gem_set_tiling.handle = bo->handles[0].u32;
165 gem_set_tiling.tiling_mode = tiling_mode;
166 gem_set_tiling.stride = bo->strides[0];
167 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GEM_SET_TILING,
169 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
172 struct drm_gem_close gem_close;
173 gem_close.handle = bo->handles[0].u32;
174 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed "
175 "errno=%x (handle=%x, tiling=%x, stride=%x)\n",
177 gem_set_tiling.handle,
178 gem_set_tiling.tiling_mode,
179 gem_set_tiling.stride);
180 drmIoctl(drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
187 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane)
190 struct drm_i915_gem_mmap_gtt gem_map;
192 memset(&gem_map, 0, sizeof(gem_map));
193 gem_map.handle = bo->handles[0].u32;
195 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
197 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
201 data->length = bo->total_size;
203 return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED,
204 bo->drv->fd, gem_map.offset);
207 static drv_format_t i915_resolve_format(drv_format_t format)
210 case DRV_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
211 /*HACK: See b/28671744 */
212 return DRV_FORMAT_XBGR8888;
213 case DRV_FORMAT_FLEX_YCbCr_420_888:
214 return DRV_FORMAT_YVU420;
220 const struct backend backend_i915 =
225 .bo_create = i915_bo_create,
226 .bo_destroy = drv_gem_bo_destroy,
227 .bo_map = i915_bo_map,
228 .resolve_format = i915_resolve_format,
230 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
231 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
232 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR |
233 DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
234 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
235 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
236 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR |
237 DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
238 {DRV_FORMAT_XBGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
239 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
240 {DRV_FORMAT_XBGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING |
241 DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
242 {DRV_FORMAT_ABGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
243 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
244 {DRV_FORMAT_ABGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING | DRV_BO_USE_CURSOR
245 | DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
246 {DRV_FORMAT_XRGB1555, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
247 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
248 {DRV_FORMAT_ARGB1555, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
249 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
250 {DRV_FORMAT_RGB565, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
251 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
252 {DRV_FORMAT_UYVY, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
253 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
254 {DRV_FORMAT_UYVY, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR |
255 DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
256 {DRV_FORMAT_YUYV, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_RENDERING
257 | DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
258 {DRV_FORMAT_YUYV, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR |
259 DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
260 {DRV_FORMAT_R8, DRV_BO_USE_SCANOUT | DRV_BO_USE_LINEAR |
261 DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
262 {DRV_FORMAT_GR88, DRV_BO_USE_SCANOUT | DRV_BO_USE_LINEAR |
263 DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
264 {DRV_FORMAT_YVU420, DRV_BO_USE_LINEAR},
265 {DRV_FORMAT_YVU420, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING |
266 DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},