2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
23 #define I915_CACHELINE_SIZE 64
24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
27 DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
28 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010,
29 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010,
30 DRM_FORMAT_XRGB8888 };
32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
35 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
42 static uint32_t i915_get_gen(int device_id)
44 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
45 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
47 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
48 if (gen3_ids[i] == device_id)
54 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
56 uint64_t value = current_flags & ~mask;
60 static int i915_add_combinations(struct driver *drv)
62 struct format_metadata metadata;
63 uint64_t render, scanout_and_render, texture_only;
65 scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
66 render = BO_USE_RENDER_MASK;
67 texture_only = BO_USE_TEXTURE_MASK;
68 uint64_t linear_mask = BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_PROTECTED |
69 BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
71 metadata.tiling = I915_TILING_NONE;
72 metadata.priority = 1;
73 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
75 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
76 &metadata, scanout_and_render);
78 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
80 drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
83 drv_modify_linear_combinations(drv);
85 * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
86 * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
88 drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
89 /* IPU3 camera ISP supports only NV12 output. */
90 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
91 BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER |
92 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT);
94 /* Android CTS tests require this. */
95 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
98 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
101 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
102 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
104 render = unset_flags(render, linear_mask);
105 scanout_and_render = unset_flags(scanout_and_render, linear_mask);
107 metadata.tiling = I915_TILING_X;
108 metadata.priority = 2;
109 metadata.modifier = I915_FORMAT_MOD_X_TILED;
111 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
112 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
113 &metadata, scanout_and_render);
115 metadata.tiling = I915_TILING_Y;
116 metadata.priority = 3;
117 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
119 scanout_and_render = unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
120 /* Support y-tiled NV12 and P010 for libva */
121 #ifdef I915_SCANOUT_Y_TILED
122 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
123 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT);
125 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
126 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
128 scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
129 drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
130 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
132 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
133 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
134 &metadata, scanout_and_render);
138 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
139 uint32_t *aligned_height)
141 struct i915_device *i915 = bo->drv->priv;
142 uint32_t horizontal_alignment;
143 uint32_t vertical_alignment;
147 case I915_TILING_NONE:
149 * The Intel GPU doesn't need any alignment in linear mode,
150 * but libva requires the allocation stride to be aligned to
151 * 16 bytes and height to 4 rows. Further, we round up the
152 * horizontal alignment so that row start on a cache line (64
155 horizontal_alignment = 64;
156 vertical_alignment = 4;
160 horizontal_alignment = 512;
161 vertical_alignment = 8;
165 if (i915->gen == 3) {
166 horizontal_alignment = 512;
167 vertical_alignment = 8;
169 horizontal_alignment = 128;
170 vertical_alignment = 32;
175 *aligned_height = ALIGN(*aligned_height, vertical_alignment);
177 *stride = ALIGN(*stride, horizontal_alignment);
179 while (*stride > horizontal_alignment)
180 horizontal_alignment <<= 1;
182 *stride = horizontal_alignment;
185 if (i915->gen <= 3 && *stride > 8192)
191 static void i915_clflush(void *start, size_t size)
193 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
194 void *end = (void *)((uintptr_t)start + size);
196 __builtin_ia32_mfence();
198 __builtin_ia32_clflush(p);
199 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
203 static int i915_init(struct driver *drv)
207 struct i915_device *i915;
208 drm_i915_getparam_t get_param;
210 i915 = calloc(1, sizeof(*i915));
214 memset(&get_param, 0, sizeof(get_param));
215 get_param.param = I915_PARAM_CHIPSET_ID;
216 get_param.value = &device_id;
217 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
219 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
224 i915->gen = i915_get_gen(device_id);
226 memset(&get_param, 0, sizeof(get_param));
227 get_param.param = I915_PARAM_HAS_LLC;
228 get_param.value = &i915->has_llc;
229 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
231 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
238 return i915_add_combinations(drv);
241 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
248 pagesize = getpagesize();
249 for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
250 uint32_t stride = drv_stride_from_format(format, width, plane);
251 uint32_t plane_height = drv_height_from_format(format, height, plane);
253 if (bo->meta.tiling != I915_TILING_NONE)
254 assert(IS_ALIGNED(offset, pagesize));
256 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
260 bo->meta.strides[plane] = stride;
261 bo->meta.sizes[plane] = stride * plane_height;
262 bo->meta.offsets[plane] = offset;
263 offset += bo->meta.sizes[plane];
266 bo->meta.total_size = ALIGN(offset, pagesize);
271 static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
272 uint32_t format, uint64_t modifier)
276 struct drm_i915_gem_create gem_create;
277 struct drm_i915_gem_set_tiling gem_set_tiling;
280 case DRM_FORMAT_MOD_LINEAR:
281 bo->meta.tiling = I915_TILING_NONE;
283 case I915_FORMAT_MOD_X_TILED:
284 bo->meta.tiling = I915_TILING_X;
286 case I915_FORMAT_MOD_Y_TILED:
287 case I915_FORMAT_MOD_Y_TILED_CCS:
288 bo->meta.tiling = I915_TILING_Y;
292 bo->meta.format_modifiers[0] = modifier;
294 if (format == DRM_FORMAT_YVU420_ANDROID) {
296 * We only need to be able to use this as a linear texture,
297 * which doesn't put any HW restrictions on how we lay it
298 * out. The Android format does require the stride to be a
299 * multiple of 16 and expects the Cr and Cb stride to be
300 * ALIGN(Y_stride / 2, 16), which we can make happen by
301 * aligning to 32 bytes here.
303 uint32_t stride = ALIGN(width, 32);
304 drv_bo_from_format(bo, stride, height, format);
305 } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
307 * For compressed surfaces, we need a color control surface
308 * (CCS). Color compression is only supported for Y tiled
309 * surfaces, and for each 32x16 tiles in the main surface we
310 * need a tile in the control surface. Y tiles are 128 bytes
311 * wide and 32 lines tall and we use that to first compute the
312 * width and height in tiles of the main surface. stride and
313 * height are already multiples of 128 and 32, respectively:
315 uint32_t stride = drv_stride_from_format(format, width, 0);
316 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
317 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
318 uint32_t size = width_in_tiles * height_in_tiles * 4096;
321 bo->meta.strides[0] = width_in_tiles * 128;
322 bo->meta.sizes[0] = size;
323 bo->meta.offsets[0] = offset;
327 * Now, compute the width and height in tiles of the control
328 * surface by dividing and rounding up.
330 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
331 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
332 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
335 * With stride and height aligned to y tiles, offset is
336 * already a multiple of 4096, which is the required alignment
339 bo->meta.strides[1] = ccs_width_in_tiles * 128;
340 bo->meta.sizes[1] = ccs_size;
341 bo->meta.offsets[1] = offset;
344 bo->meta.num_planes = 2;
345 bo->meta.total_size = offset;
347 i915_bo_from_format(bo, width, height, format);
350 memset(&gem_create, 0, sizeof(gem_create));
351 gem_create.size = bo->meta.total_size;
353 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
355 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
359 for (plane = 0; plane < bo->meta.num_planes; plane++)
360 bo->handles[plane].u32 = gem_create.handle;
362 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
363 gem_set_tiling.handle = bo->handles[0].u32;
364 gem_set_tiling.tiling_mode = bo->meta.tiling;
365 gem_set_tiling.stride = bo->meta.strides[0];
367 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
369 struct drm_gem_close gem_close;
370 memset(&gem_close, 0, sizeof(gem_close));
371 gem_close.handle = bo->handles[0].u32;
372 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
374 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
381 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
384 struct combination *combo;
386 combo = drv_get_combination(bo->drv, format, use_flags);
390 return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
393 static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
394 uint32_t format, const uint64_t *modifiers, uint32_t count)
396 static const uint64_t modifier_order[] = {
397 I915_FORMAT_MOD_Y_TILED_CCS,
398 I915_FORMAT_MOD_Y_TILED,
399 I915_FORMAT_MOD_X_TILED,
400 DRM_FORMAT_MOD_LINEAR,
404 modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
406 return i915_bo_create_for_modifier(bo, width, height, format, modifier);
409 static void i915_close(struct driver *drv)
415 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
418 struct drm_i915_gem_get_tiling gem_get_tiling;
420 ret = drv_prime_bo_import(bo, data);
424 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
425 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
426 gem_get_tiling.handle = bo->handles[0].u32;
428 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
430 drv_gem_bo_destroy(bo);
431 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
435 bo->meta.tiling = gem_get_tiling.tiling_mode;
439 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
444 if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
447 if (bo->meta.tiling == I915_TILING_NONE) {
448 struct drm_i915_gem_mmap gem_map;
449 memset(&gem_map, 0, sizeof(gem_map));
451 /* TODO(b/118799155): We don't seem to have a good way to
452 * detect the use cases for which WC mapping is really needed.
453 * The current heuristic seems overly coarse and may be slowing
454 * down some other use cases unnecessarily.
456 * For now, care must be taken not to use WC mappings for
457 * Renderscript and camera use cases, as they're
458 * performance-sensitive. */
459 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
460 !(bo->meta.use_flags &
461 (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
462 gem_map.flags = I915_MMAP_WC;
464 gem_map.handle = bo->handles[0].u32;
466 gem_map.size = bo->meta.total_size;
468 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
470 drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
474 addr = (void *)(uintptr_t)gem_map.addr_ptr;
476 struct drm_i915_gem_mmap_gtt gem_map;
477 memset(&gem_map, 0, sizeof(gem_map));
479 gem_map.handle = bo->handles[0].u32;
481 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
483 drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
487 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
488 bo->drv->fd, gem_map.offset);
491 if (addr == MAP_FAILED) {
492 drv_log("i915 GEM mmap failed\n");
496 vma->length = bo->meta.total_size;
500 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
503 struct drm_i915_gem_set_domain set_domain;
505 memset(&set_domain, 0, sizeof(set_domain));
506 set_domain.handle = bo->handles[0].u32;
507 if (bo->meta.tiling == I915_TILING_NONE) {
508 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
509 if (mapping->vma->map_flags & BO_MAP_WRITE)
510 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
512 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
513 if (mapping->vma->map_flags & BO_MAP_WRITE)
514 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
517 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
519 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
526 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
528 struct i915_device *i915 = bo->drv->priv;
529 if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
530 i915_clflush(mapping->vma->addr, mapping->vma->length);
535 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
538 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
539 /* KBL camera subsystem requires NV12. */
540 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
541 return DRM_FORMAT_NV12;
542 /*HACK: See b/28671744 */
543 return DRM_FORMAT_XBGR8888;
544 case DRM_FORMAT_FLEX_YCbCr_420_888:
546 * KBL camera subsystem requires NV12. Our other use cases
548 * - Hardware video supports NV12,
549 * - USB Camera HALv3 supports NV12,
550 * - USB Camera HALv1 doesn't use this format.
551 * Moreover, NV12 is preferred for video, due to overlay
554 return DRM_FORMAT_NV12;
560 const struct backend backend_i915 = {
564 .bo_create = i915_bo_create,
565 .bo_create_with_modifiers = i915_bo_create_with_modifiers,
566 .bo_destroy = drv_gem_bo_destroy,
567 .bo_import = i915_bo_import,
568 .bo_map = i915_bo_map,
569 .bo_unmap = drv_bo_munmap,
570 .bo_invalidate = i915_bo_invalidate,
571 .bo_flush = i915_bo_flush,
572 .resolve_format = i915_resolve_format,