2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
19 #include "external/i915_drm.h"
23 #define I915_CACHELINE_SIZE 64
24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
27 DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
28 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010,
29 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010,
30 DRM_FORMAT_XRGB8888 };
32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
35 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
38 DRM_FORMAT_MOD_LINEAR };
40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
41 I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
42 DRM_FORMAT_MOD_LINEAR };
44 struct modifier_support_t {
45 const uint64_t *order;
52 int32_t has_hw_protection;
53 struct modifier_support_t modifier;
56 static uint32_t i915_get_gen(int device_id)
58 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
59 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
60 const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
61 const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
62 0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
64 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
65 if (gen3_ids[i] == device_id)
68 for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
69 if (gen11_ids[i] == device_id)
73 for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
74 if (gen12_ids[i] == device_id)
80 static void i915_get_modifier_order(struct i915_device *i915)
82 if (i915->gen == 11) {
83 i915->modifier.order = gen11_modifier_order;
84 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
86 i915->modifier.order = gen_modifier_order;
87 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
91 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
93 uint64_t value = current_flags & ~mask;
97 static int i915_add_combinations(struct driver *drv)
99 struct format_metadata metadata;
100 uint64_t render, scanout_and_render, texture_only, hw_protected;
101 struct i915_device *i915 = drv->priv;
103 scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
104 render = BO_USE_RENDER_MASK;
105 texture_only = BO_USE_TEXTURE_MASK;
106 // HW protected buffers also need to be scanned out.
107 hw_protected = i915->has_hw_protection ? (BO_USE_PROTECTED | BO_USE_SCANOUT) : 0;
109 uint64_t linear_mask =
110 BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
112 metadata.tiling = I915_TILING_NONE;
113 metadata.priority = 1;
114 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
116 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
117 &metadata, scanout_and_render);
119 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
121 drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
124 drv_modify_linear_combinations(drv);
126 /* NV12 format for camera, display, decoding and encoding. */
127 /* IPU3 camera ISP supports only NV12 output. */
128 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
129 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
130 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
133 /* Android CTS tests require this. */
134 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
137 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
138 * from camera and input/output from hardware decoder/encoder.
140 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
141 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
142 BO_USE_HW_VIDEO_ENCODER);
144 render = unset_flags(render, linear_mask);
145 scanout_and_render = unset_flags(scanout_and_render, linear_mask);
147 metadata.tiling = I915_TILING_X;
148 metadata.priority = 2;
149 metadata.modifier = I915_FORMAT_MOD_X_TILED;
151 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
152 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
153 &metadata, scanout_and_render);
155 metadata.tiling = I915_TILING_Y;
156 metadata.priority = 3;
157 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
160 unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
161 /* Support y-tiled NV12 and P010 for libva */
162 #ifdef I915_SCANOUT_Y_TILED
163 uint64_t nv12_usage =
164 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT | hw_protected;
165 uint64_t p010_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | hw_protected;
167 uint64_t nv12_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER;
168 uint64_t p010_usage = nv12_usage;
170 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, nv12_usage);
171 drv_add_combination(drv, DRM_FORMAT_P010, &metadata, p010_usage);
173 scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
175 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
176 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
177 &metadata, scanout_and_render);
181 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
182 uint32_t *aligned_height)
184 struct i915_device *i915 = bo->drv->priv;
185 uint32_t horizontal_alignment;
186 uint32_t vertical_alignment;
190 case I915_TILING_NONE:
192 * The Intel GPU doesn't need any alignment in linear mode,
193 * but libva requires the allocation stride to be aligned to
194 * 16 bytes and height to 4 rows. Further, we round up the
195 * horizontal alignment so that row start on a cache line (64
198 #ifdef LINEAR_ALIGN_256
200 * If we want to import these buffers to amdgpu they need to
201 * their match LINEAR_ALIGNED requirement of 256 byte alignement.
203 horizontal_alignment = 256;
205 horizontal_alignment = 64;
207 vertical_alignment = 4;
211 horizontal_alignment = 512;
212 vertical_alignment = 8;
216 if (i915->gen == 3) {
217 horizontal_alignment = 512;
218 vertical_alignment = 8;
220 horizontal_alignment = 128;
221 vertical_alignment = 32;
226 *aligned_height = ALIGN(*aligned_height, vertical_alignment);
228 *stride = ALIGN(*stride, horizontal_alignment);
230 while (*stride > horizontal_alignment)
231 horizontal_alignment <<= 1;
233 *stride = horizontal_alignment;
236 if (i915->gen <= 3 && *stride > 8192)
242 static void i915_clflush(void *start, size_t size)
244 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
245 void *end = (void *)((uintptr_t)start + size);
247 __builtin_ia32_mfence();
249 __builtin_ia32_clflush(p);
250 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
254 static int i915_init(struct driver *drv)
258 struct i915_device *i915;
259 drm_i915_getparam_t get_param = { 0 };
261 i915 = calloc(1, sizeof(*i915));
265 get_param.param = I915_PARAM_CHIPSET_ID;
266 get_param.value = &device_id;
267 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
269 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
274 i915->gen = i915_get_gen(device_id);
275 i915_get_modifier_order(i915);
277 memset(&get_param, 0, sizeof(get_param));
278 get_param.param = I915_PARAM_HAS_LLC;
279 get_param.value = &i915->has_llc;
280 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
282 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
288 i915->has_hw_protection = 1;
291 return i915_add_combinations(drv);
294 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
301 pagesize = getpagesize();
302 for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
303 uint32_t stride = drv_stride_from_format(format, width, plane);
304 uint32_t plane_height = drv_height_from_format(format, height, plane);
306 if (bo->meta.tiling != I915_TILING_NONE)
307 assert(IS_ALIGNED(offset, pagesize));
309 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
313 bo->meta.strides[plane] = stride;
314 bo->meta.sizes[plane] = stride * plane_height;
315 bo->meta.offsets[plane] = offset;
316 offset += bo->meta.sizes[plane];
319 bo->meta.total_size = ALIGN(offset, pagesize);
324 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
325 uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
328 struct i915_device *i915 = bo->drv->priv;
329 bool huge_bo = (i915->gen < 11) && (width > 4096);
333 drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
335 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
338 modifier = combo->metadata.modifier;
342 * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
343 * VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
345 if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
346 modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
348 for (i = 0; modifiers && i < count; i++) {
349 if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
353 modifier = DRM_FORMAT_MOD_LINEAR;
355 modifier = I915_FORMAT_MOD_X_TILED;
359 * Skip I915_FORMAT_MOD_Y_TILED_CCS modifier if compression is disabled
360 * Pick y tiled modifier if it has been passed in, otherwise use linear
362 if (!bo->drv->compression && modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
364 for (i = 0; modifiers && i < count; i++) {
365 if (modifiers[i] == I915_FORMAT_MOD_Y_TILED)
369 modifier = DRM_FORMAT_MOD_LINEAR;
371 modifier = I915_FORMAT_MOD_Y_TILED;
375 case DRM_FORMAT_MOD_LINEAR:
376 bo->meta.tiling = I915_TILING_NONE;
378 case I915_FORMAT_MOD_X_TILED:
379 bo->meta.tiling = I915_TILING_X;
381 case I915_FORMAT_MOD_Y_TILED:
382 case I915_FORMAT_MOD_Y_TILED_CCS:
383 bo->meta.tiling = I915_TILING_Y;
387 bo->meta.format_modifiers[0] = modifier;
389 if (format == DRM_FORMAT_YVU420_ANDROID) {
391 * We only need to be able to use this as a linear texture,
392 * which doesn't put any HW restrictions on how we lay it
393 * out. The Android format does require the stride to be a
394 * multiple of 16 and expects the Cr and Cb stride to be
395 * ALIGN(Y_stride / 2, 16), which we can make happen by
396 * aligning to 32 bytes here.
398 uint32_t stride = ALIGN(width, 32);
399 drv_bo_from_format(bo, stride, height, format);
400 } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
402 * For compressed surfaces, we need a color control surface
403 * (CCS). Color compression is only supported for Y tiled
404 * surfaces, and for each 32x16 tiles in the main surface we
405 * need a tile in the control surface. Y tiles are 128 bytes
406 * wide and 32 lines tall and we use that to first compute the
407 * width and height in tiles of the main surface. stride and
408 * height are already multiples of 128 and 32, respectively:
410 uint32_t stride = drv_stride_from_format(format, width, 0);
411 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
412 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
413 uint32_t size = width_in_tiles * height_in_tiles * 4096;
416 bo->meta.strides[0] = width_in_tiles * 128;
417 bo->meta.sizes[0] = size;
418 bo->meta.offsets[0] = offset;
422 * Now, compute the width and height in tiles of the control
423 * surface by dividing and rounding up.
425 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
426 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
427 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
430 * With stride and height aligned to y tiles, offset is
431 * already a multiple of 4096, which is the required alignment
434 bo->meta.strides[1] = ccs_width_in_tiles * 128;
435 bo->meta.sizes[1] = ccs_size;
436 bo->meta.offsets[1] = offset;
439 bo->meta.num_planes = 2;
440 bo->meta.total_size = offset;
442 i915_bo_from_format(bo, width, height, format);
447 static int i915_bo_create_from_metadata(struct bo *bo)
452 struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
453 struct i915_device *i915 = bo->drv->priv;
455 if (i915->has_hw_protection && (bo->meta.use_flags & BO_USE_PROTECTED)) {
456 struct drm_i915_gem_object_param protected_param = {
457 .param = I915_OBJECT_PARAM | I915_PARAM_PROTECTED_CONTENT,
461 struct drm_i915_gem_create_ext_setparam setparam_protected = {
462 .base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
463 .param = protected_param,
466 struct drm_i915_gem_create_ext create_ext = {
467 .size = bo->meta.total_size,
468 .extensions = (uintptr_t)&setparam_protected,
471 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
473 drv_log("DRM_IOCTL_I915_GEM_CREATE_EXT failed (size=%llu)\n",
478 gem_handle = create_ext.handle;
480 struct drm_i915_gem_create gem_create = { 0 };
481 gem_create.size = bo->meta.total_size;
482 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
484 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
488 gem_handle = gem_create.handle;
491 for (plane = 0; plane < bo->meta.num_planes; plane++)
492 bo->handles[plane].u32 = gem_handle;
494 gem_set_tiling.handle = bo->handles[0].u32;
495 gem_set_tiling.tiling_mode = bo->meta.tiling;
496 gem_set_tiling.stride = bo->meta.strides[0];
498 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
500 struct drm_gem_close gem_close = { 0 };
501 gem_close.handle = bo->handles[0].u32;
502 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
504 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
511 static void i915_close(struct driver *drv)
517 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
520 struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
522 ret = drv_prime_bo_import(bo, data);
526 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
527 gem_get_tiling.handle = bo->handles[0].u32;
529 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
531 drv_gem_bo_destroy(bo);
532 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
536 bo->meta.tiling = gem_get_tiling.tiling_mode;
540 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
543 void *addr = MAP_FAILED;
545 if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
548 if (bo->meta.tiling == I915_TILING_NONE) {
549 struct drm_i915_gem_mmap gem_map = { 0 };
550 /* TODO(b/118799155): We don't seem to have a good way to
551 * detect the use cases for which WC mapping is really needed.
552 * The current heuristic seems overly coarse and may be slowing
553 * down some other use cases unnecessarily.
555 * For now, care must be taken not to use WC mappings for
556 * Renderscript and camera use cases, as they're
557 * performance-sensitive. */
558 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
559 !(bo->meta.use_flags &
560 (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
561 gem_map.flags = I915_MMAP_WC;
563 gem_map.handle = bo->handles[0].u32;
565 gem_map.size = bo->meta.total_size;
567 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
568 /* DRM_IOCTL_I915_GEM_MMAP mmaps the underlying shm
569 * file and returns a user space address directly, ie,
570 * doesn't go through mmap. If we try that on a
571 * dma-buf that doesn't have a shm file, i915.ko
572 * returns ENXIO. Fall through to
573 * DRM_IOCTL_I915_GEM_MMAP_GTT in that case, which
574 * will mmap on the drm fd instead. */
576 addr = (void *)(uintptr_t)gem_map.addr_ptr;
579 if (addr == MAP_FAILED) {
580 struct drm_i915_gem_mmap_gtt gem_map = { 0 };
582 gem_map.handle = bo->handles[0].u32;
583 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
585 drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
589 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
590 bo->drv->fd, gem_map.offset);
593 if (addr == MAP_FAILED) {
594 drv_log("i915 GEM mmap failed\n");
598 vma->length = bo->meta.total_size;
602 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
605 struct drm_i915_gem_set_domain set_domain = { 0 };
607 set_domain.handle = bo->handles[0].u32;
608 if (bo->meta.tiling == I915_TILING_NONE) {
609 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
610 if (mapping->vma->map_flags & BO_MAP_WRITE)
611 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
613 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
614 if (mapping->vma->map_flags & BO_MAP_WRITE)
615 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
618 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
620 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
627 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
629 struct i915_device *i915 = bo->drv->priv;
630 if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
631 i915_clflush(mapping->vma->addr, mapping->vma->length);
636 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
639 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
640 /* KBL camera subsystem requires NV12. */
641 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
642 return DRM_FORMAT_NV12;
643 /*HACK: See b/28671744 */
644 return DRM_FORMAT_XBGR8888;
645 case DRM_FORMAT_FLEX_YCbCr_420_888:
647 * KBL camera subsystem requires NV12. Our other use cases
649 * - Hardware video supports NV12,
650 * - USB Camera HALv3 supports NV12,
651 * - USB Camera HALv1 doesn't use this format.
652 * Moreover, NV12 is preferred for video, due to overlay
655 return DRM_FORMAT_NV12;
661 const struct backend backend_i915 = {
665 .bo_compute_metadata = i915_bo_compute_metadata,
666 .bo_create_from_metadata = i915_bo_create_from_metadata,
667 .bo_destroy = drv_gem_bo_destroy,
668 .bo_import = i915_bo_import,
669 .bo_map = i915_bo_map,
670 .bo_unmap = drv_bo_munmap,
671 .bo_invalidate = i915_bo_invalidate,
672 .bo_flush = i915_bo_flush,
673 .resolve_format = i915_resolve_format,