6 #include "va_backend.h"
8 #include "intel_batchbuffer.h"
9 #include "intel_driver.h"
11 #include "i965_defines.h"
12 #include "i965_drv_video.h"
13 #include "i965_media.h"
14 #include "i965_media_h264.h"
26 struct intra_kernel_header
29 unsigned char intra_4x4_luma_mode_0_offset;
30 unsigned char intra_4x4_luma_mode_1_offset;
31 unsigned char intra_4x4_luma_mode_2_offset;
32 unsigned char intra_4x4_luma_mode_3_offset;
34 unsigned char intra_4x4_luma_mode_4_offset;
35 unsigned char intra_4x4_luma_mode_5_offset;
36 unsigned char intra_4x4_luma_mode_6_offset;
37 unsigned char intra_4x4_luma_mode_7_offset;
39 unsigned char intra_4x4_luma_mode_8_offset;
41 unsigned short top_reference_offset;
43 unsigned char intra_8x8_luma_mode_0_offset;
44 unsigned char intra_8x8_luma_mode_1_offset;
45 unsigned char intra_8x8_luma_mode_2_offset;
46 unsigned char intra_8x8_luma_mode_3_offset;
48 unsigned char intra_8x8_luma_mode_4_offset;
49 unsigned char intra_8x8_luma_mode_5_offset;
50 unsigned char intra_8x8_luma_mode_6_offset;
51 unsigned char intra_8x8_luma_mode_7_offset;
53 unsigned char intra_8x8_luma_mode_8_offset;
55 unsigned short const_reverse_data_transfer_intra_8x8;
57 unsigned char intra_16x16_luma_mode_0_offset;
58 unsigned char intra_16x16_luma_mode_1_offset;
59 unsigned char intra_16x16_luma_mode_2_offset;
60 unsigned char intra_16x16_luma_mode_3_offset;
62 unsigned char intra_chroma_mode_0_offset;
63 unsigned char intra_chroma_mode_1_offset;
64 unsigned char intra_chroma_mode_2_offset;
65 unsigned char intra_chroma_mode_3_offset;
67 unsigned int const_intra_16x16_plane_0;
69 unsigned int const_intra_16x16_chroma_plane_0;
71 unsigned int const_intra_16x16_chroma_plane_1;
73 unsigned int const_intra_16x16_plane_1;
75 unsigned int left_shift_count_reverse_dw_ordering;
77 unsigned int const_reverse_data_transfer_intra_4x4;
79 unsigned int intra_4x4_pred_mode_offset;
82 struct inter_kernel_header
84 unsigned short weight_offset;
85 unsigned char weight_offset_flag;
89 #include "shaders/h264/mc/export.inc"
90 static unsigned long avc_mc_kernel_offset_gen4[] = {
100 #define INST_UNIT_GEN4 16
101 struct intra_kernel_header intra_kernel_header_gen4 = {
103 (INTRA_4X4_HORIZONTAL_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
104 (INTRA_4X4_DC_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
105 (INTRA_4X4_DIAG_DOWN_LEFT_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
107 (INTRA_4X4_DIAG_DOWN_RIGHT_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
108 (INTRA_4X4_VERT_RIGHT_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
109 (INTRA_4X4_HOR_DOWN_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
110 (INTRA_4X4_VERT_LEFT_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
112 (INTRA_4X4_HOR_UP_IP - INTRA_4X4_VERTICAL_IP) / INST_UNIT_GEN4,
117 (INTRA_8X8_HORIZONTAL_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
118 (INTRA_8X8_DC_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
119 (INTRA_8X8_DIAG_DOWN_LEFT_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
121 (INTRA_8X8_DIAG_DOWN_RIGHT_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
122 (INTRA_8X8_VERT_RIGHT_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
123 (INTRA_8X8_HOR_DOWN_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
124 (INTRA_8X8_VERT_LEFT_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
126 (INTRA_8X8_HOR_UP_IP - INTRA_8X8_VERTICAL_IP) / INST_UNIT_GEN4,
131 (INTRA_16x16_HORIZONTAL_IP - INTRA_16x16_VERTICAL_IP) / INST_UNIT_GEN4,
132 (INTRA_16x16_DC_IP - INTRA_16x16_VERTICAL_IP) / INST_UNIT_GEN4,
133 (INTRA_16x16_PLANE_IP - INTRA_16x16_VERTICAL_IP) / INST_UNIT_GEN4,
136 (INTRA_CHROMA_HORIZONTAL_IP - INTRA_CHROMA_DC_IP) / INST_UNIT_GEN4,
137 (INTRA_CHROMA_VERTICAL_IP - INTRA_CHROMA_DC_IP) / INST_UNIT_GEN4,
138 (INTRA_Chroma_PLANE_IP - INTRA_CHROMA_DC_IP) / INST_UNIT_GEN4,
152 (intra_Pred_4x4_Y_IP - ADD_ERROR_SB3_IP) / INST_UNIT_GEN4 * 0x1000000 +
153 (intra_Pred_4x4_Y_IP - ADD_ERROR_SB2_IP) / INST_UNIT_GEN4 * 0x10000 +
154 (intra_Pred_4x4_Y_IP - ADD_ERROR_SB1_IP) / INST_UNIT_GEN4 * 0x100 +
155 (intra_Pred_4x4_Y_IP - ADD_ERROR_SB0_IP) / INST_UNIT_GEN4
158 static uint32_t h264_avc_combined_gen4[][4] = {
159 #include "shaders/h264/mc/avc_mc.g4b"
162 static uint32_t h264_avc_null_gen4[][4] = {
163 #include "shaders/h264/mc/null.g4b"
166 static struct media_kernel h264_avc_kernels_gen4[] = {
168 "AVC combined kernel",
170 h264_avc_combined_gen4,
171 sizeof(h264_avc_combined_gen4),
179 sizeof(h264_avc_null_gen4),
185 #include "shaders/h264/mc/export.inc.gen5"
186 static unsigned long avc_mc_kernel_offset_gen5[] = {
196 #define INST_UNIT_GEN5 8
198 struct intra_kernel_header intra_kernel_header_gen5 = {
200 (INTRA_4X4_HORIZONTAL_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
201 (INTRA_4X4_DC_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
202 (INTRA_4X4_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
204 (INTRA_4X4_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
205 (INTRA_4X4_VERT_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
206 (INTRA_4X4_HOR_DOWN_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
207 (INTRA_4X4_VERT_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
209 (INTRA_4X4_HOR_UP_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
214 (INTRA_8X8_HORIZONTAL_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
215 (INTRA_8X8_DC_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
216 (INTRA_8X8_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
218 (INTRA_8X8_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
219 (INTRA_8X8_VERT_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
220 (INTRA_8X8_HOR_DOWN_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
221 (INTRA_8X8_VERT_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
223 (INTRA_8X8_HOR_UP_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
228 (INTRA_16x16_HORIZONTAL_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
229 (INTRA_16x16_DC_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
230 (INTRA_16x16_PLANE_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5) / INST_UNIT_GEN5,
233 (INTRA_CHROMA_HORIZONTAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5) / INST_UNIT_GEN5,
234 (INTRA_CHROMA_VERTICAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5) / INST_UNIT_GEN5,
235 (INTRA_Chroma_PLANE_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5) / INST_UNIT_GEN5,
249 (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB3_IP_GEN5) / INST_UNIT_GEN5 * 0x1000000 +
250 (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB2_IP_GEN5) / INST_UNIT_GEN5 * 0x10000 +
251 (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB1_IP_GEN5) / INST_UNIT_GEN5 * 0x100 +
252 (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB0_IP_GEN5) / INST_UNIT_GEN5
255 static uint32_t h264_avc_combined_gen5[][4] = {
256 #include "shaders/h264/mc/avc_mc.g4b.gen5"
259 static uint32_t h264_avc_null_gen5[][4] = {
260 #include "shaders/h264/mc/null.g4b.gen5"
263 static struct media_kernel h264_avc_kernels_gen5[] = {
265 "AVC combined kernel",
267 h264_avc_combined_gen5,
268 sizeof(h264_avc_combined_gen5),
276 sizeof(h264_avc_null_gen5),
281 #define NUM_H264_AVC_KERNELS (sizeof(h264_avc_kernels_gen4) / sizeof(h264_avc_kernels_gen4[0]))
282 struct media_kernel *h264_avc_kernels = NULL;
284 #define NUM_AVC_MC_INTERFACES (sizeof(avc_mc_kernel_offset_gen4) / sizeof(avc_mc_kernel_offset_gen4[0]))
285 static unsigned long *avc_mc_kernel_offset = NULL;
287 static struct intra_kernel_header *intra_kernel_header = NULL;
290 i965_media_h264_surface_state(VADriverContextP ctx,
292 struct object_surface *obj_surface,
293 unsigned long offset,
294 int w, int h, int pitch,
296 int vert_line_stride,
297 int vert_line_stride_ofs,
300 struct i965_driver_data *i965 = i965_driver_data(ctx);
301 struct i965_media_state *media_state = &i965->media_state;
302 struct i965_surface_state *ss;
304 uint32_t write_domain, read_domain;
306 bo = dri_bo_alloc(i965->intel.bufmgr,
308 sizeof(struct i965_surface_state), 32);
313 memset(ss, 0, sizeof(*ss));
314 ss->ss0.surface_type = I965_SURFACE_2D;
315 ss->ss0.surface_format = format;
316 ss->ss0.vert_line_stride = vert_line_stride;
317 ss->ss0.vert_line_stride_ofs = vert_line_stride_ofs;
318 ss->ss1.base_addr = obj_surface->bo->offset + offset;
319 ss->ss2.width = w - 1;
320 ss->ss2.height = h - 1;
321 ss->ss3.pitch = pitch - 1;
324 write_domain = I915_GEM_DOMAIN_RENDER;
325 read_domain = I915_GEM_DOMAIN_RENDER;
328 read_domain = I915_GEM_DOMAIN_SAMPLER;
331 dri_bo_emit_reloc(bo,
332 read_domain, write_domain,
334 offsetof(struct i965_surface_state, ss1),
338 assert(index < MAX_MEDIA_SURFACES);
339 media_state->surface_state[index].bo = bo;
343 i965_media_h264_surfaces_setup(VADriverContextP ctx,
344 struct decode_state *decode_state)
346 struct i965_driver_data *i965 = i965_driver_data(ctx);
347 struct object_surface *obj_surface;
348 VAPictureParameterBufferH264 *pic_param;
349 VAPictureH264 *va_pic;
353 assert(decode_state->pic_param && decode_state->pic_param->buffer);
354 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
357 va_pic = &pic_param->CurrPic;
358 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
359 obj_surface = SURFACE(va_pic->picture_id);
361 w = obj_surface->width;
362 h = obj_surface->height;
363 field_picture = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
364 i965_media_h264_surface_state(ctx, 0, obj_surface,
365 0, w / 4, h / (1 + field_picture), w,
368 !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD),
369 I965_SURFACEFORMAT_R8_SINT); /* Y */
370 i965_media_h264_surface_state(ctx, 1, obj_surface,
371 w * h, w / 4, h / 2 / (1 + field_picture), w,
374 !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD),
375 I965_SURFACEFORMAT_R8G8_SINT); /* INTERLEAVED U/V */
377 /* Reference Pictures */
378 for (i = 0; i < 16; i++) {
379 va_pic = &pic_param->ReferenceFrames[i];
381 if (!(va_pic->flags & VA_PICTURE_H264_INVALID)) {
382 obj_surface = SURFACE(va_pic->picture_id);
384 w = obj_surface->width;
385 h = obj_surface->height;
386 field_picture = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
387 i965_media_h264_surface_state(ctx, 2 + i, obj_surface,
388 0, w / 4, h / (1 + field_picture), w,
391 !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD),
392 I965_SURFACEFORMAT_R8_SINT); /* Y */
393 i965_media_h264_surface_state(ctx, 18 + i, obj_surface,
394 w * h, w / 4, h / 2 / (1 + field_picture), w,
397 !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD),
398 I965_SURFACEFORMAT_R8G8_SINT); /* INTERLEAVED U/V */
404 i965_media_h264_binding_table(VADriverContextP ctx)
406 struct i965_driver_data *i965 = i965_driver_data(ctx);
407 struct i965_media_state *media_state = &i965->media_state;
409 unsigned int *binding_table;
410 dri_bo *bo = media_state->binding_table.bo;
414 binding_table = bo->virtual;
415 memset(binding_table, 0, bo->size);
417 for (i = 0; i < MAX_MEDIA_SURFACES; i++) {
418 if (media_state->surface_state[i].bo) {
419 binding_table[i] = media_state->surface_state[i].bo->offset;
420 dri_bo_emit_reloc(bo,
421 I915_GEM_DOMAIN_INSTRUCTION, 0,
423 i * sizeof(*binding_table),
424 media_state->surface_state[i].bo);
428 dri_bo_unmap(media_state->binding_table.bo);
432 i965_media_h264_interface_descriptor_remap_table(VADriverContextP ctx)
434 struct i965_driver_data *i965 = i965_driver_data(ctx);
435 struct i965_media_state *media_state = &i965->media_state;
436 struct i965_interface_descriptor *desc;
440 bo = media_state->idrt.bo;
445 for (i = 0; i < NUM_AVC_MC_INTERFACES; i++) {
446 int kernel_offset = avc_mc_kernel_offset[i];
447 memset(desc, 0, sizeof(*desc));
448 desc->desc0.grf_reg_blocks = 7;
449 desc->desc0.kernel_start_pointer = (h264_avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
450 desc->desc1.const_urb_entry_read_offset = 0;
451 desc->desc1.const_urb_entry_read_len = 2;
452 desc->desc3.binding_table_entry_count = 0;
453 desc->desc3.binding_table_pointer =
454 media_state->binding_table.bo->offset >> 5; /*reloc */
456 dri_bo_emit_reloc(bo,
457 I915_GEM_DOMAIN_INSTRUCTION, 0,
458 desc->desc0.grf_reg_blocks + kernel_offset,
459 i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
460 h264_avc_kernels[H264_AVC_COMBINED].bo);
462 dri_bo_emit_reloc(bo,
463 I915_GEM_DOMAIN_INSTRUCTION, 0,
464 desc->desc3.binding_table_entry_count,
465 i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3),
466 media_state->binding_table.bo);
474 i965_media_h264_vfe_state(VADriverContextP ctx)
476 struct i965_driver_data *i965 = i965_driver_data(ctx);
477 struct i965_media_state *media_state = &i965->media_state;
478 struct i965_vfe_state *vfe_state;
481 bo = media_state->vfe_state.bo;
484 vfe_state = bo->virtual;
485 memset(vfe_state, 0, sizeof(*vfe_state));
486 vfe_state->vfe0.extend_vfe_state_present = 1;
487 vfe_state->vfe1.max_threads = media_state->urb.num_vfe_entries - 1;
488 vfe_state->vfe1.urb_entry_alloc_size = media_state->urb.size_vfe_entry - 1;
489 vfe_state->vfe1.num_urb_entries = media_state->urb.num_vfe_entries;
490 vfe_state->vfe1.vfe_mode = VFE_AVC_IT_MODE;
491 vfe_state->vfe1.children_present = 0;
492 vfe_state->vfe2.interface_descriptor_base =
493 media_state->idrt.bo->offset >> 4; /* reloc */
494 dri_bo_emit_reloc(bo,
495 I915_GEM_DOMAIN_INSTRUCTION, 0,
497 offsetof(struct i965_vfe_state, vfe2),
498 media_state->idrt.bo);
503 i965_media_h264_vfe_state_extension(VADriverContextP ctx,
504 struct decode_state *decode_state)
506 struct i965_driver_data *i965 = i965_driver_data(ctx);
507 struct i965_media_state *media_state = &i965->media_state;
508 struct i965_h264_context *i965_h264_context;
509 struct i965_vfe_state_ex *vfe_state_ex;
510 VAPictureParameterBufferH264 *pic_param;
511 VASliceParameterBufferH264 *slice_param;
512 int mbaff_frame_flag;
514 assert(media_state->private_context);
515 i965_h264_context = (struct i965_h264_context *)media_state->private_context;
517 assert(decode_state->pic_param && decode_state->pic_param->buffer);
518 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
520 assert(decode_state->slice_param && decode_state->slice_param->buffer);
521 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_param->buffer;
523 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
524 !pic_param->pic_fields.bits.field_pic_flag);
526 assert(media_state->extended_state.bo);
527 dri_bo_map(media_state->extended_state.bo, 1);
528 assert(media_state->extended_state.bo->virtual);
529 vfe_state_ex = media_state->extended_state.bo->virtual;
530 memset(vfe_state_ex, 0, sizeof(*vfe_state_ex));
533 * Indirect data buffer:
534 * --------------------------------------------------------
535 * | Motion Vectors | Weight/Offset data | Residual data |
536 * --------------------------------------------------------
537 * R4-R7: Motion Vectors
538 * R8-R9: Weight/Offset
539 * R10-R33: Residual data
541 vfe_state_ex->vfex1.avc.residual_data_fix_offset_flag = !!RESIDUAL_DATA_OFFSET;
542 vfe_state_ex->vfex1.avc.residual_data_offset = RESIDUAL_DATA_OFFSET;
544 if (slice_param->slice_type == SLICE_TYPE_I)
545 vfe_state_ex->vfex1.avc.sub_field_present_flag = PRESENT_NOMV; /* NoMV */
547 vfe_state_ex->vfex1.avc.sub_field_present_flag = PRESENT_MV_WO; /* Both MV and W/O */
549 if (vfe_state_ex->vfex1.avc.sub_field_present_flag == 0) {
550 vfe_state_ex->vfex1.avc.weight_grf_offset = 0;
551 vfe_state_ex->vfex1.avc.residual_grf_offset = 0;
553 vfe_state_ex->vfex1.avc.weight_grf_offset = 4;
554 vfe_state_ex->vfex1.avc.residual_grf_offset = 6;
557 if (!pic_param->pic_fields.bits.field_pic_flag) {
558 if (mbaff_frame_flag) {
559 vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16;
560 vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8;
561 vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4;
562 vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM;
563 vfe_state_ex->remap_table0.remap_index_4 = MBAFF_MOTION;
564 vfe_state_ex->remap_table0.remap_index_5 = MBAFF_MOTION;
565 vfe_state_ex->remap_table0.remap_index_6 = MBAFF_MOTION;
566 vfe_state_ex->remap_table0.remap_index_7 = MBAFF_MOTION;
568 vfe_state_ex->remap_table1.remap_index_8 = MBAFF_MOTION;
569 vfe_state_ex->remap_table1.remap_index_9 = MBAFF_MOTION;
570 vfe_state_ex->remap_table1.remap_index_10 = MBAFF_MOTION;
571 vfe_state_ex->remap_table1.remap_index_11 = MBAFF_MOTION;
572 vfe_state_ex->remap_table1.remap_index_12 = MBAFF_MOTION;
573 vfe_state_ex->remap_table1.remap_index_13 = MBAFF_MOTION;
574 vfe_state_ex->remap_table1.remap_index_14 = MBAFF_MOTION;
575 vfe_state_ex->remap_table1.remap_index_15 = MBAFF_MOTION;
577 vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16;
578 vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8;
579 vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4;
580 vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM;
581 vfe_state_ex->remap_table0.remap_index_4 = FRAMEMB_MOTION;
582 vfe_state_ex->remap_table0.remap_index_5 = FRAMEMB_MOTION;
583 vfe_state_ex->remap_table0.remap_index_6 = FRAMEMB_MOTION;
584 vfe_state_ex->remap_table0.remap_index_7 = FRAMEMB_MOTION;
586 vfe_state_ex->remap_table1.remap_index_8 = FRAMEMB_MOTION;
587 vfe_state_ex->remap_table1.remap_index_9 = FRAMEMB_MOTION;
588 vfe_state_ex->remap_table1.remap_index_10 = FRAMEMB_MOTION;
589 vfe_state_ex->remap_table1.remap_index_11 = FRAMEMB_MOTION;
590 vfe_state_ex->remap_table1.remap_index_12 = FRAMEMB_MOTION;
591 vfe_state_ex->remap_table1.remap_index_13 = FRAMEMB_MOTION;
592 vfe_state_ex->remap_table1.remap_index_14 = FRAMEMB_MOTION;
593 vfe_state_ex->remap_table1.remap_index_15 = FRAMEMB_MOTION;
596 vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16;
597 vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8;
598 vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4;
599 vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM;
600 vfe_state_ex->remap_table0.remap_index_4 = FIELDMB_MOTION;
601 vfe_state_ex->remap_table0.remap_index_5 = FIELDMB_MOTION;
602 vfe_state_ex->remap_table0.remap_index_6 = FIELDMB_MOTION;
603 vfe_state_ex->remap_table0.remap_index_7 = FIELDMB_MOTION;
605 vfe_state_ex->remap_table1.remap_index_8 = FIELDMB_MOTION;
606 vfe_state_ex->remap_table1.remap_index_9 = FIELDMB_MOTION;
607 vfe_state_ex->remap_table1.remap_index_10 = FIELDMB_MOTION;
608 vfe_state_ex->remap_table1.remap_index_11 = FIELDMB_MOTION;
609 vfe_state_ex->remap_table1.remap_index_12 = FIELDMB_MOTION;
610 vfe_state_ex->remap_table1.remap_index_13 = FIELDMB_MOTION;
611 vfe_state_ex->remap_table1.remap_index_14 = FIELDMB_MOTION;
612 vfe_state_ex->remap_table1.remap_index_15 = FIELDMB_MOTION;
615 if (i965_h264_context->use_avc_hw_scoreboard) {
616 vfe_state_ex->scoreboard0.enable = 1;
617 vfe_state_ex->scoreboard0.type = SCOREBOARD_STALLING;
618 vfe_state_ex->scoreboard0.mask = 0xff;
620 vfe_state_ex->scoreboard1.delta_x0 = -1;
621 vfe_state_ex->scoreboard1.delta_y0 = 0;
622 vfe_state_ex->scoreboard1.delta_x1 = 0;
623 vfe_state_ex->scoreboard1.delta_y1 = -1;
624 vfe_state_ex->scoreboard1.delta_x2 = 1;
625 vfe_state_ex->scoreboard1.delta_y2 = -1;
626 vfe_state_ex->scoreboard1.delta_x3 = -1;
627 vfe_state_ex->scoreboard1.delta_y3 = -1;
629 vfe_state_ex->scoreboard2.delta_x4 = -1;
630 vfe_state_ex->scoreboard2.delta_y4 = 1;
631 vfe_state_ex->scoreboard2.delta_x5 = 0;
632 vfe_state_ex->scoreboard2.delta_y5 = -2;
633 vfe_state_ex->scoreboard2.delta_x6 = 1;
634 vfe_state_ex->scoreboard2.delta_y6 = -2;
635 vfe_state_ex->scoreboard2.delta_x7 = -1;
636 vfe_state_ex->scoreboard2.delta_y7 = -2;
639 dri_bo_unmap(media_state->extended_state.bo);
643 i965_media_h264_upload_constants(VADriverContextP ctx, struct decode_state *decode_state)
645 struct i965_driver_data *i965 = i965_driver_data(ctx);
646 struct i965_media_state *media_state = &i965->media_state;
647 struct i965_h264_context *i965_h264_context;
648 unsigned char *constant_buffer;
649 VASliceParameterBufferH264 *slice_param;
651 assert(media_state->private_context);
652 i965_h264_context = (struct i965_h264_context *)media_state->private_context;
654 assert(decode_state->slice_param && decode_state->slice_param->buffer);
655 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_param->buffer;
657 dri_bo_map(media_state->curbe.bo, 1);
658 assert(media_state->curbe.bo->virtual);
659 constant_buffer = media_state->curbe.bo->virtual;
661 /* HW solution for W=128 */
662 if (i965_h264_context->use_hw_w128) {
663 memcpy(constant_buffer, intra_kernel_header, sizeof(*intra_kernel_header));
665 if (slice_param->slice_type == SLICE_TYPE_I) {
666 memcpy(constant_buffer, intra_kernel_header, sizeof(*intra_kernel_header));
668 /* FIXME: Need to upload CURBE data to inter kernel interface
669 * to support weighted prediction work-around
671 *(short *)constant_buffer = i965_h264_context->weight128_offset0;
672 constant_buffer += 2;
673 *(char *)constant_buffer = i965_h264_context->weight128_offset0_flag;
675 *constant_buffer = 0;
679 dri_bo_unmap(media_state->curbe.bo);
683 i965_media_h264_states_setup(VADriverContextP ctx, struct decode_state *decode_state)
685 struct i965_driver_data *i965 = i965_driver_data(ctx);
686 struct i965_media_state *media_state = &i965->media_state;
687 struct i965_h264_context *i965_h264_context;
688 VAPictureParameterBufferH264 *pic_param;
689 unsigned int *object_command;
691 assert(media_state->private_context);
692 i965_h264_context = (struct i965_h264_context *)media_state->private_context;
693 assert(decode_state->pic_param && decode_state->pic_param->buffer);
694 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
696 i965_h264_context->picture.width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
697 i965_h264_context->picture.height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff) /
698 (1 + !!pic_param->pic_fields.bits.field_pic_flag); /* picture height */
699 i965_h264_context->picture.mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
700 !pic_param->pic_fields.bits.field_pic_flag);
702 i965_h264_context->avc_it_command_mb_info.mbs = (i965_h264_context->picture.width_in_mbs *
703 i965_h264_context->picture.height_in_mbs);
705 i965_avc_bsd_pipeline(ctx, decode_state);
707 dri_bo_map(i965_h264_context->avc_it_command_mb_info.bo, True);
708 assert(i965_h264_context->avc_it_command_mb_info.bo->virtual);
709 object_command = i965_h264_context->avc_it_command_mb_info.bo->virtual;
710 memset(object_command, 0, i965_h264_context->avc_it_command_mb_info.mbs * i965_h264_context->use_avc_hw_scoreboard * MB_CMD_IN_BYTES);
711 object_command += i965_h264_context->avc_it_command_mb_info.mbs * (1 + i965_h264_context->use_avc_hw_scoreboard) * MB_CMD_IN_DWS;
712 *object_command = MI_BATCH_BUFFER_END;
713 dri_bo_unmap(i965_h264_context->avc_it_command_mb_info.bo);
715 i965_avc_hw_scoreboard(ctx, decode_state);
717 i965_media_h264_surfaces_setup(ctx, decode_state);
718 i965_media_h264_binding_table(ctx);
719 i965_media_h264_interface_descriptor_remap_table(ctx);
720 i965_media_h264_vfe_state_extension(ctx, decode_state);
721 i965_media_h264_vfe_state(ctx);
722 i965_media_h264_upload_constants(ctx, decode_state);
726 i965_media_h264_objects(VADriverContextP ctx, struct decode_state *decode_state)
728 struct i965_driver_data *i965 = i965_driver_data(ctx);
729 struct i965_media_state *media_state = &i965->media_state;
730 struct i965_h264_context *i965_h264_context;
732 assert(media_state->private_context);
733 i965_h264_context = (struct i965_h264_context *)media_state->private_context;
736 OUT_BATCH(ctx, MI_BATCH_BUFFER_START | (2 << 6));
737 OUT_RELOC(ctx, i965_h264_context->avc_it_command_mb_info.bo,
738 I915_GEM_DOMAIN_COMMAND, 0,
744 i965_media_h264_decode_init(VADriverContextP ctx)
746 struct i965_driver_data *i965 = i965_driver_data(ctx);
747 struct i965_media_state *media_state = &i965->media_state;
748 struct i965_h264_context *i965_h264_context;
751 assert(media_state->private_context);
752 i965_h264_context = media_state->private_context;
754 dri_bo_unreference(i965_h264_context->avc_it_command_mb_info.bo);
755 bo = dri_bo_alloc(i965->intel.bufmgr,
756 "avc it command mb info",
757 0x80000 * (1 + i965_h264_context->use_avc_hw_scoreboard), /* at least 522240 bytes */
760 i965_h264_context->avc_it_command_mb_info.bo = bo;
762 dri_bo_unreference(i965_h264_context->avc_it_data.bo);
763 bo = dri_bo_alloc(i965->intel.bufmgr,
765 0x1000000, /* at least 16711680 bytes */
768 i965_h264_context->avc_it_data.bo = bo;
769 i965_h264_context->avc_it_data.write_offset = 0;
770 dri_bo_unreference(media_state->indirect_object.bo);
771 media_state->indirect_object.bo = bo;
772 dri_bo_reference(media_state->indirect_object.bo);
773 media_state->indirect_object.offset = i965_h264_context->avc_it_data.write_offset;
776 i965_avc_bsd_decode_init(ctx);
779 i965_avc_hw_scoreboard_decode_init(ctx);
781 /* for Media pipeline */
782 media_state->extended_state.enabled = 1;
783 dri_bo_unreference(media_state->extended_state.bo);
784 bo = dri_bo_alloc(i965->intel.bufmgr,
786 sizeof(struct i965_vfe_state_ex), 32);
788 media_state->extended_state.bo = bo;
791 if (IS_IRONLAKE(i965->intel.device_id)) {
792 media_state->urb.num_vfe_entries = 63;
794 media_state->urb.num_vfe_entries = 23;
797 media_state->urb.size_vfe_entry = 16;
799 media_state->urb.num_cs_entries = 1;
800 media_state->urb.size_cs_entry = 1;
802 media_state->urb.vfe_start = 0;
803 media_state->urb.cs_start = media_state->urb.vfe_start +
804 media_state->urb.num_vfe_entries * media_state->urb.size_vfe_entry;
805 assert(media_state->urb.cs_start +
806 media_state->urb.num_cs_entries * media_state->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
809 media_state->media_states_setup = i965_media_h264_states_setup;
810 media_state->media_objects = i965_media_h264_objects;
814 i965_media_h264_init(VADriverContextP ctx)
816 struct i965_driver_data *i965 = i965_driver_data(ctx);
817 struct i965_media_state *media_state = &i965->media_state;
818 struct i965_h264_context *i965_h264_context;
821 i965_h264_context = calloc(1, sizeof(struct i965_h264_context));
824 assert(NUM_H264_AVC_KERNELS == (sizeof(h264_avc_kernels_gen5) /
825 sizeof(h264_avc_kernels_gen5[0])));
826 assert(NUM_AVC_MC_INTERFACES == (sizeof(avc_mc_kernel_offset_gen5) /
827 sizeof(avc_mc_kernel_offset_gen5[0])));
829 if (IS_IRONLAKE(i965->intel.device_id)) {
830 h264_avc_kernels = h264_avc_kernels_gen5;
831 avc_mc_kernel_offset = avc_mc_kernel_offset_gen5;
832 intra_kernel_header = &intra_kernel_header_gen5;
833 i965_h264_context->use_avc_hw_scoreboard = 1;
834 i965_h264_context->use_hw_w128 = 1;
836 h264_avc_kernels = h264_avc_kernels_gen4;
837 avc_mc_kernel_offset = avc_mc_kernel_offset_gen4;
838 intra_kernel_header = &intra_kernel_header_gen4;
839 i965_h264_context->use_avc_hw_scoreboard = 0;
840 i965_h264_context->use_hw_w128 = 0;
843 for (i = 0; i < NUM_H264_AVC_KERNELS; i++) {
844 struct media_kernel *kernel = &h264_avc_kernels[i];
845 kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
849 dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
852 media_state->private_context = i965_h264_context;
857 i965_media_h264_ternimate(VADriverContextP ctx)
859 struct i965_driver_data *i965 = i965_driver_data(ctx);
860 struct i965_media_state *media_state = &i965->media_state;
861 struct i965_h264_context *i965_h264_context;
864 if (media_state->private_context) {
865 i965_h264_context = (struct i965_h264_context *)media_state->private_context;
866 i965_avc_hw_scoreboard_ternimate(&i965_h264_context->avc_hw_scoreboard_context);
867 i965_avc_bsd_ternimate(&i965_h264_context->i965_avc_bsd_context);
868 dri_bo_unreference(i965_h264_context->avc_it_command_mb_info.bo);
869 dri_bo_unreference(i965_h264_context->avc_it_data.bo);
870 free(i965_h264_context);
871 media_state->private_context = NULL;
874 for (i = 0; i < NUM_H264_AVC_KERNELS; i++) {
875 struct media_kernel *kernel = &h264_avc_kernels[i];
877 dri_bo_unreference(kernel->bo);