i965_drv_video/i965_render.c

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Xiang Haihao <haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 /*
  31  * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <assert.h>
  38
  39 #include <va/va_backend.h>
  40 #include "va/x11/va_dricommon.h"
  41
  42 #include "intel_batchbuffer.h"
  43 #include "intel_driver.h"
  44
  45 #include "i965_defines.h"
  46 #include "i965_render.h"
  47 #include "i965_drv_video.h"
  48
  49 #define SF_KERNEL_NUM_GRF       16
  50 #define SF_MAX_THREADS          1
  51
  52 static const unsigned int sf_kernel_static[][4] =
  53 {
  54 #include "shaders/render/exa_sf.g4b"
  55 };
  56
  57 #define PS_KERNEL_NUM_GRF       32
  58 #define PS_MAX_THREADS          32
  59
  60 #define I965_GRF_BLOCKS(nreg)   ((nreg + 15) / 16 - 1)
  61
  62 static const unsigned int ps_kernel_static[][4] =
  63 {
  64 #include "shaders/render/exa_wm_xy.g4b"
  65 #include "shaders/render/exa_wm_src_affine.g4b"
  66 #include "shaders/render/exa_wm_src_sample_planar.g4b"
  67 #include "shaders/render/exa_wm_yuv_rgb.g4b"
  68 #include "shaders/render/exa_wm_write.g4b"
  69 };
  70 static const unsigned int ps_subpic_kernel_static[][4] =
  71 {
  72 #include "shaders/render/exa_wm_xy.g4b"
  73 #include "shaders/render/exa_wm_src_affine.g4b"
  74 #include "shaders/render/exa_wm_src_sample_argb.g4b"
  75 #include "shaders/render/exa_wm_write.g4b"
  76 };
  77
  78 /* On IRONLAKE */
  79 static const unsigned int sf_kernel_static_gen5[][4] =
  80 {
  81 #include "shaders/render/exa_sf.g4b.gen5"
  82 };
  83
  84 static const unsigned int ps_kernel_static_gen5[][4] =
  85 {
  86 #include "shaders/render/exa_wm_xy.g4b.gen5"
  87 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
  88 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
  89 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
  90 #include "shaders/render/exa_wm_write.g4b.gen5"
  91 };
  92 static const unsigned int ps_subpic_kernel_static_gen5[][4] =
  93 {
  94 #include "shaders/render/exa_wm_xy.g4b.gen5"
  95 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
  96 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
  97 #include "shaders/render/exa_wm_write.g4b.gen5"
  98 };
  99
 100 /* programs for Sandybridge */
 101 static const unsigned int sf_kernel_static_gen6[][4] =
 102 {
 103 };
 104
 105 static const uint32_t ps_kernel_static_gen6[][4] = {
 106 #include "shaders/render/exa_wm_src_affine.g6b"
 107 #include "shaders/render/exa_wm_src_sample_planar.g6b"
 108 #include "shaders/render/exa_wm_yuv_rgb.g6b"
 109 #include "shaders/render/exa_wm_write.g6b"
 110 };
 111
 112 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
 113 #include "shaders/render/exa_wm_src_affine.g6b"
 114 #include "shaders/render/exa_wm_src_sample_argb.g6b"
 115 #include "shaders/render/exa_wm_write.g6b"
 116 };
 117
 118 #define SURFACE_STATE_PADDED_SIZE       ALIGN(sizeof(struct i965_surface_state), 32)
 119 #define SURFACE_STATE_OFFSET(index)     (SURFACE_STATE_PADDED_SIZE * index)
 120 #define BINDING_TABLE_OFFSET            SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
 121
 122 static uint32_t float_to_uint (float f)
 123 {
 124     union {
 125         uint32_t i;
 126         float f;
 127     } x;
 128
 129     x.f = f;
 130     return x.i;
 131 }
 132
 133 enum
 134 {
 135     SF_KERNEL = 0,
 136     PS_KERNEL,
 137     PS_SUBPIC_KERNEL
 138 };
 139
 140 struct render_kernel
 141 {
 142     char *name;
 143     const unsigned int (*bin)[4];
 144     int size;
 145     dri_bo *bo;
 146 };
 147
 148 static struct render_kernel render_kernels_gen4[] = {
 149     {
 150         "SF",
 151         sf_kernel_static,
 152         sizeof(sf_kernel_static),
 153         NULL
 154     },
 155     {
 156         "PS",
 157         ps_kernel_static,
 158         sizeof(ps_kernel_static),
 159         NULL
 160     },
 161
 162     {
 163         "PS_SUBPIC",
 164         ps_subpic_kernel_static,
 165         sizeof(ps_subpic_kernel_static),
 166         NULL
 167     }
 168 };
 169
 170 static struct render_kernel render_kernels_gen5[] = {
 171     {
 172         "SF",
 173         sf_kernel_static_gen5,
 174         sizeof(sf_kernel_static_gen5),
 175         NULL
 176     },
 177     {
 178         "PS",
 179         ps_kernel_static_gen5,
 180         sizeof(ps_kernel_static_gen5),
 181         NULL
 182     },
 183
 184     {
 185         "PS_SUBPIC",
 186         ps_subpic_kernel_static_gen5,
 187         sizeof(ps_subpic_kernel_static_gen5),
 188         NULL
 189     }
 190 };
 191
 192 static struct render_kernel render_kernels_gen6[] = {
 193     {
 194         "SF",
 195         sf_kernel_static_gen6,
 196         sizeof(sf_kernel_static_gen6),
 197         NULL
 198     },
 199     {
 200         "PS",
 201         ps_kernel_static_gen6,
 202         sizeof(ps_kernel_static_gen6),
 203         NULL
 204     },
 205
 206     {
 207         "PS_SUBPIC",
 208         ps_subpic_kernel_static_gen6,
 209         sizeof(ps_subpic_kernel_static_gen6),
 210         NULL
 211     }
 212 };
 213
 214 static struct render_kernel *render_kernels = NULL;
 215
 216 #define NUM_RENDER_KERNEL (sizeof(render_kernels_gen4)/sizeof(render_kernels_gen4[0]))
 217
 218 #define URB_VS_ENTRIES        8
 219 #define URB_VS_ENTRY_SIZE     1
 220
 221 #define URB_GS_ENTRIES        0
 222 #define URB_GS_ENTRY_SIZE     0
 223
 224 #define URB_CLIP_ENTRIES      0
 225 #define URB_CLIP_ENTRY_SIZE   0
 226
 227 #define URB_SF_ENTRIES        1
 228 #define URB_SF_ENTRY_SIZE     2
 229
 230 #define URB_CS_ENTRIES        1
 231 #define URB_CS_ENTRY_SIZE     1
 232
 233 static void
 234 i965_render_vs_unit(VADriverContextP ctx)
 235 {
 236     struct i965_driver_data *i965 = i965_driver_data(ctx);
 237     struct i965_render_state *render_state = &i965->render_state;
 238     struct i965_vs_unit_state *vs_state;
 239
 240     dri_bo_map(render_state->vs.state, 1);
 241     assert(render_state->vs.state->virtual);
 242     vs_state = render_state->vs.state->virtual;
 243     memset(vs_state, 0, sizeof(*vs_state));
 244
 245     if (IS_IRONLAKE(i965->intel.device_id))
 246         vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
 247     else
 248         vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
 249
 250     vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
 251     vs_state->vs6.vs_enable = 0;
 252     vs_state->vs6.vert_cache_disable = 1;
 253
 254     dri_bo_unmap(render_state->vs.state);
 255 }
 256
 257 static void
 258 i965_render_sf_unit(VADriverContextP ctx)
 259 {
 260     struct i965_driver_data *i965 = i965_driver_data(ctx);
 261     struct i965_render_state *render_state = &i965->render_state;
 262     struct i965_sf_unit_state *sf_state;
 263
 264     dri_bo_map(render_state->sf.state, 1);
 265     assert(render_state->sf.state->virtual);
 266     sf_state = render_state->sf.state->virtual;
 267     memset(sf_state, 0, sizeof(*sf_state));
 268
 269     sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
 270     sf_state->thread0.kernel_start_pointer = render_kernels[SF_KERNEL].bo->offset >> 6;
 271
 272     sf_state->sf1.single_program_flow = 1; /* XXX */
 273     sf_state->sf1.binding_table_entry_count = 0;
 274     sf_state->sf1.thread_priority = 0;
 275     sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
 276     sf_state->sf1.illegal_op_exception_enable = 1;
 277     sf_state->sf1.mask_stack_exception_enable = 1;
 278     sf_state->sf1.sw_exception_enable = 1;
 279
 280     /* scratch space is not used in our kernel */
 281     sf_state->thread2.per_thread_scratch_space = 0;
 282     sf_state->thread2.scratch_space_base_pointer = 0;
 283
 284     sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
 285     sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
 286     sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
 287     sf_state->thread3.urb_entry_read_offset = 0;
 288     sf_state->thread3.dispatch_grf_start_reg = 3;
 289
 290     sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
 291     sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
 292     sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
 293     sf_state->thread4.stats_enable = 1;
 294
 295     sf_state->sf5.viewport_transform = 0; /* skip viewport */
 296
 297     sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
 298     sf_state->sf6.scissor = 0;
 299
 300     sf_state->sf7.trifan_pv = 2;
 301
 302     sf_state->sf6.dest_org_vbias = 0x8;
 303     sf_state->sf6.dest_org_hbias = 0x8;
 304
 305     dri_bo_emit_reloc(render_state->sf.state,
 306                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 307                       sf_state->thread0.grf_reg_count << 1,
 308                       offsetof(struct i965_sf_unit_state, thread0),
 309                       render_kernels[SF_KERNEL].bo);
 310
 311     dri_bo_unmap(render_state->sf.state);
 312 }
 313
 314 static void
 315 i965_render_sampler(VADriverContextP ctx)
 316 {
 317     struct i965_driver_data *i965 = i965_driver_data(ctx);
 318     struct i965_render_state *render_state = &i965->render_state;
 319     struct i965_sampler_state *sampler_state;
 320     int i;
 321
 322     assert(render_state->wm.sampler_count > 0);
 323     assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
 324
 325     dri_bo_map(render_state->wm.sampler, 1);
 326     assert(render_state->wm.sampler->virtual);
 327     sampler_state = render_state->wm.sampler->virtual;
 328     for (i = 0; i < render_state->wm.sampler_count; i++) {
 329         memset(sampler_state, 0, sizeof(*sampler_state));
 330         sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
 331         sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
 332         sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 333         sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 334         sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 335         sampler_state++;
 336     }
 337
 338     dri_bo_unmap(render_state->wm.sampler);
 339 }
 340 static void
 341 i965_subpic_render_wm_unit(VADriverContextP ctx)
 342 {
 343     struct i965_driver_data *i965 = i965_driver_data(ctx);
 344     struct i965_render_state *render_state = &i965->render_state;
 345     struct i965_wm_unit_state *wm_state;
 346
 347     assert(render_state->wm.sampler);
 348
 349     dri_bo_map(render_state->wm.state, 1);
 350     assert(render_state->wm.state->virtual);
 351     wm_state = render_state->wm.state->virtual;
 352     memset(wm_state, 0, sizeof(*wm_state));
 353
 354     wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
 355     wm_state->thread0.kernel_start_pointer = render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
 356
 357     wm_state->thread1.single_program_flow = 1; /* XXX */
 358
 359     if (IS_IRONLAKE(i965->intel.device_id))
 360         wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
 361     else
 362         wm_state->thread1.binding_table_entry_count = 7;
 363
 364     wm_state->thread2.scratch_space_base_pointer = 0;
 365     wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
 366
 367     wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
 368     wm_state->thread3.const_urb_entry_read_length = 0;
 369     wm_state->thread3.const_urb_entry_read_offset = 0;
 370     wm_state->thread3.urb_entry_read_length = 1; /* XXX */
 371     wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
 372
 373     wm_state->wm4.stats_enable = 0;
 374     wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
 375
 376     if (IS_IRONLAKE(i965->intel.device_id)) {
 377         wm_state->wm4.sampler_count = 0;        /* hardware requirement */
 378         wm_state->wm5.max_threads = 12 * 6 - 1;
 379     } else {
 380         wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
 381         wm_state->wm5.max_threads = 10 * 5 - 1;
 382     }
 383
 384     wm_state->wm5.thread_dispatch_enable = 1;
 385     wm_state->wm5.enable_16_pix = 1;
 386     wm_state->wm5.enable_8_pix = 0;
 387     wm_state->wm5.early_depth_test = 1;
 388
 389     dri_bo_emit_reloc(render_state->wm.state,
 390                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 391                       wm_state->thread0.grf_reg_count << 1,
 392                       offsetof(struct i965_wm_unit_state, thread0),
 393                       render_kernels[PS_SUBPIC_KERNEL].bo);
 394
 395     dri_bo_emit_reloc(render_state->wm.state,
 396                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 397                       wm_state->wm4.sampler_count << 2,
 398                       offsetof(struct i965_wm_unit_state, wm4),
 399                       render_state->wm.sampler);
 400
 401     dri_bo_unmap(render_state->wm.state);
 402 }
 403
 404
 405 static void
 406 i965_render_wm_unit(VADriverContextP ctx)
 407 {
 408     struct i965_driver_data *i965 = i965_driver_data(ctx);
 409     struct i965_render_state *render_state = &i965->render_state;
 410     struct i965_wm_unit_state *wm_state;
 411
 412     assert(render_state->wm.sampler);
 413
 414     dri_bo_map(render_state->wm.state, 1);
 415     assert(render_state->wm.state->virtual);
 416     wm_state = render_state->wm.state->virtual;
 417     memset(wm_state, 0, sizeof(*wm_state));
 418
 419     wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
 420     wm_state->thread0.kernel_start_pointer = render_kernels[PS_KERNEL].bo->offset >> 6;
 421
 422     wm_state->thread1.single_program_flow = 1; /* XXX */
 423
 424     if (IS_IRONLAKE(i965->intel.device_id))
 425         wm_state->thread1.binding_table_entry_count = 0;        /* hardware requirement */
 426     else
 427         wm_state->thread1.binding_table_entry_count = 7;
 428
 429     wm_state->thread2.scratch_space_base_pointer = 0;
 430     wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
 431
 432     wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
 433     wm_state->thread3.const_urb_entry_read_length = 1;
 434     wm_state->thread3.const_urb_entry_read_offset = 0;
 435     wm_state->thread3.urb_entry_read_length = 1; /* XXX */
 436     wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
 437
 438     wm_state->wm4.stats_enable = 0;
 439     wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
 440
 441     if (IS_IRONLAKE(i965->intel.device_id)) {
 442         wm_state->wm4.sampler_count = 0;        /* hardware requirement */
 443         wm_state->wm5.max_threads = 12 * 6 - 1;
 444     } else {
 445         wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
 446         wm_state->wm5.max_threads = 10 * 5 - 1;
 447     }
 448
 449     wm_state->wm5.thread_dispatch_enable = 1;
 450     wm_state->wm5.enable_16_pix = 1;
 451     wm_state->wm5.enable_8_pix = 0;
 452     wm_state->wm5.early_depth_test = 1;
 453
 454     dri_bo_emit_reloc(render_state->wm.state,
 455                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 456                       wm_state->thread0.grf_reg_count << 1,
 457                       offsetof(struct i965_wm_unit_state, thread0),
 458                       render_kernels[PS_KERNEL].bo);
 459
 460     dri_bo_emit_reloc(render_state->wm.state,
 461                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 462                       wm_state->wm4.sampler_count << 2,
 463                       offsetof(struct i965_wm_unit_state, wm4),
 464                       render_state->wm.sampler);
 465
 466     dri_bo_unmap(render_state->wm.state);
 467 }
 468
 469 static void
 470 i965_render_cc_viewport(VADriverContextP ctx)
 471 {
 472     struct i965_driver_data *i965 = i965_driver_data(ctx);
 473     struct i965_render_state *render_state = &i965->render_state;
 474     struct i965_cc_viewport *cc_viewport;
 475
 476     dri_bo_map(render_state->cc.viewport, 1);
 477     assert(render_state->cc.viewport->virtual);
 478     cc_viewport = render_state->cc.viewport->virtual;
 479     memset(cc_viewport, 0, sizeof(*cc_viewport));
 480
 481     cc_viewport->min_depth = -1.e35;
 482     cc_viewport->max_depth = 1.e35;
 483
 484     dri_bo_unmap(render_state->cc.viewport);
 485 }
 486
 487 static void
 488 i965_subpic_render_cc_unit(VADriverContextP ctx)
 489 {
 490     struct i965_driver_data *i965 = i965_driver_data(ctx);
 491     struct i965_render_state *render_state = &i965->render_state;
 492     struct i965_cc_unit_state *cc_state;
 493
 494     assert(render_state->cc.viewport);
 495
 496     dri_bo_map(render_state->cc.state, 1);
 497     assert(render_state->cc.state->virtual);
 498     cc_state = render_state->cc.state->virtual;
 499     memset(cc_state, 0, sizeof(*cc_state));
 500
 501     cc_state->cc0.stencil_enable = 0;   /* disable stencil */
 502     cc_state->cc2.depth_test = 0;       /* disable depth test */
 503     cc_state->cc2.logicop_enable = 0;   /* disable logic op */
 504     cc_state->cc3.ia_blend_enable = 0 ;  /* blend alpha just like colors */
 505     cc_state->cc3.blend_enable = 1;     /* enable color blend */
 506     cc_state->cc3.alpha_test = 0;       /* disable alpha test */
 507     cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8;       /*store alpha value with UNORM8 */
 508     cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS;       /*pass if less than the reference */
 509     cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
 510
 511     cc_state->cc5.dither_enable = 0;    /* disable dither */
 512     cc_state->cc5.logicop_func = 0xc;   /* WHITE */
 513     cc_state->cc5.statistics_enable = 1;
 514     cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
 515     cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
 516     cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
 517
 518     cc_state->cc6.clamp_post_alpha_blend = 0;
 519     cc_state->cc6.clamp_pre_alpha_blend  =0;
 520
 521     /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
 522     cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
 523     cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
 524     cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
 525
 526     /*alpha test reference*/
 527     cc_state->cc7.alpha_ref.f =0.0 ;
 528
 529
 530     dri_bo_emit_reloc(render_state->cc.state,
 531                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 532                       0,
 533                       offsetof(struct i965_cc_unit_state, cc4),
 534                       render_state->cc.viewport);
 535
 536     dri_bo_unmap(render_state->cc.state);
 537 }
 538
 539
 540 static void
 541 i965_render_cc_unit(VADriverContextP ctx)
 542 {
 543     struct i965_driver_data *i965 = i965_driver_data(ctx);
 544     struct i965_render_state *render_state = &i965->render_state;
 545     struct i965_cc_unit_state *cc_state;
 546
 547     assert(render_state->cc.viewport);
 548
 549     dri_bo_map(render_state->cc.state, 1);
 550     assert(render_state->cc.state->virtual);
 551     cc_state = render_state->cc.state->virtual;
 552     memset(cc_state, 0, sizeof(*cc_state));
 553
 554     cc_state->cc0.stencil_enable = 0;   /* disable stencil */
 555     cc_state->cc2.depth_test = 0;       /* disable depth test */
 556     cc_state->cc2.logicop_enable = 1;   /* enable logic op */
 557     cc_state->cc3.ia_blend_enable = 0;  /* blend alpha just like colors */
 558     cc_state->cc3.blend_enable = 0;     /* disable color blend */
 559     cc_state->cc3.alpha_test = 0;       /* disable alpha test */
 560     cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
 561
 562     cc_state->cc5.dither_enable = 0;    /* disable dither */
 563     cc_state->cc5.logicop_func = 0xc;   /* WHITE */
 564     cc_state->cc5.statistics_enable = 1;
 565     cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
 566     cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
 567     cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
 568
 569     dri_bo_emit_reloc(render_state->cc.state,
 570                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 571                       0,
 572                       offsetof(struct i965_cc_unit_state, cc4),
 573                       render_state->cc.viewport);
 574
 575     dri_bo_unmap(render_state->cc.state);
 576 }
 577
 578 static void
 579 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 580 {
 581     switch (tiling) {
 582     case I915_TILING_NONE:
 583         ss->ss3.tiled_surface = 0;
 584         ss->ss3.tile_walk = 0;
 585         break;
 586     case I915_TILING_X:
 587         ss->ss3.tiled_surface = 1;
 588         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 589         break;
 590     case I915_TILING_Y:
 591         ss->ss3.tiled_surface = 1;
 592         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 593         break;
 594     }
 595 }
 596
 597 static void
 598 i965_render_src_surface_state(VADriverContextP ctx,
 599                               int index,
 600                               dri_bo *region,
 601                               unsigned long offset,
 602                               int w, int h,
 603                               int pitch, int format)
 604 {
 605     struct i965_driver_data *i965 = i965_driver_data(ctx);
 606     struct i965_render_state *render_state = &i965->render_state;
 607     struct i965_surface_state *ss;
 608     dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
 609     unsigned int tiling;
 610     unsigned int swizzle;
 611
 612     assert(index < MAX_RENDER_SURFACES);
 613
 614     dri_bo_map(ss_bo, 1);
 615     assert(ss_bo->virtual);
 616     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 617     memset(ss, 0, sizeof(*ss));
 618     ss->ss0.surface_type = I965_SURFACE_2D;
 619     ss->ss0.surface_format = format;
 620     ss->ss0.writedisable_alpha = 0;
 621     ss->ss0.writedisable_red = 0;
 622     ss->ss0.writedisable_green = 0;
 623     ss->ss0.writedisable_blue = 0;
 624     ss->ss0.color_blend = 1;
 625     ss->ss0.vert_line_stride = 0;
 626     ss->ss0.vert_line_stride_ofs = 0;
 627     ss->ss0.mipmap_layout_mode = 0;
 628     ss->ss0.render_cache_read_mode = 0;
 629
 630     ss->ss1.base_addr = region->offset + offset;
 631
 632     ss->ss2.width = w - 1;
 633     ss->ss2.height = h - 1;
 634     ss->ss2.mip_count = 0;
 635     ss->ss2.render_target_rotation = 0;
 636
 637     ss->ss3.pitch = pitch - 1;
 638
 639     dri_bo_get_tiling(region, &tiling, &swizzle);
 640     i965_render_set_surface_tiling(ss, tiling);
 641
 642     dri_bo_emit_reloc(ss_bo,
 643                       I915_GEM_DOMAIN_SAMPLER, 0,
 644                       offset,
 645                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 646                       region);
 647
 648     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 649     dri_bo_unmap(ss_bo);
 650     render_state->wm.sampler_count++;
 651 }
 652
 653 static void
 654 i965_render_src_surfaces_state(VADriverContextP ctx,
 655                               VASurfaceID surface)
 656 {
 657     struct i965_driver_data *i965 = i965_driver_data(ctx);
 658     struct i965_render_state *render_state = &i965->render_state;
 659     struct object_surface *obj_surface;
 660     int w, h;
 661     int rw, rh;
 662     dri_bo *region;
 663
 664     obj_surface = SURFACE(surface);
 665     assert(obj_surface);
 666
 667     if (obj_surface->pp_out_bo) {
 668         w = obj_surface->pp_out_width;
 669         h = obj_surface->pp_out_height;
 670         rw = obj_surface->orig_pp_out_width;
 671         rh = obj_surface->orig_pp_out_height;
 672         region = obj_surface->pp_out_bo;
 673     } else {
 674         w = obj_surface->width;
 675         h = obj_surface->height;
 676         rw = obj_surface->orig_width;
 677         rh = obj_surface->orig_height;
 678         region = obj_surface->bo;
 679     }
 680
 681     i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, w, I965_SURFACEFORMAT_R8_UNORM);     /* Y */
 682     i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, w, I965_SURFACEFORMAT_R8_UNORM);
 683
 684     if (render_state->interleaved_uv) {
 685         i965_render_src_surface_state(ctx, 3, region, w * h, rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8G8_UNORM); /* UV */
 686         i965_render_src_surface_state(ctx, 4, region, w * h, rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8G8_UNORM);
 687     } else {
 688         int u3 = 3, u4 = 4, v5 = 5, v6 = 6;
 689
 690         if (obj_surface->flags & SURFACE_DERIVED) {
 691             u3 = 5, u4 = 6, v5 = 3, v6 = 4;
 692         }
 693
 694         i965_render_src_surface_state(ctx, u3, region, w * h, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM); /* U */
 695         i965_render_src_surface_state(ctx, u4, region, w * h, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);
 696         i965_render_src_surface_state(ctx, v5, region, w * h + w * h / 4, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);     /* V */
 697         i965_render_src_surface_state(ctx, v6, region, w * h + w * h / 4, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);
 698     }
 699 }
 700
 701 static void
 702 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
 703                               VASurfaceID surface)
 704 {
 705     struct i965_driver_data *i965 = i965_driver_data(ctx);
 706     struct object_surface *obj_surface = SURFACE(surface);
 707     int w, h;
 708     dri_bo *region;
 709     dri_bo *subpic_region;
 710     struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
 711     struct object_image *obj_image = IMAGE(obj_subpic->image);
 712     assert(obj_surface);
 713     assert(obj_surface->bo);
 714     w = obj_surface->width;
 715     h = obj_surface->height;
 716     region = obj_surface->bo;
 717     subpic_region = obj_image->bo;
 718     /*subpicture surface*/
 719     i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format);
 720     i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format);
 721 }
 722
 723 static void
 724 i965_render_dest_surface_state(VADriverContextP ctx, int index)
 725 {
 726     struct i965_driver_data *i965 = i965_driver_data(ctx);
 727     struct i965_render_state *render_state = &i965->render_state;
 728     struct intel_region *dest_region = render_state->draw_region;
 729     struct i965_surface_state *ss;
 730     dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
 731
 732     assert(index < MAX_RENDER_SURFACES);
 733
 734     dri_bo_map(ss_bo, 1);
 735     assert(ss_bo->virtual);
 736     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 737     memset(ss, 0, sizeof(*ss));
 738
 739     ss->ss0.surface_type = I965_SURFACE_2D;
 740     ss->ss0.data_return_format = I965_SURFACERETURNFORMAT_FLOAT32;
 741
 742     if (dest_region->cpp == 2) {
 743         ss->ss0.surface_format = I965_SURFACEFORMAT_B5G6R5_UNORM;
 744         } else {
 745         ss->ss0.surface_format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
 746     }
 747
 748     ss->ss0.writedisable_alpha = 0;
 749     ss->ss0.writedisable_red = 0;
 750     ss->ss0.writedisable_green = 0;
 751     ss->ss0.writedisable_blue = 0;
 752     ss->ss0.color_blend = 1;
 753     ss->ss0.vert_line_stride = 0;
 754     ss->ss0.vert_line_stride_ofs = 0;
 755     ss->ss0.mipmap_layout_mode = 0;
 756     ss->ss0.render_cache_read_mode = 0;
 757
 758     ss->ss1.base_addr = dest_region->bo->offset;
 759
 760     ss->ss2.width = dest_region->width - 1;
 761     ss->ss2.height = dest_region->height - 1;
 762     ss->ss2.mip_count = 0;
 763     ss->ss2.render_target_rotation = 0;
 764     ss->ss3.pitch = dest_region->pitch - 1;
 765     i965_render_set_surface_tiling(ss, dest_region->tiling);
 766
 767     dri_bo_emit_reloc(ss_bo,
 768                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 769                       0,
 770                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 771                       dest_region->bo);
 772
 773     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 774     dri_bo_unmap(ss_bo);
 775 }
 776
 777 static void
 778 i965_subpic_render_upload_vertex(VADriverContextP ctx,
 779                                  VASurfaceID surface,
 780                                  const VARectangle *output_rect)
 781 {
 782     struct i965_driver_data  *i965         = i965_driver_data(ctx);
 783     struct i965_render_state *render_state = &i965->render_state;
 784     struct object_surface    *obj_surface  = SURFACE(surface);
 785     struct object_subpic     *obj_subpic   = SUBPIC(obj_surface->subpic);
 786
 787     const float sx = (float)output_rect->width  / (float)obj_surface->orig_width;
 788     const float sy = (float)output_rect->height / (float)obj_surface->orig_height;
 789     float *vb, tx1, tx2, ty1, ty2, x1, x2, y1, y2;
 790     int i = 0;
 791
 792     VARectangle dst_rect;
 793     dst_rect.x      = output_rect->x + sx * (float)obj_subpic->dst_rect.x;
 794     dst_rect.y      = output_rect->y + sx * (float)obj_subpic->dst_rect.y;
 795     dst_rect.width  = sx * (float)obj_subpic->dst_rect.width;
 796     dst_rect.height = sy * (float)obj_subpic->dst_rect.height;
 797
 798     dri_bo_map(render_state->vb.vertex_buffer, 1);
 799     assert(render_state->vb.vertex_buffer->virtual);
 800     vb = render_state->vb.vertex_buffer->virtual;
 801
 802     tx1 = (float)obj_subpic->src_rect.x / (float)obj_subpic->width;
 803     ty1 = (float)obj_subpic->src_rect.y / (float)obj_subpic->height;
 804     tx2 = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / (float)obj_subpic->width;
 805     ty2 = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / (float)obj_subpic->height;
 806
 807     x1 = (float)dst_rect.x;
 808     y1 = (float)dst_rect.y;
 809     x2 = (float)(dst_rect.x + dst_rect.width);
 810     y2 = (float)(dst_rect.y + dst_rect.height);
 811
 812     vb[i++] = tx2;
 813     vb[i++] = ty2;
 814     vb[i++] = x2;
 815     vb[i++] = y2;
 816
 817     vb[i++] = tx1;
 818     vb[i++] = ty2;
 819     vb[i++] = x1;
 820     vb[i++] = y2;
 821
 822     vb[i++] = tx1;
 823     vb[i++] = ty1;
 824     vb[i++] = x1;
 825     vb[i++] = y1;
 826     dri_bo_unmap(render_state->vb.vertex_buffer);
 827 }
 828
 829 static void
 830 i965_render_upload_vertex(VADriverContextP ctx,
 831                           VASurfaceID surface,
 832                           short srcx,
 833                           short srcy,
 834                           unsigned short srcw,
 835                           unsigned short srch,
 836                           short destx,
 837                           short desty,
 838                           unsigned short destw,
 839                           unsigned short desth)
 840 {
 841     struct i965_driver_data *i965 = i965_driver_data(ctx);
 842     struct i965_render_state *render_state = &i965->render_state;
 843     struct intel_region *dest_region = render_state->draw_region;
 844     struct object_surface *obj_surface;
 845     float *vb;
 846
 847     float u1, v1, u2, v2;
 848     int i, width, height;
 849     int box_x1 = dest_region->x + destx;
 850     int box_y1 = dest_region->y + desty;
 851     int box_x2 = box_x1 + destw;
 852     int box_y2 = box_y1 + desth;
 853
 854     obj_surface = SURFACE(surface);
 855     assert(surface);
 856     width = obj_surface->orig_width;
 857     height = obj_surface->orig_height;
 858
 859     u1 = (float)srcx / width;
 860     v1 = (float)srcy / height;
 861     u2 = (float)(srcx + srcw) / width;
 862     v2 = (float)(srcy + srch) / height;
 863
 864     dri_bo_map(render_state->vb.vertex_buffer, 1);
 865     assert(render_state->vb.vertex_buffer->virtual);
 866     vb = render_state->vb.vertex_buffer->virtual;
 867
 868     i = 0;
 869     vb[i++] = u2;
 870     vb[i++] = v2;
 871     vb[i++] = (float)box_x2;
 872     vb[i++] = (float)box_y2;
 873
 874     vb[i++] = u1;
 875     vb[i++] = v2;
 876     vb[i++] = (float)box_x1;
 877     vb[i++] = (float)box_y2;
 878
 879     vb[i++] = u1;
 880     vb[i++] = v1;
 881     vb[i++] = (float)box_x1;
 882     vb[i++] = (float)box_y1;
 883
 884     dri_bo_unmap(render_state->vb.vertex_buffer);
 885 }
 886
 887 static void
 888 i965_render_upload_constants(VADriverContextP ctx)
 889 {
 890     struct i965_driver_data *i965 = i965_driver_data(ctx);
 891     struct i965_render_state *render_state = &i965->render_state;
 892     unsigned short *constant_buffer;
 893
 894     if (render_state->curbe.upload)
 895         return;
 896
 897     dri_bo_map(render_state->curbe.bo, 1);
 898     assert(render_state->curbe.bo->virtual);
 899     constant_buffer = render_state->curbe.bo->virtual;
 900
 901     if (render_state->interleaved_uv)
 902         *constant_buffer = 1;
 903     else
 904         *constant_buffer = 0;
 905
 906     dri_bo_unmap(render_state->curbe.bo);
 907     render_state->curbe.upload = 1;
 908 }
 909
 910 static void
 911 i965_surface_render_state_setup(VADriverContextP ctx,
 912                         VASurfaceID surface,
 913                         short srcx,
 914                         short srcy,
 915                         unsigned short srcw,
 916                         unsigned short srch,
 917                         short destx,
 918                         short desty,
 919                         unsigned short destw,
 920                         unsigned short desth)
 921 {
 922     i965_render_vs_unit(ctx);
 923     i965_render_sf_unit(ctx);
 924     i965_render_dest_surface_state(ctx, 0);
 925     i965_render_src_surfaces_state(ctx, surface);
 926     i965_render_sampler(ctx);
 927     i965_render_wm_unit(ctx);
 928     i965_render_cc_viewport(ctx);
 929     i965_render_cc_unit(ctx);
 930     i965_render_upload_vertex(ctx, surface,
 931                               srcx, srcy, srcw, srch,
 932                               destx, desty, destw, desth);
 933     i965_render_upload_constants(ctx);
 934 }
 935 static void
 936 i965_subpic_render_state_setup(VADriverContextP ctx,
 937                         VASurfaceID surface,
 938                         short srcx,
 939                         short srcy,
 940                         unsigned short srcw,
 941                         unsigned short srch,
 942                         short destx,
 943                         short desty,
 944                         unsigned short destw,
 945                         unsigned short desth)
 946 {
 947     i965_render_vs_unit(ctx);
 948     i965_render_sf_unit(ctx);
 949     i965_render_dest_surface_state(ctx, 0);
 950     i965_subpic_render_src_surfaces_state(ctx, surface);
 951     i965_render_sampler(ctx);
 952     i965_subpic_render_wm_unit(ctx);
 953     i965_render_cc_viewport(ctx);
 954     i965_subpic_render_cc_unit(ctx);
 955
 956     VARectangle output_rect;
 957     output_rect.x      = destx;
 958     output_rect.y      = desty;
 959     output_rect.width  = destw;
 960     output_rect.height = desth;
 961     i965_subpic_render_upload_vertex(ctx, surface, &output_rect);
 962 }
 963
 964
 965 static void
 966 i965_render_pipeline_select(VADriverContextP ctx)
 967 {
 968     BEGIN_BATCH(ctx, 1);
 969     OUT_BATCH(ctx, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 970     ADVANCE_BATCH(ctx);
 971 }
 972
 973 static void
 974 i965_render_state_sip(VADriverContextP ctx)
 975 {
 976     BEGIN_BATCH(ctx, 2);
 977     OUT_BATCH(ctx, CMD_STATE_SIP | 0);
 978     OUT_BATCH(ctx, 0);
 979     ADVANCE_BATCH(ctx);
 980 }
 981
 982 static void
 983 i965_render_state_base_address(VADriverContextP ctx)
 984 {
 985     struct i965_driver_data *i965 = i965_driver_data(ctx);
 986     struct i965_render_state *render_state = &i965->render_state;
 987
 988     if (IS_IRONLAKE(i965->intel.device_id)) {
 989         BEGIN_BATCH(ctx, 8);
 990         OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 6);
 991         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 992         OUT_RELOC(ctx, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 993         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 994         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 995         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 996         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 997         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 998         ADVANCE_BATCH(ctx);
 999     } else {
1000         BEGIN_BATCH(ctx, 6);
1001         OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 4);
1002         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
1003         OUT_RELOC(ctx, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1004         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
1005         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
1006         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
1007         ADVANCE_BATCH(ctx);
1008     }
1009 }
1010
1011 static void
1012 i965_render_binding_table_pointers(VADriverContextP ctx)
1013 {
1014     BEGIN_BATCH(ctx, 6);
1015     OUT_BATCH(ctx, CMD_BINDING_TABLE_POINTERS | 4);
1016     OUT_BATCH(ctx, 0); /* vs */
1017     OUT_BATCH(ctx, 0); /* gs */
1018     OUT_BATCH(ctx, 0); /* clip */
1019     OUT_BATCH(ctx, 0); /* sf */
1020     OUT_BATCH(ctx, BINDING_TABLE_OFFSET);
1021     ADVANCE_BATCH(ctx);
1022 }
1023
1024 static void
1025 i965_render_constant_color(VADriverContextP ctx)
1026 {
1027     BEGIN_BATCH(ctx, 5);
1028     OUT_BATCH(ctx, CMD_CONSTANT_COLOR | 3);
1029     OUT_BATCH(ctx, float_to_uint(1.0));
1030     OUT_BATCH(ctx, float_to_uint(0.0));
1031     OUT_BATCH(ctx, float_to_uint(1.0));
1032     OUT_BATCH(ctx, float_to_uint(1.0));
1033     ADVANCE_BATCH(ctx);
1034 }
1035
1036 static void
1037 i965_render_pipelined_pointers(VADriverContextP ctx)
1038 {
1039     struct i965_driver_data *i965 = i965_driver_data(ctx);
1040     struct i965_render_state *render_state = &i965->render_state;
1041
1042     BEGIN_BATCH(ctx, 7);
1043     OUT_BATCH(ctx, CMD_PIPELINED_POINTERS | 5);
1044     OUT_RELOC(ctx, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1045     OUT_BATCH(ctx, 0);  /* disable GS */
1046     OUT_BATCH(ctx, 0);  /* disable CLIP */
1047     OUT_RELOC(ctx, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1048     OUT_RELOC(ctx, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1049     OUT_RELOC(ctx, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1050     ADVANCE_BATCH(ctx);
1051 }
1052
1053 static void
1054 i965_render_urb_layout(VADriverContextP ctx)
1055 {
1056     int urb_vs_start, urb_vs_size;
1057     int urb_gs_start, urb_gs_size;
1058     int urb_clip_start, urb_clip_size;
1059     int urb_sf_start, urb_sf_size;
1060     int urb_cs_start, urb_cs_size;
1061
1062     urb_vs_start = 0;
1063     urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1064     urb_gs_start = urb_vs_start + urb_vs_size;
1065     urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1066     urb_clip_start = urb_gs_start + urb_gs_size;
1067     urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1068     urb_sf_start = urb_clip_start + urb_clip_size;
1069     urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1070     urb_cs_start = urb_sf_start + urb_sf_size;
1071     urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1072
1073     BEGIN_BATCH(ctx, 3);
1074     OUT_BATCH(ctx,
1075               CMD_URB_FENCE |
1076               UF0_CS_REALLOC |
1077               UF0_SF_REALLOC |
1078               UF0_CLIP_REALLOC |
1079               UF0_GS_REALLOC |
1080               UF0_VS_REALLOC |
1081               1);
1082     OUT_BATCH(ctx,
1083               ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1084               ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1085               ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1086     OUT_BATCH(ctx,
1087               ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1088               ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1089     ADVANCE_BATCH(ctx);
1090 }
1091
1092 static void
1093 i965_render_cs_urb_layout(VADriverContextP ctx)
1094 {
1095     BEGIN_BATCH(ctx, 2);
1096     OUT_BATCH(ctx, CMD_CS_URB_STATE | 0);
1097     OUT_BATCH(ctx,
1098               ((URB_CS_ENTRY_SIZE - 1) << 4) |          /* URB Entry Allocation Size */
1099               (URB_CS_ENTRIES << 0));                /* Number of URB Entries */
1100     ADVANCE_BATCH(ctx);
1101 }
1102
1103 static void
1104 i965_render_constant_buffer(VADriverContextP ctx)
1105 {
1106     struct i965_driver_data *i965 = i965_driver_data(ctx);
1107     struct i965_render_state *render_state = &i965->render_state;
1108
1109     BEGIN_BATCH(ctx, 2);
1110     OUT_BATCH(ctx, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1111     OUT_RELOC(ctx, render_state->curbe.bo,
1112               I915_GEM_DOMAIN_INSTRUCTION, 0,
1113               URB_CS_ENTRY_SIZE - 1);
1114     ADVANCE_BATCH(ctx);
1115 }
1116
1117 static void
1118 i965_render_drawing_rectangle(VADriverContextP ctx)
1119 {
1120     struct i965_driver_data *i965 = i965_driver_data(ctx);
1121     struct i965_render_state *render_state = &i965->render_state;
1122     struct intel_region *dest_region = render_state->draw_region;
1123
1124     BEGIN_BATCH(ctx, 4);
1125     OUT_BATCH(ctx, CMD_DRAWING_RECTANGLE | 2);
1126     OUT_BATCH(ctx, 0x00000000);
1127     OUT_BATCH(ctx, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1128     OUT_BATCH(ctx, 0x00000000);
1129     ADVANCE_BATCH(ctx);
1130 }
1131
1132 static void
1133 i965_render_vertex_elements(VADriverContextP ctx)
1134 {
1135     struct i965_driver_data *i965 = i965_driver_data(ctx);
1136
1137     if (IS_IRONLAKE(i965->intel.device_id)) {
1138         BEGIN_BATCH(ctx, 5);
1139         OUT_BATCH(ctx, CMD_VERTEX_ELEMENTS | 3);
1140         /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1141         OUT_BATCH(ctx, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1142                   VE0_VALID |
1143                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1144                   (0 << VE0_OFFSET_SHIFT));
1145         OUT_BATCH(ctx, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1146                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1147                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1148                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1149         /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1150         OUT_BATCH(ctx, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1151                   VE0_VALID |
1152                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1153                   (8 << VE0_OFFSET_SHIFT));
1154         OUT_BATCH(ctx, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1155                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1156                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1157                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1158         ADVANCE_BATCH(ctx);
1159     } else {
1160         BEGIN_BATCH(ctx, 5);
1161         OUT_BATCH(ctx, CMD_VERTEX_ELEMENTS | 3);
1162         /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1163         OUT_BATCH(ctx, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1164                   VE0_VALID |
1165                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1166                   (0 << VE0_OFFSET_SHIFT));
1167         OUT_BATCH(ctx, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1168                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1169                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1170                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1171                   (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1172         /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1173         OUT_BATCH(ctx, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1174                   VE0_VALID |
1175                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1176                   (8 << VE0_OFFSET_SHIFT));
1177         OUT_BATCH(ctx, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1178                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1179                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1180                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1181                   (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1182         ADVANCE_BATCH(ctx);
1183     }
1184 }
1185
1186 static void
1187 i965_render_upload_image_palette(
1188     VADriverContextP ctx,
1189     VAImageID        image_id,
1190     unsigned int     alpha
1191 )
1192 {
1193     struct i965_driver_data *i965 = i965_driver_data(ctx);
1194     unsigned int i;
1195
1196     struct object_image *obj_image = IMAGE(image_id);
1197     assert(obj_image);
1198
1199     if (obj_image->image.num_palette_entries == 0)
1200         return;
1201
1202     BEGIN_BATCH(ctx, 1 + obj_image->image.num_palette_entries);
1203     OUT_BATCH(ctx, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1204     /*fill palette*/
1205     //int32_t out[16]; //0-23:color 23-31:alpha
1206     for (i = 0; i < obj_image->image.num_palette_entries; i++)
1207         OUT_BATCH(ctx, (alpha << 24) | obj_image->palette[i]);
1208     ADVANCE_BATCH(ctx);
1209 }
1210
1211 static void
1212 i965_render_startup(VADriverContextP ctx)
1213 {
1214     struct i965_driver_data *i965 = i965_driver_data(ctx);
1215     struct i965_render_state *render_state = &i965->render_state;
1216
1217     BEGIN_BATCH(ctx, 11);
1218     OUT_BATCH(ctx, CMD_VERTEX_BUFFERS | 3);
1219     OUT_BATCH(ctx,
1220               (0 << VB0_BUFFER_INDEX_SHIFT) |
1221               VB0_VERTEXDATA |
1222               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1223     OUT_RELOC(ctx, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1224
1225     if (IS_IRONLAKE(i965->intel.device_id))
1226         OUT_RELOC(ctx, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1227     else
1228         OUT_BATCH(ctx, 3);
1229
1230     OUT_BATCH(ctx, 0);
1231
1232     OUT_BATCH(ctx,
1233               CMD_3DPRIMITIVE |
1234               _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1235               (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1236               (0 << 9) |
1237               4);
1238     OUT_BATCH(ctx, 3); /* vertex count per instance */
1239     OUT_BATCH(ctx, 0); /* start vertex offset */
1240     OUT_BATCH(ctx, 1); /* single instance */
1241     OUT_BATCH(ctx, 0); /* start instance location */
1242     OUT_BATCH(ctx, 0); /* index buffer offset, ignored */
1243     ADVANCE_BATCH(ctx);
1244 }
1245
1246 static void
1247 i965_clear_dest_region(VADriverContextP ctx)
1248 {
1249     struct i965_driver_data *i965 = i965_driver_data(ctx);
1250     struct i965_render_state *render_state = &i965->render_state;
1251     struct intel_region *dest_region = render_state->draw_region;
1252     unsigned int blt_cmd, br13;
1253     int pitch;
1254
1255     blt_cmd = XY_COLOR_BLT_CMD;
1256     br13 = 0xf0 << 16;
1257     pitch = dest_region->pitch;
1258
1259     if (dest_region->cpp == 4) {
1260         br13 |= BR13_8888;
1261         blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1262     } else {
1263         assert(dest_region->cpp == 2);
1264         br13 |= BR13_565;
1265     }
1266
1267     if (dest_region->tiling != I915_TILING_NONE) {
1268         blt_cmd |= XY_COLOR_BLT_DST_TILED;
1269         pitch /= 4;
1270     }
1271
1272     br13 |= pitch;
1273
1274     if (IS_GEN6(i965->intel.device_id))
1275         BEGIN_BLT_BATCH(ctx, 6);
1276     else
1277         BEGIN_BATCH(ctx, 6);
1278     OUT_BATCH(ctx, blt_cmd);
1279     OUT_BATCH(ctx, br13);
1280     OUT_BATCH(ctx, (dest_region->y << 16) | (dest_region->x));
1281     OUT_BATCH(ctx, ((dest_region->y + dest_region->height) << 16) |
1282               (dest_region->x + dest_region->width));
1283     OUT_RELOC(ctx, dest_region->bo,
1284               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1285               0);
1286     OUT_BATCH(ctx, 0x0);
1287     ADVANCE_BATCH(ctx);
1288 }
1289
1290 static void
1291 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1292 {
1293     i965_clear_dest_region(ctx);
1294     intel_batchbuffer_start_atomic(ctx, 0x1000);
1295     intel_batchbuffer_emit_mi_flush(ctx);
1296     i965_render_pipeline_select(ctx);
1297     i965_render_state_sip(ctx);
1298     i965_render_state_base_address(ctx);
1299     i965_render_binding_table_pointers(ctx);
1300     i965_render_constant_color(ctx);
1301     i965_render_pipelined_pointers(ctx);
1302     i965_render_urb_layout(ctx);
1303     i965_render_cs_urb_layout(ctx);
1304     i965_render_constant_buffer(ctx);
1305     i965_render_drawing_rectangle(ctx);
1306     i965_render_vertex_elements(ctx);
1307     i965_render_startup(ctx);
1308     intel_batchbuffer_end_atomic(ctx);
1309 }
1310
1311 static void
1312 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1313 {
1314     intel_batchbuffer_start_atomic(ctx, 0x1000);
1315     intel_batchbuffer_emit_mi_flush(ctx);
1316     i965_render_pipeline_select(ctx);
1317     i965_render_state_sip(ctx);
1318     i965_render_state_base_address(ctx);
1319     i965_render_binding_table_pointers(ctx);
1320     i965_render_constant_color(ctx);
1321     i965_render_pipelined_pointers(ctx);
1322     i965_render_urb_layout(ctx);
1323     i965_render_cs_urb_layout(ctx);
1324     i965_render_drawing_rectangle(ctx);
1325     i965_render_vertex_elements(ctx);
1326     i965_render_startup(ctx);
1327     intel_batchbuffer_end_atomic(ctx);
1328 }
1329
1330
1331 static void
1332 i965_render_initialize(VADriverContextP ctx)
1333 {
1334     struct i965_driver_data *i965 = i965_driver_data(ctx);
1335     struct i965_render_state *render_state = &i965->render_state;
1336     dri_bo *bo;
1337
1338     /* VERTEX BUFFER */
1339     dri_bo_unreference(render_state->vb.vertex_buffer);
1340     bo = dri_bo_alloc(i965->intel.bufmgr,
1341                       "vertex buffer",
1342                       4096,
1343                       4096);
1344     assert(bo);
1345     render_state->vb.vertex_buffer = bo;
1346
1347     /* VS */
1348     dri_bo_unreference(render_state->vs.state);
1349     bo = dri_bo_alloc(i965->intel.bufmgr,
1350                       "vs state",
1351                       sizeof(struct i965_vs_unit_state),
1352                       64);
1353     assert(bo);
1354     render_state->vs.state = bo;
1355
1356     /* GS */
1357     /* CLIP */
1358     /* SF */
1359     dri_bo_unreference(render_state->sf.state);
1360     bo = dri_bo_alloc(i965->intel.bufmgr,
1361                       "sf state",
1362                       sizeof(struct i965_sf_unit_state),
1363                       64);
1364     assert(bo);
1365     render_state->sf.state = bo;
1366
1367     /* WM */
1368     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1369     bo = dri_bo_alloc(i965->intel.bufmgr,
1370                       "surface state & binding table",
1371                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1372                       4096);
1373     assert(bo);
1374     render_state->wm.surface_state_binding_table_bo = bo;
1375
1376     dri_bo_unreference(render_state->wm.sampler);
1377     bo = dri_bo_alloc(i965->intel.bufmgr,
1378                       "sampler state",
1379                       MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1380                       64);
1381     assert(bo);
1382     render_state->wm.sampler = bo;
1383     render_state->wm.sampler_count = 0;
1384
1385     dri_bo_unreference(render_state->wm.state);
1386     bo = dri_bo_alloc(i965->intel.bufmgr,
1387                       "wm state",
1388                       sizeof(struct i965_wm_unit_state),
1389                       64);
1390     assert(bo);
1391     render_state->wm.state = bo;
1392
1393     /* COLOR CALCULATOR */
1394     dri_bo_unreference(render_state->cc.state);
1395     bo = dri_bo_alloc(i965->intel.bufmgr,
1396                       "color calc state",
1397                       sizeof(struct i965_cc_unit_state),
1398                       64);
1399     assert(bo);
1400     render_state->cc.state = bo;
1401
1402     dri_bo_unreference(render_state->cc.viewport);
1403     bo = dri_bo_alloc(i965->intel.bufmgr,
1404                       "cc viewport",
1405                       sizeof(struct i965_cc_viewport),
1406                       64);
1407     assert(bo);
1408     render_state->cc.viewport = bo;
1409 }
1410
1411 static void
1412 i965_render_put_surface(VADriverContextP ctx,
1413                         VASurfaceID surface,
1414                         short srcx,
1415                         short srcy,
1416                         unsigned short srcw,
1417                         unsigned short srch,
1418                         short destx,
1419                         short desty,
1420                         unsigned short destw,
1421                         unsigned short desth,
1422                         unsigned int flag)
1423 {
1424     i965_post_processing(ctx, surface,
1425                          srcx, srcy, srcw, srch,
1426                          destx, desty, destw, desth,
1427                          flag);
1428
1429     i965_render_initialize(ctx);
1430     i965_surface_render_state_setup(ctx, surface,
1431                             srcx, srcy, srcw, srch,
1432                             destx, desty, destw, desth);
1433     i965_surface_render_pipeline_setup(ctx);
1434     intel_batchbuffer_flush(ctx);
1435 }
1436
1437 static void
1438 i965_render_put_subpicture(VADriverContextP ctx,
1439                            VASurfaceID surface,
1440                            short srcx,
1441                            short srcy,
1442                            unsigned short srcw,
1443                            unsigned short srch,
1444                            short destx,
1445                            short desty,
1446                            unsigned short destw,
1447                            unsigned short desth)
1448 {
1449     struct i965_driver_data *i965 = i965_driver_data(ctx);
1450     struct object_surface *obj_surface = SURFACE(surface);
1451     struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
1452     assert(obj_subpic);
1453
1454     i965_render_initialize(ctx);
1455     i965_subpic_render_state_setup(ctx, surface,
1456                                    srcx, srcy, srcw, srch,
1457                                    destx, desty, destw, desth);
1458     i965_subpic_render_pipeline_setup(ctx);
1459     i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
1460     intel_batchbuffer_flush(ctx);
1461 }
1462
1463 /*
1464  * for GEN6+
1465  */
1466 static void
1467 gen6_render_initialize(VADriverContextP ctx)
1468 {
1469     struct i965_driver_data *i965 = i965_driver_data(ctx);
1470     struct i965_render_state *render_state = &i965->render_state;
1471     dri_bo *bo;
1472
1473     /* VERTEX BUFFER */
1474     dri_bo_unreference(render_state->vb.vertex_buffer);
1475     bo = dri_bo_alloc(i965->intel.bufmgr,
1476                       "vertex buffer",
1477                       4096,
1478                       4096);
1479     assert(bo);
1480     render_state->vb.vertex_buffer = bo;
1481
1482     /* WM */
1483     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1484     bo = dri_bo_alloc(i965->intel.bufmgr,
1485                       "surface state & binding table",
1486                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1487                       4096);
1488     assert(bo);
1489     render_state->wm.surface_state_binding_table_bo = bo;
1490
1491     dri_bo_unreference(render_state->wm.sampler);
1492     bo = dri_bo_alloc(i965->intel.bufmgr,
1493                       "sampler state",
1494                       MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1495                       4096);
1496     assert(bo);
1497     render_state->wm.sampler = bo;
1498     render_state->wm.sampler_count = 0;
1499
1500     /* COLOR CALCULATOR */
1501     dri_bo_unreference(render_state->cc.state);
1502     bo = dri_bo_alloc(i965->intel.bufmgr,
1503                       "color calc state",
1504                       sizeof(struct gen6_color_calc_state),
1505                       4096);
1506     assert(bo);
1507     render_state->cc.state = bo;
1508
1509     /* CC VIEWPORT */
1510     dri_bo_unreference(render_state->cc.viewport);
1511     bo = dri_bo_alloc(i965->intel.bufmgr,
1512                       "cc viewport",
1513                       sizeof(struct i965_cc_viewport),
1514                       4096);
1515     assert(bo);
1516     render_state->cc.viewport = bo;
1517
1518     /* BLEND STATE */
1519     dri_bo_unreference(render_state->cc.blend);
1520     bo = dri_bo_alloc(i965->intel.bufmgr,
1521                       "blend state",
1522                       sizeof(struct gen6_blend_state),
1523                       4096);
1524     assert(bo);
1525     render_state->cc.blend = bo;
1526
1527     /* DEPTH & STENCIL STATE */
1528     dri_bo_unreference(render_state->cc.depth_stencil);
1529     bo = dri_bo_alloc(i965->intel.bufmgr,
1530                       "depth & stencil state",
1531                       sizeof(struct gen6_depth_stencil_state),
1532                       4096);
1533     assert(bo);
1534     render_state->cc.depth_stencil = bo;
1535 }
1536
1537 static void
1538 gen6_render_color_calc_state(VADriverContextP ctx)
1539 {
1540     struct i965_driver_data *i965 = i965_driver_data(ctx);
1541     struct i965_render_state *render_state = &i965->render_state;
1542     struct gen6_color_calc_state *color_calc_state;
1543
1544     dri_bo_map(render_state->cc.state, 1);
1545     assert(render_state->cc.state->virtual);
1546     color_calc_state = render_state->cc.state->virtual;
1547     memset(color_calc_state, 0, sizeof(*color_calc_state));
1548     color_calc_state->constant_r = 1.0;
1549     color_calc_state->constant_g = 0.0;
1550     color_calc_state->constant_b = 1.0;
1551     color_calc_state->constant_a = 1.0;
1552     dri_bo_unmap(render_state->cc.state);
1553 }
1554
1555 static void
1556 gen6_render_blend_state(VADriverContextP ctx)
1557 {
1558     struct i965_driver_data *i965 = i965_driver_data(ctx);
1559     struct i965_render_state *render_state = &i965->render_state;
1560     struct gen6_blend_state *blend_state;
1561
1562     dri_bo_map(render_state->cc.blend, 1);
1563     assert(render_state->cc.blend->virtual);
1564     blend_state = render_state->cc.blend->virtual;
1565     memset(blend_state, 0, sizeof(*blend_state));
1566     blend_state->blend1.logic_op_enable = 1;
1567     blend_state->blend1.logic_op_func = 0xc;
1568     dri_bo_unmap(render_state->cc.blend);
1569 }
1570
1571 static void
1572 gen6_render_depth_stencil_state(VADriverContextP ctx)
1573 {
1574     struct i965_driver_data *i965 = i965_driver_data(ctx);
1575     struct i965_render_state *render_state = &i965->render_state;
1576     struct gen6_depth_stencil_state *depth_stencil_state;
1577
1578     dri_bo_map(render_state->cc.depth_stencil, 1);
1579     assert(render_state->cc.depth_stencil->virtual);
1580     depth_stencil_state = render_state->cc.depth_stencil->virtual;
1581     memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
1582     dri_bo_unmap(render_state->cc.depth_stencil);
1583 }
1584
1585 static void
1586 gen6_render_setup_states(VADriverContextP ctx,
1587                          VASurfaceID surface,
1588                          short srcx,
1589                          short srcy,
1590                          unsigned short srcw,
1591                          unsigned short srch,
1592                          short destx,
1593                          short desty,
1594                          unsigned short destw,
1595                          unsigned short desth)
1596 {
1597     i965_render_dest_surface_state(ctx, 0);
1598     i965_render_src_surfaces_state(ctx, surface);
1599     i965_render_sampler(ctx);
1600     i965_render_cc_viewport(ctx);
1601     gen6_render_color_calc_state(ctx);
1602     gen6_render_blend_state(ctx);
1603     gen6_render_depth_stencil_state(ctx);
1604     i965_render_upload_vertex(ctx, surface,
1605                               srcx, srcy, srcw, srch,
1606                               destx, desty, destw, desth);
1607 }
1608
1609 static void
1610 gen6_emit_invarient_states(VADriverContextP ctx)
1611 {
1612     OUT_BATCH(ctx, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1613
1614     OUT_BATCH(ctx, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1615     OUT_BATCH(ctx, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1616               GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1617     OUT_BATCH(ctx, 0);
1618
1619     OUT_BATCH(ctx, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1620     OUT_BATCH(ctx, 1);
1621
1622     /* Set system instruction pointer */
1623     OUT_BATCH(ctx, CMD_STATE_SIP | 0);
1624     OUT_BATCH(ctx, 0);
1625 }
1626
1627 static void
1628 gen6_emit_state_base_address(VADriverContextP ctx)
1629 {
1630     struct i965_driver_data *i965 = i965_driver_data(ctx);
1631     struct i965_render_state *render_state = &i965->render_state;
1632
1633     OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | (10 - 2));
1634     OUT_BATCH(ctx, BASE_ADDRESS_MODIFY); /* General state base address */
1635     OUT_RELOC(ctx, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1636     OUT_BATCH(ctx, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
1637     OUT_BATCH(ctx, BASE_ADDRESS_MODIFY); /* Indirect object base address */
1638     OUT_BATCH(ctx, BASE_ADDRESS_MODIFY); /* Instruction base address */
1639     OUT_BATCH(ctx, BASE_ADDRESS_MODIFY); /* General state upper bound */
1640     OUT_BATCH(ctx, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
1641     OUT_BATCH(ctx, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
1642     OUT_BATCH(ctx, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
1643 }
1644
1645 static void
1646 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
1647 {
1648     struct i965_driver_data *i965 = i965_driver_data(ctx);
1649     struct i965_render_state *render_state = &i965->render_state;
1650
1651     OUT_BATCH(ctx, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1652               GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1653               (4 - 2));
1654     OUT_BATCH(ctx, 0);
1655     OUT_BATCH(ctx, 0);
1656     OUT_RELOC(ctx, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1657 }
1658
1659 static void
1660 gen6_emit_urb(VADriverContextP ctx)
1661 {
1662     OUT_BATCH(ctx, GEN6_3DSTATE_URB | (3 - 2));
1663     OUT_BATCH(ctx, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1664               (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1665     OUT_BATCH(ctx, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1666               (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1667 }
1668
1669 static void
1670 gen6_emit_cc_state_pointers(VADriverContextP ctx)
1671 {
1672     struct i965_driver_data *i965 = i965_driver_data(ctx);
1673     struct i965_render_state *render_state = &i965->render_state;
1674
1675     OUT_BATCH(ctx, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1676     OUT_RELOC(ctx, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1677     OUT_RELOC(ctx, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1678     OUT_RELOC(ctx, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1679 }
1680
1681 static void
1682 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
1683 {
1684     struct i965_driver_data *i965 = i965_driver_data(ctx);
1685     struct i965_render_state *render_state = &i965->render_state;
1686
1687     OUT_BATCH(ctx, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1688               GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1689               (4 - 2));
1690     OUT_BATCH(ctx, 0); /* VS */
1691     OUT_BATCH(ctx, 0); /* GS */
1692     OUT_RELOC(ctx,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1693 }
1694
1695 static void
1696 gen6_emit_binding_table(VADriverContextP ctx)
1697 {
1698     /* Binding table pointers */
1699     OUT_BATCH(ctx, CMD_BINDING_TABLE_POINTERS |
1700               GEN6_BINDING_TABLE_MODIFY_PS |
1701               (4 - 2));
1702     OUT_BATCH(ctx, 0);          /* vs */
1703     OUT_BATCH(ctx, 0);          /* gs */
1704     /* Only the PS uses the binding table */
1705     OUT_BATCH(ctx, BINDING_TABLE_OFFSET);
1706 }
1707
1708 static void
1709 gen6_emit_depth_buffer_state(VADriverContextP ctx)
1710 {
1711     OUT_BATCH(ctx, CMD_DEPTH_BUFFER | (7 - 2));
1712     OUT_BATCH(ctx, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
1713               (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
1714     OUT_BATCH(ctx, 0);
1715     OUT_BATCH(ctx, 0);
1716     OUT_BATCH(ctx, 0);
1717     OUT_BATCH(ctx, 0);
1718     OUT_BATCH(ctx, 0);
1719
1720     OUT_BATCH(ctx, CMD_CLEAR_PARAMS | (2 - 2));
1721     OUT_BATCH(ctx, 0);
1722 }
1723
1724 static void
1725 gen6_emit_drawing_rectangle(VADriverContextP ctx)
1726 {
1727     i965_render_drawing_rectangle(ctx);
1728 }
1729
1730 static void
1731 gen6_emit_vs_state(VADriverContextP ctx)
1732 {
1733     /* disable VS constant buffer */
1734     OUT_BATCH(ctx, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
1735     OUT_BATCH(ctx, 0);
1736     OUT_BATCH(ctx, 0);
1737     OUT_BATCH(ctx, 0);
1738     OUT_BATCH(ctx, 0);
1739
1740     OUT_BATCH(ctx, GEN6_3DSTATE_VS | (6 - 2));
1741     OUT_BATCH(ctx, 0); /* without VS kernel */
1742     OUT_BATCH(ctx, 0);
1743     OUT_BATCH(ctx, 0);
1744     OUT_BATCH(ctx, 0);
1745     OUT_BATCH(ctx, 0); /* pass-through */
1746 }
1747
1748 static void
1749 gen6_emit_gs_state(VADriverContextP ctx)
1750 {
1751     /* disable GS constant buffer */
1752     OUT_BATCH(ctx, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
1753     OUT_BATCH(ctx, 0);
1754     OUT_BATCH(ctx, 0);
1755     OUT_BATCH(ctx, 0);
1756     OUT_BATCH(ctx, 0);
1757
1758     OUT_BATCH(ctx, GEN6_3DSTATE_GS | (7 - 2));
1759     OUT_BATCH(ctx, 0); /* without GS kernel */
1760     OUT_BATCH(ctx, 0);
1761     OUT_BATCH(ctx, 0);
1762     OUT_BATCH(ctx, 0);
1763     OUT_BATCH(ctx, 0);
1764     OUT_BATCH(ctx, 0); /* pass-through */
1765 }
1766
1767 static void
1768 gen6_emit_clip_state(VADriverContextP ctx)
1769 {
1770     OUT_BATCH(ctx, GEN6_3DSTATE_CLIP | (4 - 2));
1771     OUT_BATCH(ctx, 0);
1772     OUT_BATCH(ctx, 0); /* pass-through */
1773     OUT_BATCH(ctx, 0);
1774 }
1775
1776 static void
1777 gen6_emit_sf_state(VADriverContextP ctx)
1778 {
1779     OUT_BATCH(ctx, GEN6_3DSTATE_SF | (20 - 2));
1780     OUT_BATCH(ctx, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
1781               (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
1782               (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
1783     OUT_BATCH(ctx, 0);
1784     OUT_BATCH(ctx, GEN6_3DSTATE_SF_CULL_NONE);
1785     OUT_BATCH(ctx, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
1786     OUT_BATCH(ctx, 0);
1787     OUT_BATCH(ctx, 0);
1788     OUT_BATCH(ctx, 0);
1789     OUT_BATCH(ctx, 0);
1790     OUT_BATCH(ctx, 0); /* DW9 */
1791     OUT_BATCH(ctx, 0);
1792     OUT_BATCH(ctx, 0);
1793     OUT_BATCH(ctx, 0);
1794     OUT_BATCH(ctx, 0);
1795     OUT_BATCH(ctx, 0); /* DW14 */
1796     OUT_BATCH(ctx, 0);
1797     OUT_BATCH(ctx, 0);
1798     OUT_BATCH(ctx, 0);
1799     OUT_BATCH(ctx, 0);
1800     OUT_BATCH(ctx, 0); /* DW19 */
1801 }
1802
1803 static void
1804 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
1805 {
1806     /* disable WM constant buffer */
1807     OUT_BATCH(ctx, GEN6_3DSTATE_CONSTANT_PS | (5 - 2));
1808     OUT_BATCH(ctx, 0);
1809     OUT_BATCH(ctx, 0);
1810     OUT_BATCH(ctx, 0);
1811     OUT_BATCH(ctx, 0);
1812
1813     OUT_BATCH(ctx, GEN6_3DSTATE_WM | (9 - 2));
1814     OUT_RELOC(ctx, render_kernels[kernel].bo,
1815               I915_GEM_DOMAIN_INSTRUCTION, 0,
1816               0);
1817     OUT_BATCH(ctx, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
1818               (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
1819     OUT_BATCH(ctx, 0);
1820     OUT_BATCH(ctx, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
1821     OUT_BATCH(ctx, ((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
1822               GEN6_3DSTATE_WM_DISPATCH_ENABLE |
1823               GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
1824     OUT_BATCH(ctx, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
1825               GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
1826     OUT_BATCH(ctx, 0);
1827     OUT_BATCH(ctx, 0);
1828 }
1829
1830 static void
1831 gen6_emit_vertex_element_state(VADriverContextP ctx)
1832 {
1833     /* Set up our vertex elements, sourced from the single vertex buffer. */
1834     OUT_BATCH(ctx, CMD_VERTEX_ELEMENTS | (5 - 2));
1835     /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1836     OUT_BATCH(ctx, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1837               GEN6_VE0_VALID |
1838               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1839               (0 << VE0_OFFSET_SHIFT));
1840     OUT_BATCH(ctx, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1841               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1842               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1843               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1844     /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1845     OUT_BATCH(ctx, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1846               GEN6_VE0_VALID |
1847               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1848               (8 << VE0_OFFSET_SHIFT));
1849     OUT_BATCH(ctx, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1850               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1851               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1852               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1853 }
1854
1855 static void
1856 gen6_emit_vertices(VADriverContextP ctx)
1857 {
1858     struct i965_driver_data *i965 = i965_driver_data(ctx);
1859     struct i965_render_state *render_state = &i965->render_state;
1860
1861     BEGIN_BATCH(ctx, 11);
1862     OUT_BATCH(ctx, CMD_VERTEX_BUFFERS | 3);
1863     OUT_BATCH(ctx,
1864               (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
1865               GEN6_VB0_VERTEXDATA |
1866               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1867     OUT_RELOC(ctx, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1868     OUT_RELOC(ctx, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1869     OUT_BATCH(ctx, 0);
1870
1871     OUT_BATCH(ctx,
1872               CMD_3DPRIMITIVE |
1873               _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1874               (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1875               (0 << 9) |
1876               4);
1877     OUT_BATCH(ctx, 3); /* vertex count per instance */
1878     OUT_BATCH(ctx, 0); /* start vertex offset */
1879     OUT_BATCH(ctx, 1); /* single instance */
1880     OUT_BATCH(ctx, 0); /* start instance location */
1881     OUT_BATCH(ctx, 0); /* index buffer offset, ignored */
1882     ADVANCE_BATCH(ctx);
1883 }
1884
1885 static void
1886 gen6_render_emit_states(VADriverContextP ctx, int kernel)
1887 {
1888     intel_batchbuffer_start_atomic(ctx, 0x1000);
1889     intel_batchbuffer_emit_mi_flush(ctx);
1890     gen6_emit_invarient_states(ctx);
1891     gen6_emit_state_base_address(ctx);
1892     gen6_emit_viewport_state_pointers(ctx);
1893     gen6_emit_urb(ctx);
1894     gen6_emit_cc_state_pointers(ctx);
1895     gen6_emit_sampler_state_pointers(ctx);
1896     gen6_emit_vs_state(ctx);
1897     gen6_emit_gs_state(ctx);
1898     gen6_emit_clip_state(ctx);
1899     gen6_emit_sf_state(ctx);
1900     gen6_emit_wm_state(ctx, kernel);
1901     gen6_emit_binding_table(ctx);
1902     gen6_emit_depth_buffer_state(ctx);
1903     gen6_emit_drawing_rectangle(ctx);
1904     gen6_emit_vertex_element_state(ctx);
1905     gen6_emit_vertices(ctx);
1906     intel_batchbuffer_end_atomic(ctx);
1907 }
1908
1909 static void
1910 gen6_render_put_surface(VADriverContextP ctx,
1911                         VASurfaceID surface,
1912                         short srcx,
1913                         short srcy,
1914                         unsigned short srcw,
1915                         unsigned short srch,
1916                         short destx,
1917                         short desty,
1918                         unsigned short destw,
1919                         unsigned short desth,
1920                         unsigned int flag)
1921 {
1922     gen6_render_initialize(ctx);
1923     gen6_render_setup_states(ctx, surface,
1924                              srcx, srcy, srcw, srch,
1925                              destx, desty, destw, desth);
1926     i965_clear_dest_region(ctx);
1927     gen6_render_emit_states(ctx, PS_KERNEL);
1928     intel_batchbuffer_flush(ctx);
1929 }
1930
1931 static void
1932 gen6_subpicture_render_blend_state(VADriverContextP ctx)
1933 {
1934     struct i965_driver_data *i965 = i965_driver_data(ctx);
1935     struct i965_render_state *render_state = &i965->render_state;
1936     struct gen6_blend_state *blend_state;
1937
1938     dri_bo_unmap(render_state->cc.state);
1939     dri_bo_map(render_state->cc.blend, 1);
1940     assert(render_state->cc.blend->virtual);
1941     blend_state = render_state->cc.blend->virtual;
1942     memset(blend_state, 0, sizeof(*blend_state));
1943     blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
1944     blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
1945     blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
1946     blend_state->blend0.blend_enable = 1;
1947     blend_state->blend1.post_blend_clamp_enable = 1;
1948     blend_state->blend1.pre_blend_clamp_enable = 1;
1949     blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
1950     dri_bo_unmap(render_state->cc.blend);
1951 }
1952
1953 static void
1954 gen6_subpicture_render_setup_states(VADriverContextP ctx,
1955                                     VASurfaceID surface,
1956                                     short srcx,
1957                                     short srcy,
1958                                     unsigned short srcw,
1959                                     unsigned short srch,
1960                                     short destx,
1961                                     short desty,
1962                                     unsigned short destw,
1963                                     unsigned short desth)
1964 {
1965     VARectangle output_rect;
1966
1967     output_rect.x      = destx;
1968     output_rect.y      = desty;
1969     output_rect.width  = destw;
1970     output_rect.height = desth;
1971
1972     i965_render_dest_surface_state(ctx, 0);
1973     i965_subpic_render_src_surfaces_state(ctx, surface);
1974     i965_render_sampler(ctx);
1975     i965_render_cc_viewport(ctx);
1976     gen6_render_color_calc_state(ctx);
1977     gen6_subpicture_render_blend_state(ctx);
1978     gen6_render_depth_stencil_state(ctx);
1979     i965_subpic_render_upload_vertex(ctx, surface, &output_rect);
1980 }
1981
1982 static void
1983 gen6_render_put_subpicture(VADriverContextP ctx,
1984                            VASurfaceID surface,
1985                            short srcx,
1986                            short srcy,
1987                            unsigned short srcw,
1988                            unsigned short srch,
1989                            short destx,
1990                            short desty,
1991                            unsigned short destw,
1992                            unsigned short desth)
1993 {
1994     struct i965_driver_data *i965 = i965_driver_data(ctx);
1995     struct object_surface *obj_surface = SURFACE(surface);
1996     struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
1997
1998     assert(obj_subpic);
1999     gen6_render_initialize(ctx);
2000     gen6_subpicture_render_setup_states(ctx, surface,
2001                                         srcx, srcy, srcw, srch,
2002                                         destx, desty, destw, desth);
2003     gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2004     i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
2005     intel_batchbuffer_flush(ctx);
2006 }
2007
2008 /*
2009  * global functions
2010  */
2011 void
2012 intel_render_put_surface(VADriverContextP ctx,
2013                         VASurfaceID surface,
2014                         short srcx,
2015                         short srcy,
2016                         unsigned short srcw,
2017                         unsigned short srch,
2018                         short destx,
2019                         short desty,
2020                         unsigned short destw,
2021                         unsigned short desth,
2022                         unsigned int flag)
2023 {
2024     struct i965_driver_data *i965 = i965_driver_data(ctx);
2025
2026     if (IS_GEN6(i965->intel.device_id))
2027         gen6_render_put_surface(ctx, surface,
2028                                 srcx, srcy, srcw, srch,
2029                                 destx, desty, destw, desth,
2030                                 flag);
2031     else
2032         i965_render_put_surface(ctx, surface,
2033                                 srcx, srcy, srcw, srch,
2034                                 destx, desty, destw, desth,
2035                                 flag);
2036 }
2037
2038 void
2039 intel_render_put_subpicture(VADriverContextP ctx,
2040                            VASurfaceID surface,
2041                            short srcx,
2042                            short srcy,
2043                            unsigned short srcw,
2044                            unsigned short srch,
2045                            short destx,
2046                            short desty,
2047                            unsigned short destw,
2048                            unsigned short desth)
2049 {
2050     struct i965_driver_data *i965 = i965_driver_data(ctx);
2051
2052     if (IS_GEN6(i965->intel.device_id))
2053         gen6_render_put_subpicture(ctx, surface,
2054                                    srcx, srcy, srcw, srch,
2055                                    destx, desty, destw, desth);
2056     else
2057         i965_render_put_subpicture(ctx, surface,
2058                                    srcx, srcy, srcw, srch,
2059                                    destx, desty, destw, desth);
2060 }
2061
2062 Bool
2063 i965_render_init(VADriverContextP ctx)
2064 {
2065     struct i965_driver_data *i965 = i965_driver_data(ctx);
2066     struct i965_render_state *render_state = &i965->render_state;
2067     int i;
2068
2069     /* kernel */
2070     assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
2071                                  sizeof(render_kernels_gen5[0])));
2072     assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
2073                                  sizeof(render_kernels_gen6[0])));
2074
2075     if (IS_GEN6(i965->intel.device_id))
2076         render_kernels = render_kernels_gen6;
2077     else if (IS_IRONLAKE(i965->intel.device_id))
2078         render_kernels = render_kernels_gen5;
2079     else
2080         render_kernels = render_kernels_gen4;
2081
2082     for (i = 0; i < NUM_RENDER_KERNEL; i++) {
2083         struct render_kernel *kernel = &render_kernels[i];
2084
2085         if (!kernel->size)
2086             continue;
2087
2088         kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
2089                                   kernel->name,
2090                                   kernel->size, 0x1000);
2091         assert(kernel->bo);
2092         dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
2093     }
2094
2095     /* constant buffer */
2096     render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
2097                       "constant buffer",
2098                       4096, 64);
2099     assert(render_state->curbe.bo);
2100     render_state->curbe.upload = 0;
2101
2102     i965_post_processing_once_init(ctx);
2103
2104     return True;
2105 }
2106
2107 Bool
2108 i965_render_terminate(VADriverContextP ctx)
2109 {
2110     int i;
2111     struct i965_driver_data *i965 = i965_driver_data(ctx);
2112     struct i965_render_state *render_state = &i965->render_state;
2113
2114     i965_post_processing_terminate(ctx);
2115
2116     dri_bo_unreference(render_state->curbe.bo);
2117     render_state->curbe.bo = NULL;
2118
2119     for (i = 0; i < NUM_RENDER_KERNEL; i++) {
2120         struct render_kernel *kernel = &render_kernels[i];
2121
2122         dri_bo_unreference(kernel->bo);
2123         kernel->bo = NULL;
2124     }
2125
2126     dri_bo_unreference(render_state->vb.vertex_buffer);
2127     render_state->vb.vertex_buffer = NULL;
2128     dri_bo_unreference(render_state->vs.state);
2129     render_state->vs.state = NULL;
2130     dri_bo_unreference(render_state->sf.state);
2131     render_state->sf.state = NULL;
2132     dri_bo_unreference(render_state->wm.sampler);
2133     render_state->wm.sampler = NULL;
2134     dri_bo_unreference(render_state->wm.state);
2135     render_state->wm.state = NULL;
2136     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2137     dri_bo_unreference(render_state->cc.viewport);
2138     render_state->cc.viewport = NULL;
2139     dri_bo_unreference(render_state->cc.state);
2140     render_state->cc.state = NULL;
2141     dri_bo_unreference(render_state->cc.blend);
2142     render_state->cc.blend = NULL;
2143     dri_bo_unreference(render_state->cc.depth_stencil);
2144     render_state->cc.depth_stencil = NULL;
2145
2146     if (render_state->draw_region) {
2147         dri_bo_unreference(render_state->draw_region->bo);
2148         free(render_state->draw_region);
2149         render_state->draw_region = NULL;
2150     }
2151
2152     return True;
2153 }
2154