2 * Copyright © <2010>, Intel Corporation.
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4 * This program is licensed under the terms and conditions of the
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5 * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
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6 * http://www.opensource.org/licenses/eclipse-1.0.php.
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9 #if !defined(__AVC_ILDB_HEADER__) // Make sure this file is only included once
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10 #define __AVC_ILDB_HEADER__
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12 // Module name: AVC_ILDB.inc
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17 //========== Root thread input parameters ==================================================
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18 #define RootParam r1 // :w
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19 #define MBsCntX r1.0 // :w, MB count per row
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20 #define MBsCntY r1.1 // :w, MB count per col
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21 //#define PicType r1.2 // :w, Picture type
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22 #define MaxThreads r1.3 // :w, Max Thread limit
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23 #define EntrySignature r1.4 // :w, Debug flag
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24 #define BitFields r1.5 // :uw
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25 #define MbaffFlag BIT0 // :w, mbaff flag, bit 0 in BitFields
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26 #define BotFieldFlag BIT1 // :w, bottom field flag, bit 1 in BitFields
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27 #define CntlDataExpFlag BIT2 // :w, Control Data Expansion Flag, bit 2 in BitFields
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28 #define RampConst r1.12 // 8 :ub, Ramp constant, r1.12 - r1.19:ub
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29 #define StepToNextMB r1.20 // :b, 2 bytes
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30 #define Minus2Minus1 r1.22 // :b, 2 bytes
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31 // next one starts at r1.11:w
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33 #define TopFieldFlag 0xFFFD // :w, top field flag, used to set bit1 to 0.
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36 //========== Root Locals =============================================================
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38 // Variables in root kernel for launching child therad
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39 #define ChildParam r2.0 // :w
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40 //Not used #define URBOffset r2.3 // :w, Each row occupies 4 URB entries. All children in the same row use the same set of URB entries
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41 #define CurCol r2.10 // :w, current col
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42 #define CurColB r2.20 // :b, current col
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43 #define CurRow r2.11 // :w, current row
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44 #define CurRowB r2.22 // :b, current row
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45 #define LastCol r2.12 // :w, last col
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46 #define LastRow r2.13 // :w, last row
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48 // Root local constants during spawning process
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49 #define Col_Boundary r3.0 // :w,
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50 #define Row_Boundary r3.1 // :w,
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51 //#define TotalBlocks r3.2 // :w, Total blocks in the frame
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52 #define URB_EntriesPerMB_2 r3.3 // :w, = URB entries per MB, but in differnt form
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53 #define URBOffsetUVBase r3.4 // :w, UV Base offset in URB
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55 #define Temp1_D r3.6 // :d:
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56 #define Temp1_W r3.12 // :w, Temp1
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57 #define Temp1_B r3.24 // :b, = Temp1_W
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58 #define Temp2_W r3.13 // :w, Temp2
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59 #define Temp2_B r3.26 // :b, = Temp2_W
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61 // Root local variables
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62 #define JumpTable r4 // :d, jump table
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63 #define JUMPTABLE_BASE 4*32
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64 #define JumpAddr a0.7
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66 #define TopRowForScan r5.0 // :w, track the top row for scan. All rows above this row is deblocked already.
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69 // Child Thread R0 Header Field
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74 .declare GatewayAperture Base=r50.0 ElementSize=4 SrcRegion=REGION(8,1) Type=ud
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75 #define GatewayApertureB 1600 // r50 byte offset from r0.0
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77 // Chroma root thread updates luma root's ThreadLimit at r10.0:w via gateway
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78 #define ThreadLimit r62.0 // :w, thread limit //r56.0
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79 #define THREAD_LIMIT_OFFSET 0x01800000 // Offset from r50 to r56 = 12*32 = 384 = 0x0180. 0x180 << 16 = 0x01800000
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80 //#define THREAD_LIMIT_OFFSET 0x00C00000 // Offset from r50 to r56 = 6*32 = 192 = 0x00C0. 0xC0 << 16 = 0x00C00000
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83 // Gateway size is 16 GRF. 68 rows of MBs takes 9 GRFs (r6 - r14)
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84 // For CTG: Expended to support 1280 rows of pixel (80 rows of MBs). It requires 10 GRFs (r6 - r15)
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85 .declare GatewayAperture Base=r6.0 ElementSize=4 SrcRegion=REGION(8,1) Type=ud
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86 #define GatewayApertureB 192 // r0.0 byte offset from r0.0
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88 // Chroma root thread updates luma root's ThreadLimit at r10.0:w via gateway
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89 #define ThreadLimit r18.0 // :w, thread limit
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90 #define THREAD_LIMIT_OFFSET 0x01800000 // Offset from r50 to r56 = 12*32 = 384 = 0x0180. 0x180 << 16 = 0x01800000
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91 #define TotalBlocks r18.1 // :w, Total blocks in the frame
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93 // Root local variables
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94 #define ChildThreadsID r19.0 // :w, Child thread ID, unique to each child
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95 #define OutstandingThreads r20.0 // :w, Outstanding threads
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96 #define ProcessedMBs r20.1 // :w, # of MBs processed
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98 #define URBOffset r21.0 // :w, Each row occupies 4 URB entries. All children in the same row use the same set of URB entries
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100 //=================================================================================
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102 #define ScoreBd_Size 128 //96 // size of Status[] or ProcCol[]
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104 #define ScoreBd_Idx 2
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105 //#define Saved_Col 0
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107 #define StatusAddr a0.4 // :w, point to r50
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108 //=================================================================================
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112 #define GatewayPayload r48.0 // :ud
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113 #define GatewayPayloadKey r48.8 // :uw
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114 #define DispatchID r48.20 // :ub
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115 #define RegBase_GatewaySize r48.5 // :ud, used in open a gateway
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116 #define Offset_Length r48.5 // :ud, used in forwardmsg back to root
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117 #define EUID_TID r48.9 // :uw, used in forwardmsg back to root
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119 // Gateway response
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120 #define GatewayResponse r49.0 // :ud, one GRF
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122 #define URBWriteMsgDesc a0.0 // Used in URB write, :ud
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123 #define URBWriteMsgDescLow a0.0 // Used in URB write, :uw
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124 #define URBWriteMsgDescHigh a0.1 // Used in URB write, :uw
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126 .declare WritebackResponse Base=r50 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 1 GRF for write backs
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129 /////////////////////////////////////////////////////////////////////////////////////////////
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130 // IDesc Order Offset
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132 // 0) luma root 0 from luma root
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133 // 1) luma child 16 from luma root
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134 // 2) chroma root 32 from luma root
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135 // 3) chroma child 16 from chroma root
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137 // 4) luma field root 0 from luma field root
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138 // 5) luma field child 16 from luma field root
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139 // 6) chroma field root 32 from luma field root
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140 // 7) chroma field child 16 from chroma field root
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142 // 8) luma Mbaff root 0 from luma Mbaff root
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143 // 9) luma Mbaff child 16 from luma Mbaff root
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144 // 10) chroma Mbaff root 32 from luma Mbaff root
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145 // 11) chroma Mbaff child 16 from chroma Mbaff root
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147 // IDesc offset within non-mbaff or mbaff mode
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148 #define CHROMA_ROOT_OFFSET 32 // Offset from luma root to chroma root
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149 #define CHILD_OFFSET 16 // Offset from luma root to luma child,
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150 // and from chroma root to chroma child
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151 /////////////////////////////////////////////////////////////////////////////////////////////
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154 //========== End of Root Variables ======================================================
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157 //========== Child thread input parameters ==============================================
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158 //#define MBsCntX r1.0 // :w, MB count per row (same as root)
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159 //#define MBsCntY r1.1 // :w, MB count per col (same as root)
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160 //#define PicTypeC r1.2 // :w, Picture type same as root thread (same as root)
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161 #define URBOffsetC r1.3 // :w,
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162 #define EntrySignatureC r1.4 // :w, Debug field (same as root)
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163 //#define BitFields r1.5 // :w (same as root)
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164 //#define MbaffFlag BIT0 // :w, mbaff flag, bit 0 in BitFields
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165 //#define BotFieldFlag BIT1 // :w, bottom field flag, bit 1 in BitFields
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166 //#define CntlDataExpFlag BIT2 // :w, Control Data Expansion Flag, bit 2 in BitFields
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167 #define RampConstC r1.12 // 8 :ub, Ramp constant, r1.12 - r1.19:ub.
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168 #define ORIX r1.10 // :w, carry over from root r1 in MB count
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169 #define ORIY r1.11 // :w, carry over from root r1 in MB count
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170 #define LastColC r1.12 // :w, last col
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171 #define LastRowC r1.13 // :w, last row
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173 .declare GatewayApertureC Base=r1.0 ElementSize=4 SrcRegion=REGION(8,1) Type=ud
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174 #define GatewayApertureCBase 32 // r1 byte offset from r0.0
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177 //========== Child Variables ============================================================
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179 // Mbaff Alpha, Beta, Tc0 vectors for an edge
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180 .declare Mbaff_ALPHA Base=r14.0 ElementSize=2 SrcRegion=REGION(8,1) Type=uw // r14
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181 .declare Mbaff_BETA Base=r15.0 ElementSize=2 SrcRegion=REGION(8,1) Type=uw // r15
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182 .declare Mbaff_TC0 Base=r16.0 ElementSize=2 SrcRegion=REGION(8,1) Type=uw // r16
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183 .declare RRampW Base=r17.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w // r17
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185 .declare Mbaff_ALPHA2 Base=r45.0 ElementSize=2 SrcRegion=REGION(8,1) Type=uw // alpha2 = (alpha >> 2) + 2
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188 #define ORIX_CUR r46.0 // :w, current block origin X in bytes
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189 #define ORIY_CUR r46.1 // :w, current block origin Y in bytes
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190 #define ORIX_LEFT r46.2 // :w, left block origin X in bytes
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191 #define ORIY_LEFT r46.3 // :w, left block origin Y in bytes
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192 #define ORIX_TOP r46.4 // :w, top block origin X in bytes
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193 #define ORIY_TOP r46.5 // :w, top block origin Y in bytes
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194 //#define FilterSampleFlag r46.6 // :uw,
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195 #define CTemp0_W r46.7 // :w, child Temp0
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197 #define alpha r46.8 // :w, Scaler version for non Mbaff
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198 #define beta r46.9 // :w, Scaler version for non Mbaff
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199 #define tc0 r46.20 // 4 :ub, r46.20 ~ r46.23, Scaler version for non Mbaff
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200 #define MaskA r46.12 // :uw
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201 #define MaskB r46.13 // :uw
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203 // Child control flags
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204 #define DualFieldMode r47.0 // Cur MB is frame based, above MB is field based in mbaff mode
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205 // :uw, 0 = not in dual field mode, 1 = in dual field mode, filter both top and bot fields
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206 #define GateWayOffsetC r47.1 // :w, Gateway offset for child writing into root space
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207 #define CntrlDataOffsetY r47.1 // :ud, MB control data data offset
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208 #define alpha2 r47.4 // :uw, alpha2 = (alpha >> 2) + 2
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210 #define VertEdgePattern r47.5 // :uw,
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212 #define CTemp1_W r47.6 // :w, child Temp1
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213 #define CTemp1_B r47.12 // :b, = child Temp1_W
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214 #define CTemp2_W r47.7 // :w, child Temp2
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215 #define CTemp2_B r47.14 // :b, = child Temp2_W
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218 #define ECM_AddrReg a0.4 // Edge Control Map register
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219 #define P_AddrReg a0.6 // point to P samples in left or top MB
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220 #define Q_AddrReg a0.7 // point to Q samples in cur MB
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223 .declare RTempD Base=r26.0 ElementSize=4 SrcRegion=REGION(8,1) Type=d // r26-27
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224 .declare RTempB Base=r26.0 ElementSize=1 SrcRegion=REGION(8,4) Type=ub // r26-27
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225 .declare RTempW Base=r26.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w // r26-27
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226 #define LEFT_TEMP_D RTempD
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227 #define LEFT_TEMP_B RTempB
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228 #define LEFT_TEMP_W RTempW
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230 .declare TempRow0 Base=r26.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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231 .declare TempRow0B Base=r26.0 ElementSize=1 SrcRegion=REGION(8,2) Type=ub
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232 .declare TempRow1 Base=r27.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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233 .declare TempRow1B Base=r27.0 ElementSize=1 SrcRegion=REGION(8,2) Type=ub
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235 .declare CUR_TEMP_D Base=r28.0 ElementSize=4 SrcRegion=REGION(8,1) Type=d // 8 GRFs
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236 .declare CUR_TEMP_B Base=r28.0 ElementSize=1 SrcRegion=REGION(8,4) Type=ub
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237 .declare CUR_TEMP_W Base=r28.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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239 #define FilterSampleFlag r28.0 // :uw,
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241 .declare A Base=r28.0 ElementSize=2 SrcRegion=REGION(16,1) Type=w
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242 .declare B Base=r29.0 ElementSize=2 SrcRegion=REGION(16,1) Type=w
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244 .declare TempRow3 Base=r30.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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245 .declare TempRow3B Base=r30.0 ElementSize=1 SrcRegion=REGION(8,2) Type=ub
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247 .declare tc0_exp Base=r30.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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248 .declare tc8 Base=r30.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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250 .declare tc_exp Base=r31.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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251 .declare tx_exp_8 Base=r31.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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253 .declare q0_p0 Base=r32.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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254 .declare ABS_q0_p0 Base=r33.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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256 .declare ap Base=r34.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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257 .declare aq Base=r35.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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259 // These buffers have the src data for each edge to be beblocked.
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260 // They have modified pixels from previous edges.
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263 // +----+----+----+----+----+----+----+----+
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264 // | p3 | p2 | P1 | p0 | q0 | q1 | q2 | q3 |
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265 // +----+----+----+----+----+----+----+----+
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267 // p3 = r[P_AddrReg, 0]<16;16,1>
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268 // p2 = r[P_AddrReg, 16]<16;16,1>
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269 // p1 = r[P_AddrReg, 32]<16;16,1>
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270 // p0 = r[P_AddrReg, 48]<16;16,1>
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271 // q0 = r[Q_AddrReg, 0]<16;16,1>
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272 // q1 = r[Q_AddrReg, 16]<16;16,1>
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273 // q2 = r[Q_AddrReg, 32]<16;16,1>
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274 // q3 = r[Q_AddrReg, 48]<16;16,1>
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276 .declare p0123_W Base=r36.0 ElementSize=2 SrcRegion=REGION(16,1) Type=uw // r36, r37
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277 .declare q0123_W Base=r38.0 ElementSize=2 SrcRegion=REGION(16,1) Type=uw // r38, r39
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278 .declare p3 Base=r36.0 ElementSize=1 SrcRegion=REGION(8,1) Type=ub
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279 .declare p2 Base=r36.16 ElementSize=1 SrcRegion=REGION(8,1) Type=ub
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280 .declare p1 Base=r37.0 ElementSize=1 SrcRegion=REGION(8,1) Type=ub
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281 .declare p0 Base=r37.16 ElementSize=1 SrcRegion=REGION(8,1) Type=ub
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282 .declare q0 Base=r38.0 ElementSize=1 SrcRegion=REGION(8,1) Type=ub
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283 .declare q1 Base=r38.16 ElementSize=1 SrcRegion=REGION(8,1) Type=ub
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284 .declare q2 Base=r39.0 ElementSize=1 SrcRegion=REGION(8,1) Type=ub
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285 .declare q3 Base=r39.16 ElementSize=1 SrcRegion=REGION(8,1) Type=ub
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287 .declare TempRow2 Base=r38.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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289 // Temp space for mbaff dual field mode
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290 #define ABOVE_CUR_MB_BASE 40*GRFWIB // Byte offset to r40
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291 .declare ABOVE_CUR_MB_YW Base=r40 ElementSize=2 SrcRegion=REGION(8,1) Type=uw
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292 .declare ABOVE_CUR_MB_UW Base=r40 ElementSize=2 SrcRegion=REGION(8,1) Type=uw
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294 .declare P0_plus_P1 Base=r41.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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295 .declare Q0_plus_Q1 Base=r42.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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297 .declare P2_plus_P3 Base=r43.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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298 .declare Q2_plus_Q3 Base=r44.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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301 //////////////////////////////////////////////////////////////////////////////////////////
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302 // MB control data reference
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304 // Expanded control data is in r18 - r25
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305 .declare CNTRL_DATA_D Base=r18 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // For read, 8 GRFs
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306 #define CNTRL_DATA_BASE 18*GRFWIB // Base offset to r18
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308 // Bit mask for extracting bits
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309 #define MbaffFrameFlag 0x01
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310 #define FieldModeCurrentMbFlag 0x02
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311 #define FieldModeLeftMbFlag 0x04
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312 #define FieldModeAboveMbFlag 0x08
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313 #define FilterInternal8x8EdgesFlag 0x10
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314 #define FilterInternal4x4EdgesFlag 0x20
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315 #define FilterLeftMbEdgeFlag 0x40
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316 #define FilterTopMbEdgeFlag 0x80
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318 #define DISABLE_ILDB_FLAG 0x01
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320 // Exact bit pattern for left and cur MB coding mode (frame vs. field)
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321 #define LEFT_FRAME_CUR_FRAME 0x00
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322 #define LEFT_FRAME_CUR_FIELD 0x02
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323 #define LEFT_FIELD_CUR_FRAME 0x04
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324 #define LEFT_FIELD_CUR_FIELD 0x06
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326 // Exact bit pattern for above and cur MB coding mode (frame vs. field)
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327 #define ABOVE_FRAME_CUR_FRAME 0x00
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328 #define ABOVE_FRAME_CUR_FIELD 0x02
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329 #define ABOVE_FIELD_CUR_FRAME 0x08
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330 #define ABOVE_FIELD_CUR_FIELD 0x0A
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334 //========== MB control data field offset in byte ==========
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336 #if !defined(_APPLE)
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338 // GRF0 - GRF1 holds original control data
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341 #define HorizOrigin 0
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342 #define VertOrigin 1
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343 #define BitFlags 2 // Bit flags
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345 #define bbSinternalLeftVert 4 // Internal left vertical bS, 2 bits per bS for 4 Y pixels and 2 U/V pixels
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346 #define bbSinternalMidVert 5 // Internal mid vertical bS
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347 #define bbSinternalRightVert 6 // Internal right vertical bS
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348 #define bbSinternalTopHorz 7 // Internal top horizontal bS
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350 #define bbSinternalMidHorz 8 // Internal mid horizontal bS
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351 #define bbSinternalBotHorz 9 // Internal bottom horizontal bS
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352 #define wbSLeft0 10 // External left vertical bS (0), 4 bits per bS for 4 Y pixels and 2 U/V pixels, and byte 11
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354 #define wbSLeft1 12 // External left vertical bS (1), and byte 13
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355 #define wbSTop0 14 // External top horizontal bS (0), and byte 15
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357 #define wbSTop1 16 // Externaltop horizontal bS (1), and byte 17
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358 #define bIndexAinternal_Y 18 // Internal index A for Y
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359 #define bIndexBinternal_Y 19 // Internal index B for Y
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361 #define bIndexAleft0_Y 20 // Left index A for Y (0)
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362 #define bIndexBleft0_Y 21 // Left index B for Y (0)
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363 #define bIndexAleft1_Y 22 // Left index A for Y (1)
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364 #define bIndexBleft1_Y 23 // Left index B for Y (1)
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366 #define bIndexAtop0_Y 24 // Top index A for Y (0)
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367 #define bIndexBtop0_Y 25 // Top index B for Y (0)
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368 #define bIndexAtop1_Y 26 // Top index A for Y (1)
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369 #define bIndexBtop1_Y 27 // Top index B for Y (1)
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371 #define bIndexAinternal_Cb 28 // Internal index A for Cb
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372 #define bIndexBinternal_Cb 29 // Internal index B for Cb
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373 #define bIndexAleft0_Cb 30 // Left index A for Cb (0)
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374 #define bIndexBleft0_Cb 31 // Left index B for Cb (0)
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377 #define bIndexAleft1_Cb 32 // Left index A for Cb (1)
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378 #define bIndexBleft1_Cb 33 // Left index B for Cb (1)
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379 #define bIndexAtop0_Cb 34 // Top index A for Cb (0)
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380 #define bIndexBtop0_Cb 35 // Top index B for Cb (0)
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382 #define bIndexAtop1_Cb 36 // Top index A for Cb (1)
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383 #define bIndexBtop1_Cb 37 // Top index B for Cb (1)
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384 #define bIndexAinternal_Cr 38 // Internal index A for Cr
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385 #define bIndexBinternal_Cr 39 // Internal index B for Cr
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387 #define bIndexAleft0_Cr 40 // Left index A for Cr (0)
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388 #define bIndexBleft0_Cr 41 // Left index B for Cr (0)
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389 #define bIndexAleft1_Cr 42 // Left index A for Cr (1)
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390 #define bIndexBleft1_Cr 43 // Left index B for Cr (1)
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392 #define bIndexAtop0_Cr 44 // Top index A for Cr (0)
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393 #define bIndexBtop0_Cr 45 // Top index B for Cr (0)
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394 #define bIndexAtop1_Cr 46 // Top index A for Cr (1)
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395 #define bIndexBtop1_Cr 47 // Top index B for Cr (1)
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397 #define ExtBitFlags 48 // Extended bit flags, such as disable ILDB bits
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399 // Offset 49 - 63 not used
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402 //===== GRF2 - GRF7 hold expanded control data =====
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405 #define wEdgeCntlMap_IntLeftVert 64 // Derived from bbSinternalLeftVert, 1 bit per pixel
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406 #define wEdgeCntlMap_IntMidVert 66 // Derived from bbSinternalLeftVert
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408 #define wEdgeCntlMap_IntRightVert 68 // Derived from bbSinternalRightVert
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409 #define wEdgeCntlMap_IntTopHorz 70 // Derived from bbSinternalTopHorz, 1bit per pixel
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411 #define wEdgeCntlMap_IntMidHorz 72 // Derived from bbSinternalMidHorz
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412 #define wEdgeCntlMap_IntBotHorz 74 // Derived from bbSinternalBotHorz
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414 // Offset 76 - 79 not used
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416 #define wEdgeCntlMapA_ExtLeftVert0 80 // Derived from wbSLeft0, 1bit per pixel
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417 #define wEdgeCntlMapB_ExtLeftVert0 82 // Derived from wbSLeft0
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419 #define wEdgeCntlMapA_ExtTopHorz0 84 // Derived from wbSTop0, 1bit per pixel
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420 #define wEdgeCntlMapB_ExtTopHorz0 86 // Derived from wbSTop0
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422 #define wEdgeCntlMapA_ExtLeftVert1 88 // Derived from wbSLeft1, 1bit per pixel
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423 #define wEdgeCntlMapB_ExtLeftVert1 90 // Derived from wbSLeft1
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425 #define wEdgeCntlMapA_ExtTopHorz1 92 // Derived from wbSTop1, 1bit per pixel
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426 #define wEdgeCntlMapB_ExtTopHorz1 94 // Derived from wbSTop1
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430 #define bTc0_v00_0_Y 96 // Derived from bSv00_0 and bIndexAleft0_Y, 4 pixels per tc0
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431 #define bTc0_v10_0_Y 97 // Derived from bSv10_0 and bIndexAleft0_Y
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432 #define bTc0_v20_0_Y 98 // Derived from bSv20_0 and bIndexAleft0_Y
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433 #define bTc0_v30_0_Y 99 // Derived from bSv30_0 and bIndexAleft0_Y
\r
435 #define bTc0_v01_Y 100 // Derived from bSv01 and bIndexAinternal_Y
\r
436 #define bTc0_v11_Y 101 // Derived from bSv11 and bIndexAinternal_Y
\r
437 #define bTc0_v21_Y 102 // Derived from bSv21 and bIndexAinternal_Y
\r
438 #define bTc0_v31_Y 103 // Derived from bSv31 and bIndexAinternal_Y
\r
440 #define bTc0_v02_Y 104 // Derived from bSv02 and bIndexAinternal_Y
\r
441 #define bTc0_v12_Y 105 // Derived from bSv12 and bIndexAinternal_Y
\r
442 #define bTc0_v22_Y 106 // Derived from bSv22 and bIndexAinternal_Y
\r
443 #define bTc0_v32_Y 107 // Derived from bSv32 and bIndexAinternal_Y
\r
445 #define bTc0_v03_Y 108 // Derived from bSv03 and bIndexAinternal_Y
\r
446 #define bTc0_v13_Y 109 // Derived from bSv13 and bIndexAinternal_Y
\r
447 #define bTc0_v23_Y 110 // Derived from bSv23 and bIndexAinternal_Y
\r
448 #define bTc0_v33_Y 111 // Derived from bSv33 and bIndexAinternal_Y
\r
450 #define bTc0_h00_0_Y 112 // Derived from bSh00_0 and bIndexAleft0_Y
\r
451 #define bTc0_h01_0_Y 113 // Derived from bSh01_0 and bIndexAleft0_Y
\r
452 #define bTc0_h02_0_Y 114 // Derived from bSh02_0 and bIndexAleft0_Y
\r
453 #define bTc0_h03_0_Y 115 // Derived from bSh03_0 and bIndexAleft0_Y
\r
455 #define bTc0_h10_Y 116 // Derived from bSh10 and bIndexAinternal_Y
\r
456 #define bTc0_h11_Y 117 // Derived from bSh11 and bIndexAinternal_Y
\r
457 #define bTc0_h12_Y 118 // Derived from bSh12 and bIndexAinternal_Y
\r
458 #define bTc0_h13_Y 119 // Derived from bSh13 and bIndexAinternal_Y
\r
460 #define bTc0_h20_Y 120 // Derived from bSh20 and bIndexAinternal_Y
\r
461 #define bTc0_h21_Y 121 // Derived from bSh21 and bIndexAinternal_Y
\r
462 #define bTc0_h22_Y 122 // Derived from bSh22 and bIndexAinternal_Y
\r
463 #define bTc0_h23_Y 123 // Derived from bSh23 and bIndexAinternal_Y
\r
465 #define bTc0_h30_Y 124 // Derived from bSh30 and bIndexAinternal_Y
\r
466 #define bTc0_h31_Y 125 // Derived from bSh31 and bIndexAinternal_Y
\r
467 #define bTc0_h32_Y 126 // Derived from bSh32 and bIndexAinternal_Y
\r
468 #define bTc0_h33_Y 127 // Derived from bSh33 and bIndexAinternal_Y
\r
471 #define bAlphaLeft0_Y 128 // Derived from bIndexAleft0_Y
\r
472 #define bBetaLeft0_Y 129 // Derived from bIndexBleft0_Y
\r
473 #define bAlphaTop0_Y 130 // Derived from bIndexAtop0_Y
\r
474 #define bBetaTop0_Y 131 // Derived from bIndexBtop0_Y
\r
476 #define bAlphaInternal_Y 132 // Derived from bIndexAinternal_Y
\r
477 #define bBetaInternal_Y 133 // Derived from bIndexBinternal_Y
\r
478 // Offset 134 - 135 not used
\r
480 // Offset 136 - 143 not used
\r
481 #define bAlphaLeft1_Y 144 // Derived from bIndexAleft1_Y Used in Mbaff mode only
\r
482 #define bBetaLeft1_Y 145 // Derived from bIndexBleft1_Y Used in Mbaff mode only
\r
483 #define bAlphaTop1_Y 146 // Derived from bIndexAtop1_Y Used in Mbaff mode only
\r
484 #define bBetaTop1_Y 147 // Derived from bIndexBtop1_Y Used in Mbaff mode only
\r
486 // Offset 148 - 151 not used
\r
487 #define bTc0_v00_1_Y 152 // Derived from bSv00_1 and bIndexAleft1_Y Used in Mbaff mode only
\r
488 #define bTc0_v10_1_Y 153 // Derived from bSv10_1 and bIndexAleft1_Y Used in Mbaff mode only
\r
489 #define bTc0_v20_1_Y 154 // Derived from bSv20_1 and bIndexAleft1_Y Used in Mbaff mode only
\r
490 #define bTc0_v30_1_Y 155 // Derived from bSv30_1 and bIndexAleft1_Y Used in Mbaff mode only
\r
492 #define bTc0_h00_1_Y 156 // Derived from bSh00_1 and bIndexAleft1_Y Used in Mbaff mode only
\r
493 #define bTc0_h01_1_Y 157 // Derived from bSh01_1 and bIndexAleft1_Y Used in Mbaff mode only
\r
494 #define bTc0_h02_1_Y 158 // Derived from bSh02_1 and bIndexAleft1_Y Used in Mbaff mode only
\r
495 #define bTc0_h03_1_Y 159 // Derived from bSh03_1 and bIndexAleft1_Y Used in Mbaff mode only
\r
499 #define bTc0_v00_0_Cb 160 // Derived from bSv00_0 and bIndexAleft0_Cb, 2 pixels per tc0 Left0
\r
500 #define bTc0_v10_0_Cb 161 // Derived from bSv10_0 and bIndexAleft0_Cb
\r
501 #define bTc0_v20_0_Cb 162 // Derived from bSv20_0 and bIndexAleft0_Cb
\r
502 #define bTc0_v30_0_Cb 163 // Derived from bSv30_0 and bIndexAleft0_Cb
\r
504 #define bTc0_v02_Cb 164 // Derived from bSv02 and bIndexAinternal_Cb MidVert
\r
505 #define bTc0_v12_Cb 165 // Derived from bSv12 and bIndexAinternal_Cb
\r
506 #define bTc0_v22_Cb 166 // Derived from bSv22 and bIndexAinternal_Cb
\r
507 #define bTc0_v32_Cb 167 // Derived from bSv32 and bIndexAinternal_Cb
\r
509 #define bTc0_h00_0_Cb 168 // Derived from bSh00_0 and bIndexAleft0_Cb Top0
\r
510 #define bTc0_h01_0_Cb 169 // Derived from bSh01_0 and bIndexAleft0_Cb
\r
511 #define bTc0_h02_0_Cb 170 // Derived from bSh02_0 and bIndexAleft0_Cb
\r
512 #define bTc0_h03_0_Cb 171 // Derived from bSh03_0 and bIndexAleft0_Cb
\r
514 #define bTc0_h20_Cb 172 // Derived from bSh20 and bIndexAinternal_Cb MidHorz
\r
515 #define bTc0_h21_Cb 173 // Derived from bSh21 and bIndexAinternal_Cb
\r
516 #define bTc0_h22_Cb 174 // Derived from bSh22 and bIndexAinternal_Cb
\r
517 #define bTc0_h23_Cb 175 // Derived from bSh23 and bIndexAinternal_Cb
\r
519 #define bTc0_v00_0_Cr 176 // Derived from bSv00_0 and bIndexAleft0_Cr, 2 pixels per tc0 Left0
\r
520 #define bTc0_v10_0_Cr 177 // Derived from bSv10_0 and bIndexAleft0_Cr
\r
521 #define bTc0_v20_0_Cr 178 // Derived from bSv20_0 and bIndexAleft0_Cr
\r
522 #define bTc0_v30_0_Cr 179 // Derived from bSv30_0 and bIndexAleft0_Cr
\r
524 #define bTc0_v02_Cr 180 // Derived from bSv02 and bIndexAinternal_Cr Mid Vert
\r
525 #define bTc0_v12_Cr 181 // Derived from bSv12 and bIndexAinternal_Cr
\r
526 #define bTc0_v22_Cr 182 // Derived from bSv22 and bIndexAinternal_Cr
\r
527 #define bTc0_v32_Cr 183 // Derived from bSv32 and bIndexAinternal_Cr
\r
529 #define bTc0_h00_0_Cr 184 // Derived from bSh00_0 and bIndexAleft0_Cr, 2 pixels per tc0 Top0
\r
530 #define bTc0_h01_0_Cr 185 // Derived from bSh01_0 and bIndexAleft0_Cr
\r
531 #define bTc0_h02_0_Cr 186 // Derived from bSh02_0 and bIndexAleft0_Cr
\r
532 #define bTc0_h03_0_Cr 187 // Derived from bSh03_0 and bIndexAleft0_Cr
\r
534 #define bTc0_h20_Cr 188 // Derived from bSh20 and bIndexAinternal_Cr Mid Horz
\r
535 #define bTc0_h21_Cr 189 // Derived from bSh21 and bIndexAinternal_Cr
\r
536 #define bTc0_h22_Cr 190 // Derived from bSh22 and bIndexAinternal_Cr
\r
537 #define bTc0_h23_Cr 191 // Derived from bSh23 and bIndexAinternal_Cr
\r
540 #define bAlphaLeft0_Cb 192 // Derived from bIndexAleft0_Cb
\r
541 #define bBetaLeft0_Cb 193 // Derived from bIndexBleft0_Cb
\r
542 #define bAlphaTop0_Cb 194 // Derived from bIndexAtop0_Cb
\r
543 #define bBetaTop0_Cb 195 // Derived from bIndexBtop0_Cb
\r
545 #define bAlphaInternal_Cb 196 // Derived from bIndexAinternal_Cb
\r
546 #define bBetaInternal_Cb 197 // Derived from bIndexBinternal_Cb
\r
547 // Offset 198 - 199 not used
\r
549 #define bAlphaLeft0_Cr 200 // Derived from bIndexAleft0_Cr
\r
550 #define bBetaLeft0_Cr 201 // Derived from bIndexBleft0_Cr
\r
551 #define bAlphaTop0_Cr 202 // Derived from bIndexAtop0_Cr
\r
552 #define bBetaTop0_Cr 203 // Derived from bIndexBtop0_Cr
\r
554 #define bAlphaInternal_Cr 204 // Derived from bIndexAinternal_Cr
\r
555 #define bBetaInternal_Cr 205 // Derived from bIndexBinternal_Cr
\r
556 // Offset 206 - 223 not used
\r
559 #define bAlphaLeft1_Cb 224 // Derived from bIndexAleft1_Cb Used in Mbaff mode only
\r
560 #define bBetaLeft1_Cb 225 // Derived from bIndexBleft1_Cb Used in Mbaff mode only
\r
561 #define bAlphaTop1_Cb 226 // Derived from bIndexAtop1_Cb Used in Mbaff mode only
\r
562 #define bBetaTop1_Cb 227 // Derived from bIndexBtop1_Cb Used in Mbaff mode only
\r
564 // Offset 228 - 231 not used
\r
566 #define bTc0_v00_1_Cb 232 // Derived from bSv00_1 and bIndexAleft1_Cb Used in Mbaff mode only
\r
567 #define bTc0_v10_1_Cb 233 // Derived from bSv10_1 and bIndexAleft1_Cb Used in Mbaff mode only
\r
568 #define bTc0_v20_1_Cb 234 // Derived from bSv20_1 and bIndexAleft1_Cb Used in Mbaff mode only
\r
569 #define bTc0_v30_1_Cb 235 // Derived from bSv30_1 and bIndexAleft1_Cb Used in Mbaff mode only
\r
571 #define bTc0_h00_1_Cb 236 // Derived from bSh00_1 and bIndexAleft1_Cb Used in Mbaff mode only
\r
572 #define bTc0_h01_1_Cb 237 // Derived from bSh01_1 and bIndexAleft1_Cb Used in Mbaff mode only
\r
573 #define bTc0_h02_1_Cb 238 // Derived from bSh02_1 and bIndexAleft1_Cb Used in Mbaff mode only
\r
574 #define bTc0_h03_1_Cb 239 // Derived from bSh03_1 and bIndexAleft1_Cb Used in Mbaff mode only
\r
576 #define bAlphaLeft1_Cr 240 // Derived from bIndexAleft1_Cr Used in Mbaff mode only
\r
577 #define bBetaLeft1_Cr 241 // Derived from bIndexBleft1_Cr Used in Mbaff mode only
\r
578 #define bAlphaTop1_Cr 242 // Derived from bIndexAtop1_Cr Used in Mbaff mode only
\r
579 #define bBetaTop1_Cr 243 // Derived from bIndexBtop1_Cr Used in Mbaff mode only
\r
581 // Offset 244 - 247 not used
\r
583 #define bTc0_v00_1_Cr 248 // Derived from bSv00_1 and bIndexAleft1_Cr Used in Mbaff mode only
\r
584 #define bTc0_v10_1_Cr 249 // Derived from bSv10_1 and bIndexAleft1_Cr Used in Mbaff mode only
\r
585 #define bTc0_v20_1_Cr 250 // Derived from bSv20_1 and bIndexAleft1_Cr Used in Mbaff mode only
\r
586 #define bTc0_v30_1_Cr 251 // Derived from bSv30_1 and bIndexAleft1_Cr Used in Mbaff mode only
\r
588 #define bTc0_h00_1_Cr 252 // Derived from bSh00_1 and bIndexAleft1_Cr Used in Mbaff mode only
\r
589 #define bTc0_h01_1_Cr 253 // Derived from bSh01_1 and bIndexAleft1_Cr Used in Mbaff mode only
\r
590 #define bTc0_h02_1_Cr 254 // Derived from bSh02_1 and bIndexAleft1_Cr Used in Mbaff mode only
\r
591 #define bTc0_h03_1_Cr 255 // Derived from bSh03_1 and bIndexAleft1_Cr Used in Mbaff mode only
\r
594 #else // _APPLE is defined
\r
596 //******** Crestline for Apple, progressive only, 88 bytes **********
\r
599 #define HorizOrigin 0
\r
600 #define VertOrigin 1
\r
601 #define BitFlags 2 // Bit flags
\r
603 #define wEdgeCntlMap_IntLeftVert 4 // Derived from bbSinternalLeftVert, 1 bit per pixel
\r
604 #define wEdgeCntlMap_IntMidVert 6 // Derived from bbSinternalLeftVert
\r
605 #define wEdgeCntlMap_IntRightVert 8 // Derived from bbSinternalRightVert
\r
606 #define wEdgeCntlMap_IntTopHorz 10 // Derived from bbSinternalTopHorz, 1bit per pixel
\r
607 #define wEdgeCntlMap_IntMidHorz 12 // Derived from bbSinternalMidHorz
\r
608 #define wEdgeCntlMap_IntBotHorz 14 // Derived from bbSinternalBotHorz
\r
609 #define wEdgeCntlMapA_ExtLeftVert0 16 // Derived from wbSLeft0, 1bit per pixel
\r
610 #define wEdgeCntlMapB_ExtLeftVert0 18 // Derived from wbSLeft0
\r
611 #define wEdgeCntlMapA_ExtTopHorz0 20 // Derived from wbSTop0, 1bit per pixel
\r
612 #define wEdgeCntlMapB_ExtTopHorz0 22 // Derived from wbSTop0
\r
614 #define bAlphaLeft0_Y 24 // Derived from bIndexAleft0_Y
\r
615 #define bBetaLeft0_Y 25 // Derived from bIndexBleft0_Y
\r
616 #define bAlphaTop0_Y 26 // Derived from bIndexAtop0_Y
\r
617 #define bBetaTop0_Y 27 // Derived from bIndexBtop0_Y
\r
618 #define bAlphaInternal_Y 28 // Derived from bIndexAinternal_Y
\r
619 #define bBetaInternal_Y 29 // Derived from bIndexBinternal_Y
\r
622 #define bTc0_v00_0_Y 32 // Derived from bSv00_0 and bIndexAleft0_Y, 4 pixels per tc0
\r
623 #define bTc0_v10_0_Y 33 // Derived from bSv10_0 and bIndexAleft0_Y
\r
624 #define bTc0_v20_0_Y 34 // Derived from bSv20_0 and bIndexAleft0_Y
\r
625 #define bTc0_v30_0_Y 35 // Derived from bSv30_0 and bIndexAleft0_Y
\r
626 #define bTc0_v01_Y 36 // Derived from bSv01 and bIndexAinternal_Y
\r
627 #define bTc0_v11_Y 37 // Derived from bSv11 and bIndexAinternal_Y
\r
628 #define bTc0_v21_Y 38 // Derived from bSv21 and bIndexAinternal_Y
\r
629 #define bTc0_v31_Y 39 // Derived from bSv31 and bIndexAinternal_Y
\r
630 #define bTc0_v02_Y 40 // Derived from bSv02 and bIndexAinternal_Y
\r
631 #define bTc0_v12_Y 41 // Derived from bSv12 and bIndexAinternal_Y
\r
632 #define bTc0_v22_Y 42 // Derived from bSv22 and bIndexAinternal_Y
\r
633 #define bTc0_v32_Y 43 // Derived from bSv32 and bIndexAinternal_Y
\r
634 #define bTc0_v03_Y 44 // Derived from bSv03 and bIndexAinternal_Y
\r
635 #define bTc0_v13_Y 45 // Derived from bSv13 and bIndexAinternal_Y
\r
636 #define bTc0_v23_Y 46 // Derived from bSv23 and bIndexAinternal_Y
\r
637 #define bTc0_v33_Y 47 // Derived from bSv33 and bIndexAinternal_Y
\r
639 #define bTc0_h00_0_Y 48 // Derived from bSh00_0 and bIndexAleft0_Y
\r
640 #define bTc0_h01_0_Y 49 // Derived from bSh01_0 and bIndexAleft0_Y
\r
641 #define bTc0_h02_0_Y 50 // Derived from bSh02_0 and bIndexAleft0_Y
\r
642 #define bTc0_h03_0_Y 51 // Derived from bSh03_0 and bIndexAleft0_Y
\r
643 #define bTc0_h10_Y 52 // Derived from bSh10 and bIndexAinternal_Y
\r
644 #define bTc0_h11_Y 53 // Derived from bSh11 and bIndexAinternal_Y
\r
645 #define bTc0_h12_Y 54 // Derived from bSh12 and bIndexAinternal_Y
\r
646 #define bTc0_h13_Y 55 // Derived from bSh13 and bIndexAinternal_Y
\r
647 #define bTc0_h20_Y 56 // Derived from bSh20 and bIndexAinternal_Y
\r
648 #define bTc0_h21_Y 57 // Derived from bSh21 and bIndexAinternal_Y
\r
649 #define bTc0_h22_Y 58 // Derived from bSh22 and bIndexAinternal_Y
\r
650 #define bTc0_h23_Y 59 // Derived from bSh23 and bIndexAinternal_Y
\r
651 #define bTc0_h30_Y 60 // Derived from bSh30 and bIndexAinternal_Y
\r
652 #define bTc0_h31_Y 61 // Derived from bSh31 and bIndexAinternal_Y
\r
653 #define bTc0_h32_Y 62 // Derived from bSh32 and bIndexAinternal_Y
\r
654 #define bTc0_h33_Y 63 // Derived from bSh33 and bIndexAinternal_Y
\r
657 #define bTc0_v00_0_Cb 64 // Derived from bSv00_0 and bIndexAleft0_Cb, 2 pixels per tc0 Left0
\r
658 #define bTc0_v10_0_Cb 65 // Derived from bSv10_0 and bIndexAleft0_Cb
\r
659 #define bTc0_v20_0_Cb 66 // Derived from bSv20_0 and bIndexAleft0_Cb
\r
660 #define bTc0_v30_0_Cb 67 // Derived from bSv30_0 and bIndexAleft0_Cb
\r
661 #define bTc0_v02_Cb 68 // Derived from bSv02 and bIndexAinternal_Cb MidVert
\r
662 #define bTc0_v12_Cb 69 // Derived from bSv12 and bIndexAinternal_Cb
\r
663 #define bTc0_v22_Cb 70 // Derived from bSv22 and bIndexAinternal_Cb
\r
664 #define bTc0_v32_Cb 71 // Derived from bSv32 and bIndexAinternal_Cb
\r
665 #define bTc0_h00_0_Cb 72 // Derived from bSh00_0 and bIndexAleft0_Cb Top0
\r
666 #define bTc0_h01_0_Cb 73 // Derived from bSh01_0 and bIndexAleft0_Cb
\r
667 #define bTc0_h02_0_Cb 74 // Derived from bSh02_0 and bIndexAleft0_Cb
\r
668 #define bTc0_h03_0_Cb 75 // Derived from bSh03_0 and bIndexAleft0_Cb
\r
669 #define bTc0_h20_Cb 76 // Derived from bSh20 and bIndexAinternal_Cb MidHorz
\r
670 #define bTc0_h21_Cb 77 // Derived from bSh21 and bIndexAinternal_Cb
\r
671 #define bTc0_h22_Cb 78 // Derived from bSh22 and bIndexAinternal_Cb
\r
672 #define bTc0_h23_Cb 79 // Derived from bSh23 and bIndexAinternal_Cb
\r
674 #define bAlphaLeft0_Cb 80 // Derived from bIndexAleft0_Cb
\r
675 #define bBetaLeft0_Cb 81 // Derived from bIndexBleft0_Cb
\r
676 #define bAlphaTop0_Cb 82 // Derived from bIndexAtop0_Cb
\r
677 #define bBetaTop0_Cb 83 // Derived from bIndexBtop0_Cb
\r
678 #define bAlphaInternal_Cb 84 // Derived from bIndexAinternal_Cb
\r
679 #define bBetaInternal_Cb 85 // Derived from bIndexBinternal_Cb
\r
681 #define ExtBitFlags 86 // Extended bit flags, such as disable ILDB bits
\r
683 // Shared between Cb and Cr
\r
684 #define bTc0_v00_0_Cr bTc0_v00_0_Cb
\r
685 #define bTc0_v10_0_Cr bTc0_v10_0_Cb
\r
686 #define bTc0_v20_0_Cr bTc0_v20_0_Cb
\r
687 #define bTc0_v30_0_Cr bTc0_v30_0_Cb
\r
688 #define bTc0_v02_Cr bTc0_v02_Cb
\r
689 #define bTc0_v12_Cr bTc0_v12_Cb
\r
690 #define bTc0_v22_Cr bTc0_v22_Cb
\r
691 #define bTc0_v32_Cr bTc0_v32_Cb
\r
692 #define bTc0_h00_0_Cr bTc0_h00_0_Cb
\r
693 #define bTc0_h01_0_Cr bTc0_h01_0_Cb
\r
694 #define bTc0_h02_0_Cr bTc0_h02_0_Cb
\r
695 #define bTc0_h03_0_Cr bTc0_h03_0_Cb
\r
696 #define bTc0_h20_Cr bTc0_h20_Cb
\r
697 #define bTc0_h21_Cr bTc0_h21_Cb
\r
698 #define bTc0_h22_Cr bTc0_h22_Cb
\r
699 #define bTc0_h23_Cr bTc0_h23_Cb
\r
701 #define bAlphaLeft0_Cr bAlphaLeft0_Cb
\r
702 #define bBetaLeft0_Cr bBetaLeft0_Cb
\r
703 #define bAlphaTop0_Cr bAlphaTop0_Cb
\r
704 #define bBetaTop0_Cr bBetaTop0_Cb
\r
705 #define bAlphaInternal_Cr bAlphaInternal_Cb
\r
706 #define bBetaInternal_Cr bBetaInternal_Cb
\r
712 //========== End of Child Variables ===============================================================
\r
714 #if !defined(COMBINED_KERNEL)
\r
715 #define ILDB_LABEL(x) x // No symbol extension for standalone kernels
\r
718 #endif // !defined(__AVC_ILDB_HEADER__)
\r
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