2 * Copyright © <2010>, Intel Corporation.
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4 * This program is licensed under the terms and conditions of the
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5 * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
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6 * http://www.opensource.org/licenses/eclipse-1.0.php.
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9 ////////// AVC ILDB filter vertical Mbaff Y ///////////////////////////////////////////////////////
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11 // This filter code prepares the src data and control data for ILDB filtering on all vertical edges of Y.
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13 // It sssumes the data for vertical de-blocking is already transposed.
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17 // +-------+-------+-------+-------+
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21 // +-------+-------+-------+-------+
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25 // +-------+-------+-------+-------+
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29 // +-------+-------+-------+-------+
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33 // +-------+-------+-------+-------+
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36 // Edge Edge Edge Edge
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38 /////////////////////////////////////////////////////////////////////////////
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40 #if defined(_DEBUG)
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41 mov (1) EntrySignatureC:w 0xBBBB:w
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45 //========== Luma deblocking ==========
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48 //---------- Deblock Y external left edge (V0) ----------
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50 cmp.z.f0.0 (8) null:w VertEdgePattern:uw LEFT_FIELD_CUR_FRAME:w
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51 cmp.z.f0.1 (8) null:w VertEdgePattern:uw LEFT_FRAME_CUR_FIELD:w
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53 // Intial set for both are frame or field
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54 mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub
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55 mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub
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56 mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Y]<1;4,0>:ub
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58 // For FieldModeCurrentMbFlag=1 && FieldModeLeftMbFlag=0
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59 (f0.0) mov (8) Mbaff_ALPHA(0,0)<2> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub { NoDDClr }
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60 (f0.0) mov (8) Mbaff_ALPHA(0,1)<2> r[ECM_AddrReg, bAlphaLeft1_Y]<0;1,0>:ub { NoDDChk }
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61 (f0.0) mov (8) Mbaff_BETA(0,0)<2> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub { NoDDClr }
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62 (f0.0) mov (8) Mbaff_BETA(0,1)<2> r[ECM_AddrReg, bBetaLeft1_Y]<0;1,0>:ub { NoDDChk }
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63 (f0.0) mov (8) Mbaff_TC0(0,0)<2> r[ECM_AddrReg, bTc0_v00_0_Y]<1;2,0>:ub { NoDDClr }
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64 (f0.0) mov (8) Mbaff_TC0(0,1)<2> r[ECM_AddrReg, bTc0_v00_1_Y]<1;2,0>:ub { NoDDChk }
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66 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterLeftMbEdgeFlag:w // Check for FilterLeftMbEdgeFlag
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68 // For FieldModeCurrentMbFlag=0 && FieldModeLeftMbFlag=1
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69 (f0.1) mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub { NoDDClr }
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70 (f0.1) mov (8) Mbaff_ALPHA(0,8)<1> r[ECM_AddrReg, bAlphaLeft1_Y]<0;1,0>:ub { NoDDChk }
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71 (f0.1) mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub { NoDDClr }
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72 (f0.1) mov (8) Mbaff_BETA(0,8)<1> r[ECM_AddrReg, bBetaLeft1_Y]<0;1,0>:ub { NoDDChk }
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73 (f0.1) mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Y]<1;2,0>:ub { NoDDClr }
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74 (f0.1) mov (8) Mbaff_TC0(0,8)<1> r[ECM_AddrReg, bTc0_v00_1_Y]<1;2,0>:ub { NoDDChk }
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76 // Get (alpha >> 2) + 2
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77 shr (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA(0) 2:w // alpha >> 2
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79 // p3 = Prev MB Y row 0 = r[P_AddrReg, 0]<16;16,1>
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80 // p2 = Prev MB Y row 1 = r[P_AddrReg, 16]<16;16,1>
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81 // p1 = Prev MB Y row 2 = r[P_AddrReg, 32]<16;16,1>
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82 // p0 = Prev MB Y row 3 = r[P_AddrReg, 48]<16;16,1>
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83 // q0 = Cur MB Y row 0 = r[Q_AddrReg, 0]<16;16,1>
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84 // q1 = Cur MB Y row 1 = r[Q_AddrReg, 16]<16;16,1>
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85 // q2 = Cur MB Y row 2 = r[Q_AddrReg, 32]<16;16,1>
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86 // q3 = Cur MB Y row 3 = r[Q_AddrReg, 48]<16;16,1>
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87 mov (1) P_AddrReg:w PREV_MB_Y_BASE:w { NoDDClr }
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88 mov (1) Q_AddrReg:w SRC_MB_Y_BASE:w { NoDDChk }
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90 // Set MaskA and MaskB
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91 mov (2) MaskA<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]<2;2,1>:uw
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93 add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2
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95 // CALL(FILTER_Y_MBAFF, 1)
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96 PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1)
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99 //------------------------------------------------------------------
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103 //---------- Deblock Y external left edge (V0) ----------
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105 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterLeftMbEdgeFlag:w // Check for FilterLeftMbEdgeFlag
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106 (f0.0) jmpi ILDB_LABEL(BYPASS_EXT_LEFT_EDGE_Y)
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108 // Get vertical border edge control data
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110 // mov (1) f0.0 0:w
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111 and (1) CTemp1_W:uw r[ECM_AddrReg, BitFlags]:ub FieldModeLeftMbFlag+FieldModeCurrentMbFlag:uw
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112 cmp.z.f0.0 (1) null:w CTemp1_W:uw LEFT_FIELD_CUR_FRAME:w
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113 (-f0.0) jmpi LEFT_EDGE_Y_NEXT1
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115 // For FieldModeCurrentMbFlag=1 && FieldModeLeftMbFlag=0
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116 mov (8) Mbaff_ALPHA(0,0)<2> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub { NoDDClr }
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117 mov (8) Mbaff_ALPHA(0,1)<2> r[ECM_AddrReg, bAlphaLeft1_Y]<0;1,0>:ub { NoDDChk }
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118 mov (8) Mbaff_BETA(0,0)<2> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub { NoDDClr }
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119 mov (8) Mbaff_BETA(0,1)<2> r[ECM_AddrReg, bBetaLeft1_Y]<0;1,0>:ub { NoDDChk }
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120 mov (8) Mbaff_TC0(0,0)<2> r[ECM_AddrReg, bTc0_v00_0_Y]<1;2,0>:ub { NoDDClr }
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121 mov (8) Mbaff_TC0(0,1)<2> r[ECM_AddrReg, bTc0_v00_1_Y]<1;2,0>:ub { NoDDChk }
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123 jmpi LEFT_EDGE_Y_ALPHA_BETA_TC0_SELECTED
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126 cmp.z.f0.0 (1) null:w CTemp1_W:uw LEFT_FRAME_CUR_FIELD:w
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127 (-f0.0) jmpi LEFT_EDGE_Y_NEXT2
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130 // For FieldModeCurrentMbFlag=0 && FieldModeLeftMbFlag=1
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131 mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub { NoDDClr }
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132 mov (8) Mbaff_ALPHA(0,8)<1> r[ECM_AddrReg, bAlphaLeft1_Y]<0;1,0>:ub { NoDDChk }
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133 mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub { NoDDClr }
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134 mov (8) Mbaff_BETA(0,8)<1> r[ECM_AddrReg, bBetaLeft1_Y]<0;1,0>:ub { NoDDChk }
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135 mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Y]<1;2,0>:ub { NoDDClr }
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136 mov (8) Mbaff_TC0(0,8)<1> r[ECM_AddrReg, bTc0_v00_1_Y]<1;2,0>:ub { NoDDChk }
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138 jmpi LEFT_EDGE_Y_ALPHA_BETA_TC0_SELECTED
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141 // both are frame or field
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142 mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub
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143 mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub
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144 mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Y]<1;4,0>:ub
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146 LEFT_EDGE_Y_ALPHA_BETA_TC0_SELECTED:
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148 mov (2) MaskA<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]<2;2,1>:uw
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150 // p3 = Prev MB Y row 0 = r[P_AddrReg, 0]<16;16,1>
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151 // p2 = Prev MB Y row 1 = r[P_AddrReg, 16]<16;16,1>
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152 // p1 = Prev MB Y row 2 = r[P_AddrReg, 32]<16;16,1>
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153 // p0 = Prev MB Y row 3 = r[P_AddrReg, 48]<16;16,1>
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154 // q0 = Cur MB Y row 0 = r[Q_AddrReg, 0]<16;16,1>
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155 // q1 = Cur MB Y row 1 = r[Q_AddrReg, 16]<16;16,1>
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156 // q2 = Cur MB Y row 2 = r[Q_AddrReg, 32]<16;16,1>
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157 // q3 = Cur MB Y row 3 = r[Q_AddrReg, 48]<16;16,1>
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158 mov (1) P_AddrReg:w PREV_MB_Y_BASE:w { NoDDClr }
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159 mov (1) Q_AddrReg:w SRC_MB_Y_BASE:w { NoDDChk }
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161 // Get (alpha >> 2) + 2
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162 shr (16) Mbaff_ALPHA2(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub 2:w // alpha >> 2
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163 add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2
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165 CALL(FILTER_Y_MBAFF, 1)
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167 ILDB_LABEL(BYPASS_EXT_LEFT_EDGE_Y):
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168 //------------------------------------------------------------------
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171 // Same alpha, alpha2, beta and MaskB for all internal edges
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173 // Get (alpha >> 2) + 2
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174 shr (16) Mbaff_ALPHA2(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Y]<0;1,0>:ub 2:w // alpha >> 2
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176 // alpha = bAlphaInternal_Y
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177 // beta = bBetaInternal_Y
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178 mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Y]<0;1,0>:ub
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179 mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaInternal_Y]<0;1,0>:ub
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181 mov (1) MaskB:uw 0:w // Set MaskB = 0 for all 3 edges, so it always uses bS < 4 algorithm.
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183 add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2
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185 //---------- Deblock Y internal left edge (V1) ----------
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187 // Bypass deblocking if FilterInternal4x4EdgesFlag = 0
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188 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag
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189 // (f0.0) jmpi BYPASS_V1_Y
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191 // p3 = Cur MB Y row 0 = r[P_AddrReg, 0]<16;16,1>
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192 // p2 = Cur MB Y row 1 = r[P_AddrReg, 16]<16;16,1>
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193 // p1 = Cur MB Y row 2 = r[P_AddrReg, 32]<16;16,1>
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194 // p0 = Cur MB Y row 3 = r[P_AddrReg, 48]<16;16,1>
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195 // q0 = Cur MB Y row 4 = r[Q_AddrReg, 0]<16;16,1>
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196 // q1 = Cur MB Y row 5 = r[Q_AddrReg, 16]<16;16,1>
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197 // q2 = Cur MB Y row 6 = r[Q_AddrReg, 32]<16;16,1>
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198 // q3 = Cur MB Y row 7 = r[Q_AddrReg, 48]<16;16,1>
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199 mov (1) P_AddrReg:w SRC_MB_Y_BASE:w { NoDDClr }
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200 mov (1) Q_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk }
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202 mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]:uw
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204 // tc0 has bTc0_v31_Y + bTc0_v21_Y + bTc0_v11_Y + bTc0_v01_Y
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205 mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v01_Y]<1;4,0>:ub
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207 // CALL(FILTER_Y_MBAFF, 1)
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208 PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1)
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211 //------------------------------------------------------------------
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214 //---------- Deblock Y internal mid vert edge (V2) ----------
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216 // Bypass deblocking if FilterInternal8x8EdgesFlag = 0
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217 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal8x8EdgesFlag:w // Check for FilterInternal4x4EdgesFlag
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218 // (f0.0) jmpi BYPASS_V2_Y
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220 // p3 = Cur MB Y row 4 = r[P_AddrReg, 0]<16;16,1>
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221 // p2 = Cur MB Y row 5 = r[P_AddrReg, 16]<16;16,1>
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222 // p1 = Cur MB Y row 6 = r[P_AddrReg, 32]<16;16,1>
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223 // p0 = Cur MB Y row 7 = r[P_AddrReg, 48]<16;16,1>
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224 // q0 = Cur MB Y row 8 = r[Q_AddrReg, 0]<16;16,1>
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225 // q1 = Cur MB Y row 9 = r[Q_AddrReg, 16]<16;16,1>
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226 // q2 = Cur MB Y row 10 = r[Q_AddrReg, 32]<16;16,1>
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227 // q3 = Cur MB Y row 11 = r[Q_AddrReg, 48]<16;16,1>
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228 mov (1) P_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr }
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229 mov (1) Q_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk }
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231 mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntMidVert]:uw
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233 // tc0 has bTc0_v32_Y + bTc0_v22_Y + bTc0_v12_Y + bTc0_v02_Y
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234 mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v02_Y]<1;4,0>:ub
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236 // CALL(FILTER_Y_MBAFF, 1)
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237 PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1)
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240 //-----------------------------------------------
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243 //---------- Deblock Y interal right edge (V3) ----------
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245 // Bypass deblocking if FilterInternal4x4EdgesFlag = 0
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246 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag
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247 // (f0.0) jmpi BYPASS_V3_Y
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249 // p3 = Cur MB Y row 8 = r[P_AddrReg, 0]<16;16,1>
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250 // p2 = Cur MB Y row 9 = r[P_AddrReg, 16]<16;16,1>
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251 // p1 = Cur MB Y row 10 = r[P_AddrReg, 32]<16;16,1>
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252 // p0 = Cur MB Y row 11 = r[P_AddrReg, 48]<16;16,1>
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253 // q0 = Cur MB Y row 12 = r[Q_AddrReg, 0]<16;16,1>
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254 // q1 = Cur MB Y row 13 = r[Q_AddrReg, 16]<16;16,1>
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255 // q2 = Cur MB Y row 14 = r[Q_AddrReg, 32]<16;16,1>
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256 // q3 = Cur MB Y row 15 = r[Q_AddrReg, 48]<16;16,1>
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257 mov (1) P_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr }
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258 mov (1) Q_AddrReg:w 12*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk }
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260 mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntRightVert]:uw
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262 // tc0 has bTc0_v33_Y + bTc0_v23_Y + bTc0_v13_Y + bTc0_v03_Y
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263 mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v03_Y]<1;4,0>:ub
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265 // CALL(FILTER_Y_MBAFF, 1)
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266 PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1)
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269 //-----------------------------------------------
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