2 * Copyright © <2010>, Intel Corporation.
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4 * This program is licensed under the terms and conditions of the
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5 * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
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6 * http://www.opensource.org/licenses/eclipse-1.0.php.
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9 ////////// AVC LDB filter vertical UV ///////////////////////////////////////////////////////
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11 // This filter code prepares the src data and control data for ILDB filtering on all vertical edges of UV.
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13 // It sssumes the data for vertical de-blocking is already transposed.
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17 // +-------+-------+
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21 // +-------+-------+
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25 // +-------+-------+
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30 /////////////////////////////////////////////////////////////////////////////
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32 #if defined(_DEBUG)
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33 mov (1) EntrySignatureC:w 0xBBBC:w
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36 //=============== Chroma deblocking ================
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38 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterLeftMbEdgeFlag:w // Check for FilterLeftMbEdgeFlag
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39 // (f0.0) jmpi BYPASS_EXT_LEFT_EDGE_UV
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41 // Get vertical border edge control data.
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43 // Get Luma maskA and maskB
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44 shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]<0;1,0>:uw RRampW(0)
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45 shr (16) TempRow1(0)<1> r[ECM_AddrReg, wEdgeCntlMapB_ExtLeftVert0]<0;1,0>:uw RRampW(0)
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47 (f0.0) jmpi ILDB_LABEL(BYPASS_EXT_LEFT_EDGE_UV)
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49 // Extract UV MaskA and MaskB from every other bit of Y masks
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50 and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w
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51 and.nz.f0.1 (8) null:w TempRow1(0)<16;8,2> 1:w
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53 //---------- Deblock U external edge ----------
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54 // p1 = Prev MB U row 0
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55 // p0 = Prev MB U row 1
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56 // q0 = Cur MB U row 0
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57 // q1 = Cur MB U row 1
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58 mov (1) P_AddrReg:w PREV_MB_U_BASE:w { NoDDClr }
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59 mov (1) Q_AddrReg:w SRC_MB_U_BASE:w { NoDDChk }
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61 // alpha = bAlphaLeft0_Cb, beta = bBetaLeft0_Cb
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62 mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaLeft0_Cb]<2;2,1>:ub { NoDDClr }
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63 // tc0 has bTc0_v30_0_Cb + bTc0_v20_0_Cb + bTc0_v10_0_Cb + bTc0_v00_0_Cb
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64 mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v00_0_Cb]<4;4,1>:ub { NoDDChk }
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66 // UV MaskA and MaskB
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67 mov (2) MaskA<1>:uw f0.0<2;2,1>:uw
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71 //---------- Deblock V external edge ----------
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72 // p1 = Prev MB V row 0
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73 // p0 = Prev MB V row 1
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74 // q0 = Cur MB V row 0
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75 // q1 = Cur MB V row 1
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76 mov (1) P_AddrReg:w PREV_MB_V_BASE:w { NoDDClr }
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77 mov (1) Q_AddrReg:w SRC_MB_V_BASE:w { NoDDChk }
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79 // for vert edge: alpha = bAlphaLeft0_Cr, beta = bBetaLeft0_Cr
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80 mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaLeft0_Cr]<2;2,1>:ub { NoDDClr }
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82 // tc0 has bTc0_v30_0_Cr + bTc0_v20_0_Cr + bTc0_v10_0_Cr + bTc0_v00_0_Cr
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83 mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v00_0_Cr]<4;4,1>:ub { NoDDChk }
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85 // UV MaskA and MaskB
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86 mov (2) f0.0<1>:uw MaskA<2;2,1>:uw
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91 ILDB_LABEL(BYPASS_EXT_LEFT_EDGE_UV):
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92 // Set EdgeCntlMap2 = 0, so it always uses bS < 4 algorithm.
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93 // Same alpha and beta for all internal vert and horiz edges
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96 //***** Need to take every other bit to form U or V maskA
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97 // Get Luma maskA and maskB
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98 shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMap_IntMidVert]<0;1,0>:uw RRampW(0)
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100 //---------- Deblock U internal edge ----------
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101 // p1 = Cur MB U row 2
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102 // p0 = Cur MB U row 3
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103 // q0 = Cur MB U row 4
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104 // q1 = Cur MB U row 5
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105 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDClr }
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106 mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDChk }
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108 // alpha = bAlphaInternal_Cb, beta = bBetaInternal_Cb
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109 mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaInternal_Cb]<2;2,1>:ub { NoDDClr }
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111 // tc0 has bTc0_v32_Cb + bTc0_v22_Cb + bTc0_v12_Cb + bTc0_v02_Cb
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112 mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v02_Cb]<4;4,1>:ub { NoDDChk }
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114 // Extract UV MaskA and MaskB from every other bit of Y masks
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115 and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w
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117 // UV MaskA and MaskB
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118 mov (1) f0.1:uw 0:w
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119 mov (1) MaskB:uw 0:w { NoDDClr }
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120 mov (1) MaskA:uw f0.0:uw { NoDDChk }
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122 CALL(FILTER_UV, 1)
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125 //---------- Deblock V internal edge ----------
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126 // P1 = Cur MB V row 2
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127 // P0 = Cur MB V row 3
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128 // Q0 = Cur MB V row 4
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129 // Q1 = Cur MB V row 5
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130 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDClr }
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131 mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDChk }
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133 // alpha = bAlphaInternal_Cr, beta = bBetaInternal_Cr
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134 mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaInternal_Cr]<2;2,1>:ub { NoDDClr }
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136 // tc0 has bTc0_v32_Cr + bTc0_v22_Cr + bTc0_v12_Cr + bTc0_v02_Cr
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137 mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v02_Cr]<4;4,1>:ub { NoDDChk }
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139 // UV MaskA and MaskB
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140 mov (2) f0.0<1>:uw MaskA<2;2,1>:uw
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142 CALL(FILTER_UV, 1)
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145 //BYPASS_4x4_DEBLOCK_V:
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