i965_drv_video/shaders/h264/ildb/AVC_ILDB_Root_Mbaff_UV.asm

   1 /*\r
   2  * Copyright © <2010>, Intel Corporation.\r
   3  *\r
   4  * This program is licensed under the terms and conditions of the\r
   5  * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at\r
   6  * http://www.opensource.org/licenses/eclipse-1.0.php.\r
   7  *\r
   8  */\r
   9 /////////////////////////////////////////////////////////////////////////////////////\r
  10 // Kernel name: AVC_ILDB_Root_Mbaff.asm\r
  11 //\r
  12 //  Root kernel serves as a scheduler for child threads.\r
  13 //\r
  14 //\r
  15 //      ***** Note *****\r
  16 //      Initial design bundle MB pair for each thread, and share AVC_ILDB_MB_Dep_Check.asm\r
  17 //      with non mbaff kernels.\r
  18 //\r
  19 //      Optimization will be done later, putting top and bottom MBs on separate threads.\r
  20 //\r
  21 //\r
  22 /////////////////////////////////////////////////////////////////////////////////////\r
  23 //\r
  24 //  $Revision: 1 $\r
  25 //  $Date: 10/19/06 5:06p $\r
  26 //\r
  27 \r
  28 // ----------------------------------------------------\r
  29 //  AVC_ILDB_ROOT_MBAFF_UV\r
  30 // ----------------------------------------------------\r
  31 #define AVC_ILDB\r
  32 \r
  33 .kernel AVC_ILDB_ROOT_MBAFF_UV\r
  34 #if defined(COMBINED_KERNEL)\r
  35 ILDB_LABEL(AVC_ILDB_ROOT_UV):\r
  36 #endif\r
  37 \r
  38 #include "setupVPKernel.asm"\r
  39 #include "AVC_ILDB.inc"\r
  40 \r
  41 \r
  42 #if defined(_DEBUG) \r
  43 \r
  44 /////////////////////////////////////////////////////////////////////////////////////\r
  45 // Init URB space for running on RTL.  It satisfies reading an unwritten URB entries.  \r
  46 // Will remove it for production release.\r
  47 \r
  48 \r
  49 //mov (8) m1:ud                 0x11111111:ud\r
  50 //mov (8) m2:ud                 0x22222222:ud \r
  51 //mov (8) m3:ud                 0x33333333:ud\r
  52 //mov (8) m4:ud                 0x44444444:ud \r
  53 \r
  54 //mov (1)       Temp1_W:w       0:w\r
  55 \r
  56 //ILDB_INIT_URB:\r
  57 //mul (1)       URBOffset:w                             Temp1_W:w               4:w\r
  58 //shl (1) URBWriteMsgDescLow:uw         URBOffset:w             4:w             // Msg descriptor: URB write dest offset (9:4)\r
  59 //mov (1) URBWriteMsgDescHigh:uw        0x0650:uw                               // Msg descriptor: URB write 5 MRFs (m0 - m4)\r
  60 //#include "writeURB.asm"\r
  61 \r
  62 //add           (1)             Temp1_W:w       Temp1_W:w       1:w                             // Increase block count\r
  63 //cmp.l.f0.0 (1)        null            Temp1_W:w       MBsCntY:w               // Check the block count limit\r
  64 //(f0.0) jmpi           ILDB_INIT_URB                                                   // Loop back\r
  65 \r
  66 \r
  67 /////////////////////////////////////////////////////////////////////////////////////\r
  68 \r
  69 \r
  70 mov             (1)             EntrySignature:w                        0xEFF0:w\r
  71 \r
  72 #endif\r
  73 //----------------------------------------------------------------------------------------------------------------\r
  74 \r
  75 // Set global variable\r
  76 mov (32)        ChildParam:uw                   0:uw                                                            // Reset local variables\r
  77 //mul   (1)             TotalBlocks:w                   MBsCntX:w               MBsCntY:w                       // Total # of MB pairs\r
  78 //add   (1)             GatewayApertureE:w              MBsCntY:w               GatewayApertureB:w      // Aperture End = aperture Head + BlockCntY\r
  79 \r
  80 \r
  81 // 2 URB entries for Y:\r
  82 // Entry 0 - Child thread R0Hdr\r
  83 // Entry 1 - input parameter to child kernel (child r1)\r
  84 \r
  85 #define         URB_ENTRIES_PER_MB      2\r
  86 \r
  87 // URB_ENTRIES_PER_MB in differnt form, the final desired format is (URB_ENTRIES_PER_MB-1) << 10\r
  88 mov (1) URB_EntriesPerMB_2:w            URB_ENTRIES_PER_MB-1:w\r
  89 shl (1) URB_EntriesPerMB_2:w            URB_EntriesPerMB_2:w    10:w\r
  90 \r
  91 #define         CHROMA_ROOT                                                                                                             // Compiling flag for chroma only\r
  92 //mul (1)               URBOffsetUVBase:w               MBsCntY:w               URB_ENTRIES_PER_MB:w    // Right after Y entries\r
  93 \r
  94 // URB base for UV kernels\r
  95 #if defined(DEV_CL)     \r
  96         mov (1)         URBOffsetUVBase:w               240:w\r
  97 #else\r
  98         mov (1)         URBOffsetUVBase:w               320:w\r
  99 #endif\r
 100 \r
 101 \r
 102 mov     (1)             ChildThreadsID:uw               3:uw\r
 103 \r
 104 shr (1)         ThreadLimit:w           MaxThreads:w            1:w             // Initial luma thread limit to 50%\r
 105 mul     (1)             TotalBlocks:w           MBsCntX:w               MBsCntY:w       // MBs to be processed count down from TotalBlocks\r
 106 \r
 107 //***** Init CT_R0Hdr fields that are common to all threads *************************\r
 108 mov (8) CT_R0Hdr.0:ud                   r0.0<8;8,1>:ud                          // Init to root R0 header\r
 109 mov (1) CT_R0Hdr.7:ud                   r0.6:ud                                         // Copy Parent Thread Cnt; JJ did the change on 06/20/2006\r
 110 mov (1) CT_R0Hdr.31:ub                  0:w                                                     // Reset the highest byte\r
 111 mov (1) CT_R0Hdr.3:ud                   0x00000000       \r
 112 mov (1) CT_R0Hdr.6:uw                   sr0.0:uw                                        // sr0.0: state reg contains general thread states, e.g. EUID/TID.\r
 113 \r
 114 //***** Init ChildParam fields that are common to all threads ***********************\r
 115 mov (8)         ChildParam<1>:ud        RootParam<8;8,1>:ud             // Copy all root parameters\r
 116 mov (4)         CurCol<1>:w                     0:w                                             // Reset CurCol, CurRow\r
 117 add     (2)             LastCol<1>:w            MBsCntX<2;2,1>:w                -1:w    // Get LastCol and LastRow\r
 118 \r
 119 mov (1) URBWriteMsgDesc:ud              MSG_LEN(2)+URBWMSGDSC:ud\r
 120 \r
 121 //===================================================================================\r
 122 \r
 123 #include "AVC_ILDB_OpenGateway.asm"             // Open root thread gateway for receiving notification \r
 124 \r
 125 #include "AVC_ILDB_Dep_Check.asm"       // Check dependency and spawn all MBs\r
 126 \r
 127 //#include "AVC_ILDB_UpdateThrdLimit.asm"       // Update thread limit in luma root thread via gateway\r
 128 \r
 129 #include "AVC_ILDB_CloseGateway.asm"    // Close root thread gateway \r
 130 \r
 131 // Chroma root EOT = child send EOT : Request type = 1\r
 132         END_CHILD_THREAD\r
 133 \r
 134 #undef  CHROMA_ROOT\r
 135 \r
 136 #if !defined(COMBINED_KERNEL)           // For standalone kernel only\r
 137 .end_code\r
 138 \r
 139 .end_kernel\r
 140 #endif\r