2 * Header file for all AVC intra prediction kernels
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3 * Copyright © <2010>, Intel Corporation.
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5 * This program is licensed under the terms and conditions of the
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6 * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
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7 * http://www.opensource.org/licenses/eclipse-1.0.php.
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10 #if !defined(__INTRA_HEADER__) // Make sure this file is only included once
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11 #define __INTRA_HEADER__
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13 // Module name: intra_header.inc
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15 // Header file for all AVC intra prediction kernels
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17 // This header file defines everything that's specific to intra macroblock kernels
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20 // ----------- Various data buffers and pointers ------------
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22 // I_PCM data buffer
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24 #define I_PCM_BUF_Y 4
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25 #define I_PCM_BUF_UV 12
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27 #define REG_I_PCM_BUF_Y r4
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28 #define REG_I_PCM_BUF_UV r12
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30 .declare I_PCM_Y Base=REG_I_PCM_BUF_Y ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8-bit I_PCM Y data
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31 .declare I_PCM_UV Base=REG_I_PCM_BUF_UV ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8-bit I_PCM U/V data
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33 // Intra macroblock error data blocks
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35 #define ERRBUF 4 // Starting GRF index for error data
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36 #define REG_ERRBUF r4
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37 .declare MBBLOCKW Base=REG_ERRBUF ElementSize=2 SrcRegion=REGION(16,1) Type=w // For 16-bit inter MB
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38 .declare MBBLOCKD Base=REG_ERRBUF ElementSize=2 SrcRegion=REGION(16,1) Type=uw // For use in "send" command
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40 #define PERROR a0.2 // Pointer to macroblock error data
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41 #define PERROR1 a0.3 // Pointer to macroblock error data used by instruction compression
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42 #define PERROR_UD a0.1 // Pointer to macroblock error data in DWORD unit
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44 // Intra macroblock reference data
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46 #define REG_INTRA_REF_TOP r49 // Must be an odd numbered GRF register
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47 .declare INTRA_REF_TOP0 Base=REG_INTRA_REF_TOP ElementSize=1 SrcRegion=REGION(16,1) Type=ub
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48 .declare INTRA_REF_TOP Base=REG_INTRA_REF_TOP.4 ElementSize=1 SrcRegion=REGION(16,1) Type=ub
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49 // Actual top row reference data start at offset 4 in BYTE
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50 .declare INTRA_REF_TOP_W Base=REG_INTRA_REF_TOP.2 ElementSize=2 SrcRegion=REGION(16,1) Type=uw
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51 // Actual top row reference data start at offset 2 in WORD
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52 .declare INTRA_REF_TOP_D Base=REG_INTRA_REF_TOP ElementSize=4 DstRegion=<1> Type=ud // Only used in "send" instruction
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54 #define INTRA_REF_LEFT_ID 50
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55 #define REG_INTRA_REF_LEFT r50
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56 .declare INTRA_REF_LEFT0 Base=REG_INTRA_REF_LEFT ElementSize=1 SrcRegion=REGION(8,4) Type=ub
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57 .declare INTRA_REF_LEFT Base=REG_INTRA_REF_LEFT.3 ElementSize=1 SrcRegion=REGION(8,4) Type=ub
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58 // Actual left column reference data are located at offset 3 in BYTE
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59 .declare INTRA_REF_LEFT_UV Base=REG_INTRA_REF_LEFT.2 ElementSize=1 SrcRegion=REGION(8,4) Type=ub
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60 // Actual left column U/V reference data are located at offset 2 in BYTE
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61 .declare INTRA_REF_LEFT_W Base=REG_INTRA_REF_LEFT.1 ElementSize=2 SrcRegion=REGION(8,2) Type=uw
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62 // Actual left column reference data are located at offset 1 in WORD
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63 .declare INTRA_REF_LEFT_D Base=REG_INTRA_REF_LEFT ElementSize=4 DstRegion=<1> Type=ud // Only used in "send" instruction
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65 #define PREF_LEFT a0.4 // Pointer to left reference data
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66 #define PREF_LEFT_UD a0.2 // Pointer in DWORD to left reference data
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68 #define INTRA_TEMP_0 52
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69 #define INTRA_TEMP_1 53
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70 #define INTRA_TEMP_2 54
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71 #define INTRA_TEMP_3 55
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72 #define INTRA_TEMP_4 56
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73 #define INTRA_TEMP_5 57
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74 #define INTRA_TEMP_6 58
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76 #define REG_INTRA_TEMP_0 r52
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77 #define REG_INTRA_TEMP_1 r53
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78 #define REG_INTRA_TEMP_2 r54
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79 #define REG_INTRA_TEMP_3 r55
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80 #define REG_INTRA_TEMP_4 r56
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81 #define REG_INTRA_TEMP_5 r57
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82 #define REG_INTRA_TEMP_6 r58
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83 #define REG_INTRA_TEMP_7 r59
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84 #define REG_INTRA_TEMP_8 r60
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86 // Destination registers for write commit
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87 #define REG_WRITE_COMMIT_Y r60.0
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88 #define REG_WRITE_COMMIT_UV r61.0
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90 // ----------- Various data buffers and pointers ------------
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91 // R32 - R47 for predicted picture buffer (for both Y and U/V blocks)
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93 #define PREDBUF 32 // Starting GRF index for predicted buffer
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94 #define REG_PREDBUF r32
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96 .declare PRED_Y Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted Y picture
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97 .declare PRED_YW Base=REG_PREDBUF ElementSize=2 SrcRegion=REGION(16,1) Type=uw // Predicted Y picture stored in WORD
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98 .declare PRED_Y_FM Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted Y picture frame
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99 .declare PRED_Y_TF Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted Y picture Top field
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101 .declare PRED_UV Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted U/V picture
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102 .declare PRED_UVW Base=REG_PREDBUF ElementSize=2 SrcRegion=REGION(16,1) Type=uw // Predicted U/V picture stored in WORD
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103 .declare PRED_UV_FM Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted U/V picture frame
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104 .declare PRED_UV_TF Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted U/V picture top field
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105 .declare PRED_UV_BF Base=REG_PREDBUF.16 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted U/V picture bottom field
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107 // The same region will also be used as finally decoded Y blocks shared with U/V blocks
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110 #define REG_DECBUF r32
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111 .declare DEC_Y Base=REG_DECBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Decoded Y picture
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112 .declare DEC_UV Base=REG_DECBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Decoded U/V P-/B-picture
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113 .declare DEC_UD Base=REG_DECBUF ElementSize=4 SrcRegion=REGION(8,1) Type=ud // Decoded buffer in UD type
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115 // Reference buffer for intra_NxN prediction
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117 #define PRED_MODE REG_INTRA_TEMP_0
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118 .declare REF_TOP0 Base=REG_INTRA_TEMP_5 ElementSize=1 SrcRegion=REGION(16,1) Type=ub
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119 .declare REF_TOP Base=REG_INTRA_TEMP_5.4 ElementSize=1 SrcRegion=REGION(16,1) Type=ub
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120 // Actual top reference data start from offset 3,i.e. p[-1,-1]
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121 .declare REF_TOP_W Base=REG_INTRA_TEMP_5 ElementSize=2 SrcRegion=REGION(16,1) Type=uw
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122 .declare REF_TOP_D Base=REG_INTRA_TEMP_5 ElementSize=4 SrcRegion=REGION(8,1) Type=ud
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123 .declare REF_LEFT Base=REG_INTRA_TEMP_6 ElementSize=1 SrcRegion=REGION(16,1) Type=ub
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124 .declare REF_LEFT_D Base=REG_INTRA_TEMP_6 ElementSize=4 SrcRegion=REGION(8,1) Type=ud
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126 // For intra prediction plane mode
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128 .declare H1 Base=REG_INTRA_TEMP_0 ElementSize=2 SrcRegion=REGION(8,1) Type=w // Make sure it's an even GRF
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129 .declare H2 Base=REG_INTRA_TEMP_0.8 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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130 .declare V1 Base=REG_INTRA_TEMP_1 ElementSize=2 SrcRegion=REGION(8,1) Type=w // Make sure it's the following odd GRF
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131 .declare V2 Base=REG_INTRA_TEMP_1.8 ElementSize=2 SrcRegion=REGION(8,1) Type=w
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133 .declare CP Base=REG_INTRA_TEMP_2 ElementSize=2 SrcRegion=REGION(16,1) Type=w
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135 #define PINTRAPRED_Y a0.7 // Used as luma intra prediction mode pointer
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136 #define PINTRAPRED_UV a0.7 // Used as chroma intra prediction mode pointer
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137 #define PINTRA4X4_Y a0.4 // Used as luma intra_4x4 prediction mode pointer
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139 #define PBWDCOPY_4 a0.4 // a0.4 - a0.7 used in intra_4x4 prediction for moving data backward
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140 #define PBWDCOPY_8 a0.6 // a0.6 - a0.7 used in intra_8x8 prediction for moving data backward
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142 // For Intra_4x4 prediction mode
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144 .declare INTRA_4X4_MODE Base=REG_INTRA_TEMP_1 ElementSize=4 SrcRegion=REGION(1,0) DstRegion=<1> Type=d // Actually only need 1 DWORD
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146 // ----------- Intra CURBE constants ------------
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148 #define REG_CURBE1 r1
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149 #define REG_CURBE2 r2
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150 #define INTRA_4X4_OFFSET 1*GRFWIB // 9 Bytes
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151 #define INTRA_8X8_OFFSET 1*GRFWIB+12 // 9 Bytes starting sub-register r1.3:ud
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152 #define INTRA_16X16_OFFSET 1*GRFWIB+24 // 4 Bytes starting sub-register r1.6:ud
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153 #define INTRA_CHROMA_OFFSET 1*GRFWIB+28 // 4 Bytes starting sub-register r1.7:ud
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155 #define TOP_REF_OFFSET REG_CURBE1.10 // r1.5:w
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157 // Constants used in plane intra prediction mode
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158 #define XY_3 REG_CURBE2.4 // Stored BYTE constants x-3 for x=0...7, i.e. -3,-2,...3,4 for U/V, need duplicate to every other byte
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159 #define XY_3_1 REG_CURBE2.5 // Stored BYTE constants x-3 for x=0...7, i.e. -3,-2,...3,4 for 2nd instruction in {Comp}
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160 #define XY_7 REG_CURBE2.0 // Stored BYTE constants x-7 for x=0...15, i.e. -7,-6,...7,8 for Y
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161 #define XY_7_1 REG_CURBE2.1 // Stored BYTE constants x-7 for x=0...15, i.e. -7,-6,...7,8 for 2nd instruction in {Comp}
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163 #define INV_SHIFT REG_CURBE2.16
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165 #define INV_TRANS4 REG_CURBE2.20 // For reverse data transfer for intra_4x4 (0x00020406)
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166 #define INV_TRANS48 REG_CURBE2.22 // For reverse data transfer for intra_4x4 (0x0002)
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167 #define INV_TRANS8 REG_CURBE1.22 // For reverse data transfer for intra_8x8 (0x0001)
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169 #define INTRA_MODE REG_CURBE2.24 // Offset to intra_Pred_4x4_Y from each sub-block
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171 // ----------- In-line parameters ------------
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173 #define REG_INLINE r3
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175 #define INLINE_DW0 REG_INLINE.0<0;1,0>:ud
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176 #define INLINE_DW1 REG_INLINE.1<0;1,0>:ud
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177 #define INLINE_DW2 REG_INLINE.2<0;1,0>:ud
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178 #define INLINE_DW3 REG_INLINE.3<0;1,0>:ud
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179 #define INLINE_DW4 REG_INLINE.4<0;1,0>:ud
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180 #define INLINE_DW5 REG_INLINE.5<0;1,0>:ud
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181 #define INLINE_DW6 REG_INLINE.6<0;1,0>:ud
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182 #define INLINE_DW7 REG_INLINE.7<0;1,0>:ud
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184 // Intra macroblock in-line data
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187 #define REG_MBAFF_FIELD REG_INLINE.1 // :uw, can be added directly to lower-word of MSGDSC
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188 #define MBAFF_FIELD BIT26+BIT25 // Bits 26:25 - MBAFF field macroblock flag
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189 // 00 = Current macroblock is not an MBAFF field macroblock
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190 // 11 = Current macroblock is an MBAFF field macroblock
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192 #define REG_FIELD_PARITY INLINE_DW0
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193 #define FIELD_PARITY BIT24 // Bit 24 - Macroblock field parity flag
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194 // 0 = Current field is a top field
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195 // 1 = Current field is a bottom field
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197 #define REG_FIELD_MACROBLOCK_FLAG INLINE_DW0
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198 #define FIELD_MACROBLOCK_FLAG BIT14 // Bit 14 - Field macroblock flag
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199 // 0 = Current macroblock is not a field macroblock
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200 // 1 = Current macroblock is a field macroblock
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201 #define REG_MACROBLOCK_TYPE INLINE_DW0
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202 #define MACROBLOCK_TYPE BIT12+BIT11+BIT10+BIT9+BIT8 // Bit 12:8 - Intra macroblock flag
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204 #define REG_CHROMA_FORMAT_IDC INLINE_DW0
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205 #define CHROMA_FORMAT_IDC BIT3+BIT2 // Bit 3:2 - Chroma format
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206 // 00 = Luma only (Monochrome)
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210 #define REG_MBAFF_PIC INLINE_DW0
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211 #define MBAFF_PIC BIT1 // Bit 1 - MBAFF Frame picture
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212 // 0 = Not an MBAFF frame picture
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213 // 1 = An MBAFF frame picture
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214 #define REG_INTRA_PRED_8X8_BLK2_AVAIL_FLAG INLINE_DW0
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215 #define INTRA_PRED_8X8_BLK2_AVAIL_FLAG BIT4 // Bit 4: Pixel available for block 2 in an intra_8x8 MB.
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218 #define ORIX REG_INLINE.4 // :ub, H. origin of the macroblock in macroblock unit
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219 #define ORIY REG_INLINE.5 // :ub, V. origin of the macroblock in macroblock unit
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222 #define REG_CBPCYB REG_INLINE.9 // :ub, Coded block pattern
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223 #define REG_CBPCY INLINE_DW2 // Bits 13:8 - Coded block pattern
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224 // reflect Y0, Y1, Y2, Y3, Cb4, Cr5
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231 #define CBP_MASK 0x3F00:ud // Bit mask for all CBP bits
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232 #define CBP_Y_MASK 0x3C00:ud // Bit mask for CBP Y bits
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233 #define CBP_UV_MASK 0x0300:ud // Bit mask for CBP U/V bits
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235 #define CBP_Y0_MASK BIT13:ud // Bit mask for CBP Y0 bit
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236 #define CBP_Y1_MASK BIT12:ud // Bit mask for CBP Y1 bit
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237 #define CBP_Y2_MASK BIT11:ud // Bit mask for CBP Y2 bit
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238 #define CBP_Y3_MASK BIT10:ud // Bit mask for CBP Y3 bit
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239 #define CBP_U_MASK BIT9:ud // Bit mask for CBP U bit
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240 #define CBP_V_MASK BIT8:ud // Bit mask for CBP V bit
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243 #define REG_INTRA_CHROMA_PRED_MODE REG_INLINE.12 // :ub - Intra chroma prediction mode
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244 #define INTRA_CHROMA_PRED_MODE BIT7+BIT6 // Bit 7:6 - Intra chroma prediction mode
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245 // 00 = Intra DC prediction
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246 // 01 = Intra horizontal prediction
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247 // 10 = Intra vertical prediction
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248 // 11 = Intra plane prediction
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249 #define INTRA_CHROMA_PRED_MODE_SHIFT 6 // Intra chroma prediction mode shift
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251 #define REG_INTRA_PRED_AVAIL_FLAG INLINE_DW3
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252 #define INTRA_PRED_AVAIL_FLAG BIT4+BIT3+BIT2+BIT1+BIT0 // Bits 4:0 - Intra prediction available flag
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253 // Bit 0: Macroblock A (the left neighbor) entire or top half
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254 // Bit 1: Macroblock B (the upper neighbor)
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255 // Bit 2: Macroblock C (the above-right neighbor)
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256 // Bit 3: Macroblock D (the above-left neighbor)
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257 // Bit 4: Macroblock A (the left neighbor) bottom half
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258 // Each bit is defined below
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259 // 0 = The macroblock is not available for intra prediction
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260 // 1 = The macroblock is available for intra prediction
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261 #define INTRA_PRED_LEFT_TH_AVAIL_FLAG BIT0 // Bit 0: Macroblock A (the left neighbor) entire or top half
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262 #define INTRA_PRED_UP_AVAIL_FLAG BIT1 // Bit 1: Macroblock B (the upper neighbor)
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263 #define INTRA_PRED_UP_RIGHT_AVAIL_FLAG BIT2 // Bit 2: Macroblock C (the above-right neighbor)
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264 #define INTRA_PRED_UP_LEFT_AVAIL_FLAG BIT3 // Bit 3: Macroblock D (the above-left neighbor)
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265 #define INTRA_PRED_LEFT_BH_AVAIL_FLAG BIT4 // Bit 4: Macroblock A (the left neighbor) bottom half
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266 //#define INTRA_PRED_8X8_BLK2_AVAIL_FLAG BIT5 // Bit 5: Pixel available for block 2 in an intra_8x8 MB.
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267 #define REG_INTRA_PRED_AVAIL_FLAG_BYTE REG_INLINE.12 // Byte location of Intra_Pred_Avail_Flag
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268 #define REG_INTRA_PRED_AVAIL_FLAG_WORD REG_INLINE.6 // Word location of Intra_Pred_Avail_Flag
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271 .declare INTRA_PRED_MODE Base=REG_INLINE.16 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Intra prediction mode
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273 // End of intra_header.inc
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275 #endif // !defined(__INTRA_HEADER__)
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