2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Wang Zhenyu <zhenyu.z.wang@intel.com>
25 * Keith Packard <keithp@keithp.com>
33 define(`dst_x_uw', `g1.8<2,4,0>UW')
34 define(`dst_y_uw', `g1.10<2,4,0>UW')
35 define(`screen_x0', `g1.0<0,1,0>F')
36 define(`screen_y0', `g1.4<0,1,0>F')
39 define(`interleaved_uv', `g2.0<0,1,0>UW')
41 /* Source transformation parameters */
42 define(`src_du_dx', `g3.0<0,1,0>F')
43 define(`src_du_dy', `g3.4<0,1,0>F')
44 define(`src_uo', `g3.12<0,1,0>F')
45 define(`src_dv_dx', `g3.16<0,1,0>F')
46 define(`src_dv_dy', `g3.20<0,1,0>F')
47 define(`src_vo', `g3.28<0,1,0>F')
48 define(`src_dw_dx', `g4.0<0,1,0>F')
49 define(`src_dw_dy', `g4.4<0,1,0>F')
50 define(`src_wo', `g4.12<0,1,0>F')
52 define(`mask_du_dx', `g5.0<0,1,0>F')
53 define(`mask_du_dy', `g5.4<0,1,0>F')
54 define(`mask_uo', `g5.12<0,1,0>F')
55 define(`mask_dv_dx', `g5.16<0,1,0>F')
56 define(`mask_dv_dy', `g5.20<0,1,0>F')
57 define(`mask_vo', `g5.28<0,1,0>F')
58 define(`mask_dw_dx', `g6.0<0,1,0>F')
59 define(`mask_dw_dy', `g6.4<0,1,0>F')
60 define(`mask_wo', `g6.12<0,1,0>F')
63 * Local variables. Pairs must be aligned on even reg boundry
66 /* this holds the X dest coordinates */
68 define(`dst_x_0', `dst_x')
69 define(`dst_x_1', `g9')
71 /* this holds the Y dest coordinates */
72 define(`dst_y', `g10')
73 define(`dst_y_0', `dst_y')
74 define(`dst_y_1', `g11')
76 /* When computing x * dn/dx, use this */
77 define(`temp_x', `g30')
78 define(`temp_x_0', `temp_x')
79 define(`temp_x_1', `g31')
81 /* When computing y * dn/dy, use this */
82 define(`temp_y', `g28')
83 define(`temp_y_0', temp_y)
84 define(`temp_y_1', `g29')
86 /* when loading x/y, use these to hold them in UW format */
87 define(`temp_x_uw', temp_x)
88 define(`temp_y_uw', temp_y)
90 /* compute source and mask u/v to this pair to send to sampler */
91 define(`src_msg', `m1')
92 define(`src_msg_ind',`1')
95 define(`src_w', `g12')
96 define(`src_w_0', `src_w')
97 define(`src_w_1', `g13')
99 define(`mask_msg', `m7')
100 define(`mask_msg_ind',`7')
101 define(`mask_u', `m8')
102 define(`mask_v', `m10')
103 define(`mask_w', `src_w')
104 define(`mask_w_0', `src_w_0')
105 define(`mask_w_1', `src_w_1')
107 /* sample src to these registers */
108 define(`src_sample_base', `g14')
110 define(`src_sample_r', `g14')
111 define(`src_sample_r_01', `g14')
112 define(`src_sample_r_23', `g15')
114 define(`src_sample_g', `g16')
115 define(`src_sample_g_01', `g16')
116 define(`src_sample_g_23', `g17')
118 define(`src_sample_b', `g18')
119 define(`src_sample_b_01', `g18')
120 define(`src_sample_b_23', `g19')
122 define(`src_sample_a', `g20')
123 define(`src_sample_a_01', `g20')
124 define(`src_sample_a_23', `g21')
126 /* sample mask to these registers */
127 define(`mask_sample_base', `g22')
129 define(`mask_sample_r', `g22')
130 define(`mask_sample_r_01', `g22')
131 define(`mask_sample_r_23', `g23')
133 define(`mask_sample_g', `g24')
134 define(`mask_sample_g_01', `g24')
135 define(`mask_sample_g_23', `g25')
137 define(`mask_sample_b', `g26')
138 define(`mask_sample_b_01', `g26')
139 define(`mask_sample_b_23', `g27')
141 define(`mask_sample_a', `g28')
142 define(`mask_sample_a_01', `g28')
143 define(`mask_sample_a_23', `g29')
145 /* data port SIMD16 send registers */
147 define(`data_port_msg_0', `m0')
148 define(`data_port_msg_0_ind', `0')
149 define(`data_port_msg_1', `m1')
150 define(`data_port_r_01', `m2')
151 define(`data_port_g_01', `m3')
152 define(`data_port_b_01', `m4')
153 define(`data_port_a_01', `m5')
155 define(`data_port_r_23', `m6')
156 define(`data_port_g_23', `m7')
157 define(`data_port_b_23', `m8')
158 define(`data_port_a_23', `m9')