2 ; MSP430fr2433 minimal declarations for Fast FORTH usage
6 DEVICE = "MSP430FR2476"
8 HMPY ; hardware multiplier
9 FLL ; Frequency Locked Loop CLOCK
10 ; ----------------------------------------------
11 ; MSP430FR2476 MEMORY MAP
12 ; ----------------------------------------------
13 ; 0000-0005 = reserved
15 ; 0020-0FFF = peripherals (4 KB)
16 ; 1000-17FF = ROM bootstrap loader BSL1 (2k)
17 ; 1800-19FF = info B (FRAM 512 B)
18 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
20 ; 2000-3FFF = RAM (8 KB)
22 ; 8000-17FFF = code memory (FRAM 64 kB)
23 ; FF80-FFFF = interrupt vectors (FRAM 128 B)
24 ; C0000-C3FFF = CapTivate lib
25 ; FFC00-FFFFF = BSL2 (2k)
26 ; ----------------------------------------------
27 PAGESIZE .equ 512 ; MPU unit
28 ; ----------------------------------------------
30 ; ----------------------------------------------
31 BSL1 .equ 01000h ; to 17FFh
32 CapTivateLib .equ 0C0000h ; to 0C3FFFh
33 BSL2 .equ 0FFC00h ; to 0FFFFFh
34 ; ----------------------------------------------
36 ; ----------------------------------------------
37 TinyRAM .equ 00006h ; to 0001Fh
38 INFO_ORG .equ 01800h ; to 019FFh
40 TLV_ORG .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
42 ; ----------------------------------------------
44 ; ----------------------------------------------
45 RAM_ORG .equ 02000h ; to 3FFFh
47 ; ----------------------------------------------
49 ; ----------------------------------------------
50 MAIN_ORG .equ 08000h ; Code space start
51 ; ----------------------------------------------
52 ; Interrupt Vectors and signatures - MSP430FR2355
53 ; ----------------------------------------------
54 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
55 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
56 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked
57 BSL_SIG1 .equ 0FF84h ;
58 BSL_SIG2 .equ 0FF86h ;
59 JTAG_PASSWORD .equ 0FF88h ; 256 bits
60 BSL_PASSWORD .equ 0FFE0h ; 256 bits
61 BSL_I2C_ADRE .equ 0FFA0h ;
62 I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address
63 I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address
64 I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address
65 I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address
66 VECT_ORG .equ 0FF8Ch ; FFDA-FFFF
68 ; ----------------------------------------------
70 ; ----------------------------------------------
71 ; Interrupt Vectors and signatures - MSP430FR243x
72 ; ----------------------------------------------
75 ;;Start of JTAG and BSL signatures
76 ; .word 0FFFFh ; JTAG signature 1
77 ; .word 0FFFFh ; JTAG signature 2
78 ; .word 0FFFFh ; BSL signature 1, 5555h to disable BSL
79 ; .word 0FFFFh ; BSL signature 2
81 ; .org INTVECT ; FFDA-FFFF 27 vectors + reset
83 ; .word reset ; 0FFC8h - CapTivate
84 ; .word reset ; 0FFCAh - eCOMP0
85 ; .word reset ; 0FFCCh - P6
86 ; .word reset ; 0FFCEh - P5
87 ; .word reset ; 0FFD0h - P4
88 ; .word reset ; 0FFD2h - P3
89 ; .word reset ; 0FFD4h - P2
90 ; .word reset ; 0FFD6h - P1
91 ; .word reset ; 0FFD8h - ADC10
92 ; .word reset ; 0FFDAh - eUSCI_B1
93 ; .word reset ; 0FFDCh - eUSCI_B0
94 ; .word reset ; 0FFDEh - eUSCI_A1
95 ; .word reset ; 0FFE0h - eUSCI_A0
96 ; .word reset ; 0FFE2h - WDT
97 ; .word reset ; 0FFE4h - RTC
98 ; .word reset ; 0FFE6h - TB0_x
99 ; .word reset ; 0FFE8h - TB0_0
100 ; .word reset ; 0FFEAh - TA3_x
101 ; .word reset ; 0FFECh - TA3_0
102 ; .word reset ; 0FFEEh - TA2_x
103 ; .word reset ; 0FFF0h - TA2_0
104 ; .word reset ; 0FFF2h - TA1_x
105 ; .word reset ; 0FFF4h - TA1_0
106 ; .word reset ; 0FFF6h - TA0_x
107 ; .word reset ; 0FFF8h - TA0_0
108 ; .word reset ; 0FFFAh - UserNMI
109 ; .word reset ; 0FFFCh - SysNMI
110 ; .word reset ; 0FFFEh - Reset
112 ; ----------------------------------------------------------------------
113 ; MSP430FR2476 Peripheral File Map
114 ; ----------------------------------------------------------------------
115 SFR_SFR .equ 0100h ; Special function
116 PMM_SFR .equ 0120h ; PMM
117 SYS_SFR .equ 0140h ; SYS
118 CS_SFR .equ 0180h ; Clock System
119 FRAM_SFR .equ 01A0h ; FRAM control
121 WDT_A_SFR .equ 01CCh ; Watchdog
122 PA_SFR .equ 0200h ; PORT1/2
123 PB_SFR .equ 0220h ; PORT3/4
124 PC_SFR .equ 0240h ; PORT5/6
132 eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
133 eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
134 eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
135 eUSCI_B1_SFR .equ 0580h ; eUSCI_B1
136 BACK_MEM_SFR .equ 0660h
137 ADC10_B_SFR .equ 0700h
140 ; ----------------------------------------------------------------------
141 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
142 ; ----------------------------------------------------------------------
144 SFRIFG1 .equ SFR_SFR + 2
145 SFRRPCR .equ SFR_SFR + 4
150 PM5CTL0 .equ PMM_SFR + 10h ; Power mode 5 control register 0
151 LOCKLPM5 .equ 1 ; bit position
153 ; ----------------------------------------------------------------------
154 ; POWER ON RESET SYS config
155 ; ----------------------------------------------------------------------
156 SYSCTL .equ SYS_SFR + 00h ; System control
157 SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area
158 SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control
159 SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0
160 SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1
161 SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0
162 SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1
163 SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator
164 SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator
165 SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator
166 SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator
167 SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0
168 SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1
169 SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2
175 ; ----------------------------------------------------------------------
176 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
177 ; ----------------------------------------------------------------------
179 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
181 ; WDTCTL Control Bits
183 WDTHOLD .equ 0080h ; WDT - Timer hold
184 WDTCNTCL .equ 0008h ; WDT timer counter clear
187 ; ----------------------------------------------------------------------
189 ; ----------------------------------------------------------------------
191 FRCTL0 .equ FRAM_SFR + 00h ; FRAM Controller Control 0
192 FRCTL0_H .equ FRAM_SFR + 01h ; FRAM Controller Control 0 high byte
194 ; ----------------------------------------------------------------------
195 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
196 ; ----------------------------------------------------------------------
198 CSCTL0 .equ CS_SFR + 00h ; Clock System Control Register 0
199 CSCTL1 .equ CS_SFR + 02h ; Clock System Control Register 1
200 CSCTL2 .equ CS_SFR + 04h ; Clock System Control Register 2
201 CSCTL3 .equ CS_SFR + 06h ; Clock System Control Register 3
202 CSCTL4 .equ CS_SFR + 08h ; Clock System Control Register 4
203 CSCTL5 .equ CS_SFR + 0Ah ; Clock System Control Register 5
204 CSCTL6 .equ CS_SFR + 0Ch ; Clock System Control Register 6
205 CSCTL7 .equ CS_SFR + 0Eh ; Clock System Control Register 7
206 CSCTL8 .equ CS_SFR + 10h ; Clock System Control Register 8
208 ; ----------------------------------------------------------------------
209 ; POWER ON RESET AND INITIALIZATION : PORT1/2
210 ; ----------------------------------------------------------------------
212 PAIN .equ PA_SFR + 00h ; Port A Input
213 PAOUT .equ PA_SFR + 02h ; Port A Output
214 PADIR .equ PA_SFR + 04h ; Port A Direction
215 PAREN .equ PA_SFR + 06h ; Port A Resistor Enable
216 PASEL0 .equ PA_SFR + 0Ah ; Port A Selection 0
217 PASEL1 .equ PA_SFR + 0Ch ; Port A Selection 1
218 PASELC .equ PA_SFR + 16h ; Port A Complement Selection
219 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
220 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
221 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt Flag
223 P1IN .equ PA_SFR + 00h ; Port 1 Input
224 P1OUT .equ PA_SFR + 02h ; Port 1 Output
225 P1DIR .equ PA_SFR + 04h ; Port 1 Direction
226 P1REN .equ PA_SFR + 06h ; Port 1 Resistor Enable
227 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 Selection 0
228 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 Selection 1
229 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
230 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
231 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
232 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt Flag
234 P2IN .equ PA_SFR + 01h ; Port 2 Input
235 P2OUT .equ PA_SFR + 03h ; Port 2 Output
236 P2DIR .equ PA_SFR + 05h ; Port 2 Direction
237 P2REN .equ PA_SFR + 07h ; Port 2 Resistor Enable
238 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 Selection 0
239 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 Selection 1
240 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
241 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
242 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag
243 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
245 ; ----------------------------------------------------------------------
246 ; POWER ON RESET AND INITIALIZATION : PORT3/4
247 ; ----------------------------------------------------------------------
249 PBIN .equ PB_SFR + 00h ; Port B Input
250 PBOUT .equ PB_SFR + 02h ; Port B Output 1/0 or pullup/pulldown resistor
251 PBDIR .equ PB_SFR + 04h ; Port B Direction
252 PBREN .equ PB_SFR + 06h ; Port B Resistor Enable
253 PBSEL0 .equ PB_SFR + 0Ah ; Port B Selection 0
254 PBSEL1 .equ PB_SFR + 0Ch ; Port B Selection 1
255 PBSELC .equ PB_SFR + 16h ; Port B Complement Selection
256 PBIES .equ PB_SFR + 18h ; Port B Interrupt Edge Select
257 PBIE .equ PB_SFR + 1Ah ; Port B Interrupt Enable
258 PBIFG .equ PB_SFR + 1Ch ; Port B Interrupt Flag
260 P3IN .equ PB_SFR + 00h ; Port 3 Input */
261 P3OUT .equ PB_SFR + 02h ; Port 3 Output
262 P3DIR .equ PB_SFR + 04h ; Port 3 Direction
263 P3REN .equ PB_SFR + 06h ; Port 3 Resistor Enable
264 P3SEL0 .equ PB_SFR + 0Ah ; Port 3 Selection 0
265 P3SEL1 .equ PB_SFR + 0Ch ; Port 3 Selection 1
266 P3SELC .equ PB_SFR + 16h ; Port 3 Complement Selection
267 P3IES .equ PB_SFR + 18h ; Port 3 Interrupt Edge Select
268 P3IE .equ PB_SFR + 1Ah ; Port 3 Interrupt Enable
269 P3IFG .equ PB_SFR + 1Ch ; Port 3 Interrupt Flag
270 P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word
272 P4IN .equ PB_SFR + 01h ; Port 4 Input */
273 P4OUT .equ PB_SFR + 03h ; Port 4 Output
274 P4DIR .equ PB_SFR + 05h ; Port 4 Direction
275 P4REN .equ PB_SFR + 07h ; Port 4 Resistor Enable
276 P4SEL0 .equ PB_SFR + 0Bh ; Port 4 Selection 0
277 P4SEL1 .equ PB_SFR + 0Dh ; Port 4 Selection 1
278 P4SELC .equ PB_SFR + 17h ; Port 4 Complement Selection
279 P4IES .equ PB_SFR + 19h ; Port 4 Interrupt Edge Select
280 P4IE .equ PB_SFR + 1Bh ; Port 4 Interrupt Enable
281 P4IFG .equ PB_SFR + 1Dh ; Port 4 Interrupt Flag
282 P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word
284 ; ----------------------------------------------------------------------
285 ; POWER ON RESET AND INITIALIZATION : PORT5/6
286 ; ----------------------------------------------------------------------
288 PCIN .equ PC_SFR + 00h ; Port C Input
289 PCOUT .equ PC_SFR + 02h ; Port C Output
290 PCDIR .equ PC_SFR + 04h ; Port C Direction
291 PCREN .equ PC_SFR + 06h ; Port C Resistor Enable
292 PCSEL0 .equ PC_SFR + 0Ah ; Port C Selection 0
293 PCSEL1 .equ PC_SFR + 0Ch ; Port C Selection 1
294 PCSELC .equ PC_SFR + 16h ; Port C Complement Selection
295 PCIES .equ PC_SFR + 18h ; Port C Interrupt Edge Select
296 PCIE .equ PC_SFR + 1Ah ; Port C Interrupt Enable
297 PCIFG .equ PC_SFR + 1Ch ; Port C Interrupt Flag
299 P5IN .equ PC_SFR + 00h ; Port 5 Input
300 P5OUT .equ PC_SFR + 02h ; Port 5 Output
301 P5DIR .equ PC_SFR + 04h ; Port 5 Direction
302 P5REN .equ PC_SFR + 06h ; Port 5 Resistor Enable
303 P5SEL0 .equ PC_SFR + 0Ah ; Port 5 Selection 0
304 P5SEL1 .equ PC_SFR + 0Ch ; Port 5 Selection 1
305 P5IV .equ PC_SFR + 0Eh ; Port 5 Interrupt Vector word
306 P5SELC .set PC_SFR + 16h ; Port 5 Complement Selection
307 P5IES .equ PC_SFR + 18h ; Port 5 Interrupt Edge Select
308 P5IE .equ PC_SFR + 1Ah ; Port 5 Interrupt Enable
309 P5IFG .equ PC_SFR + 1Ch ; Port 5 Interrupt Flag
311 P6IN .equ PC_SFR + 01h ; Port 6 Input
312 P6OUT .equ PC_SFR + 03h ; Port 6 Output
313 P6DIR .equ PC_SFR + 05h ; Port 6 Direction
314 P6REN .equ PC_SFR + 07h ; Port 6 Resistor Enable
315 P6SEL0 .equ PC_SFR + 0Bh ; Port 6 Selection 0
316 P6SEL1 .equ PC_SFR + 0Dh ; Port 6 Selection 1
317 P6SELC .set PC_SFR + 17h ; Port 6 Complement Selection
318 P6IES .equ PC_SFR + 19h ; Port 6 Interrupt Edge Select
319 P6IE .equ PC_SFR + 1Bh ; Port 6 Interrupt Enable
320 P6IFG .equ PC_SFR + 1Dh ; Port 6 Interrupt Flag
321 P6IV .equ PC_SFR + 1Eh ; Port 6 Interrupt Vector word
323 ; ----------------------------------------------------------------------
325 ; ----------------------------------------------------------------------
326 RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control
327 RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector
328 RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo
329 RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter
331 ; ----------------------------------------------------------------------
333 ; ----------------------------------------------------------------------
335 MPY .equ MPY_SFR + 00h ; Multiply16 Unsigned/Operand 1 */
336 MPYS .equ MPY_SFR + 02h ; Multiply16 signed/Operand 1
337 MAC .equ MPY_SFR + 04h ; MultiplyAccumulate16 Unsigned/Operand 1 */
338 MACS .equ MPY_SFR + 06h ; MultiplyAccumulate16 signed/Operand 1
339 OP2 .equ MPY_SFR + 08h ; Operand2_16 */
340 RESLO .equ MPY_SFR + 0Ah ; 16x16-bit result low - least significant word */
341 RESHI .equ MPY_SFR + 0Ch ; 16x16-bit result high */
342 SUMEXT .equ MPY_SFR + 0Eh ; 16x16-bit sum extension register
343 MPY32L .equ MPY_SFR + 10h ; Multiply32 Unsigned/Operand 1
344 MPY32H .equ MPY_SFR + 12h ; Multiply32 Unsigned/Operand 1
345 MPYS32L .equ MPY_SFR + 14h ; Multiply32 signed/Operand 1
346 MPYS32H .equ MPY_SFR + 16h ; Multiply32 signed/Operand 1
347 MAC32L .equ MPY_SFR + 18h ; MultiplyAccumulate32 Unsigned/Operand 1
348 MAC32H .equ MPY_SFR + 1Ah ; MultiplyAccumulate32 Unsigned/Operand 1
349 MACS32L .equ MPY_SFR + 1Ch ; MultiplyAccumulate32 signed/Operand 1
350 MACS32H .equ MPY_SFR + 1Eh ; MultiplyAccumulate32 signed/Operand 1
351 OP2L .equ MPY_SFR + 20h ; Multiply32 Operand 2
352 OP2H .equ MPY_SFR + 22h ; Multiply32 Operand 2
353 RES0 .equ MPY_SFR + 24h ; 32x32-bit result 0 - least significant word */
354 RES1 .equ MPY_SFR + 26h ; 32x32-bit result 1 */
355 RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */
356 RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
357 MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
362 ; ----------------------------------------------------------------------
364 ; ----------------------------------------------------------------------
365 TERM_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
366 TERM_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
367 TERM_MCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
368 TERM_STATW .equ eUSCI_A0_SFR + 0Ah ; eUSCI_A0 status Word Register
369 TERM_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
370 TERM_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
371 TERM_IE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
372 TERM_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
374 TERM_VEC .equ 0FFE0h ; interrupt vector for eUSCI_A0
375 WAKE_UP .equ 1 ; UART RX interrupt
382 ; ----------------------------------------------------------------------
384 ; ----------------------------------------------------------------------
385 SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; USCI_A1 Control Word Register 0
386 SD_BRW .equ eUSCI_A1_SFR + 06h ; USCI_A1 Baud Word Rate 0
387 SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; USCI_A1 Receive Buffer 8
388 SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; USCI_A1 Transmit Buffer 8
389 SD_IFG .equ eUSCI_A1_SFR + 1Ch ; USCI_A1 Interrupt Flags Register
396 ; ----------------------------------------------------------------------
398 ; ----------------------------------------------------------------------
399 TERM_CTLW0 .equ eUSCI_B1_SFR + 00h ; USCI_B1 Control Word Register 0
400 TERM_CTLW1 .equ eUSCI_B1_SFR + 02h ; USCI_B1 Control Word Register 1
401 TERM_BRW .equ eUSCI_B1_SFR + 06h ; USCI_B1 Baud Word Rate 0
402 TERM_STATW .equ eUSCI_B1_SFR + 08h ; USCI_B1 Status Word
403 TERM_RXBUF .equ eUSCI_B1_SFR + 0Ch ; USCI_B1 Receive Buffer 8
404 TERM_TXBUF .equ eUSCI_B1_SFR + 0Eh ; USCI_B1 Transmit Buffer 8
405 TERM_I2COA0 .equ eUSCI_B1_SFR + 14h ; USCI_B1 I2C Own Address 0
406 TERM_ADDRX .equ eUSCI_B1_SFR + 1Ch ; USCI_B1 Received Address Register
407 TERM_I2CSA .equ eUSCI_B1_SFR + 20h ; USCI_B1 I2C Slave Address
408 TERM_IE .equ eUSCI_B1_SFR + 2Ah ; USCI_B1 Interrupt Enable
409 TERM_IFG .equ eUSCI_B1_SFR + 2Ch ; USCI_B1 Interrupt Flags Register
411 TERM_VEC .equ 0FFDAh ; interrupt vector for eUSCI_B0
412 WAKE_UP .equ 4 ; START interrupt