2 ; MSP430FR4133 minimal declarations for FAST FORTH usage
3 DEVICE = "MSP430FR4133"
6 ; ----------------------------------------------
7 ; MSP430FR4133 MEMORY MAP
8 ; ----------------------------------------------
9 ; 0000-0FFF = peripherals (4 KB)
10 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
11 ; 1800-19FF = info B (FRAM 512 B)
12 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
14 ; 2000-27FF = RAM (2 KB)
16 ; C400-FF7F = code memory (FRAM 15232 B)
17 ; FF80-FFFF = interrupt vectors (FRAM 128 B)
18 ; ----------------------------------------------
19 PAGESIZE .equ 512 ; MPU unit
20 ; ----------------------------------------------
22 ; ----------------------------------------------
25 TLV_ORG .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
27 ; ----------------------------------------------
29 ; ----------------------------------------------
32 ; ----------------------------------------------
34 ; ----------------------------------------------
35 MAIN_ORG .equ 0C400h ; Code space start
36 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
37 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
38 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked
39 BSL_SIG1 .equ 0FF84h ;
40 BSL_SIG2 .equ 0FF86h ;
41 JTAG_PASSWORD .equ 0FF88h ; 256 bits
42 VECT_ORG .equ 0FFE2h ; FFE2-FFFF
44 BSL_PASSWORD .equ 0FFE0h ; 256 bits
46 ; ----------------------------------------------
47 ; Interrupt Vectors and signatures - MSP430FR4133
48 ; ----------------------------------------------
51 ;;Start of JTAG and BSL signatures
52 ; .word 0FFFFh ; JTAG signature 1
53 ; .word 0FFFFh ; JTAG signature 2
54 ; .word 0FFFFh ; BSL signature 1, 5555h to disable BSL
55 ; .word 0FFFFh ; BSL signature 2
57 ; .org INTVECT ; FFE2-FFFF 14 vectors + reset
59 ; .word reset ; FFE2h - LCD
60 ; .word reset ; FFE4h - P2
61 ; .word reset ; FFE6h - P1
62 ; .word reset ; FFE8h - ADC10
63 ; .word reset ; FFEAh - eUSCI_B0
64 ; .word reset ; FFECh - eUSCI_A0
65 ; .word reset ; FFEEh - WDT
66 ; .word reset ; FFF0h - RTC
67 ; .word reset ; FFF2h - TA1_x
68 ; .word reset ; FFF4h - TA1_0
69 ; .word reset ; FFF6h - TA0_x
70 ; .word reset ; FFF8h - TA0_0
71 ; .word reset ; FFFAh - UserNMI
72 ; .word reset ; FFFCh - SysNMI
73 ; .word reset ; FFFEh - Reset
76 ; ----------------------------------------------------------------------
77 ; EXP430FR4133 Peripheral File Map
78 ; ----------------------------------------------------------------------
79 SFR_SFR .set 0100h ; Special function
80 PMM_SFR .set 0120h ; PMM
81 SYS_SFR .set 0140h ; SYS
82 CS_SFR .set 0180h ; Clock System
83 FRAM_SFR .set 01A0h ; FRAM control
85 WDT_A_SFR .set 01CCh ; Watchdog
86 PA_SFR .set 0200h ; PORT1/2
87 PB_SFR .set 0220h ; PORT3/4
88 PC_SFR .set 0240h ; PORT5/6
89 PD_SFR .set 0260h ; PORT7/8
90 CTIO0_SFR .set 02E0h ; Capacitive Touch IO
94 eUSCI_A0_SFR .set 0500h ; eUSCI_A0
95 eUSCI_B0_SFR .set 0540h ; eUSCI_B0
97 BACK_MEM_SFR .set 0660h
98 ADC10_B_SFR .equ 0700h
101 ; ----------------------------------------------------------------------
102 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
103 ; ----------------------------------------------------------------------
107 PM5CTL0 .equ PMM_SFR + 10h ; Power mode 5 control register 0
108 LOCKLPM5 .equ 1 ; bit position
110 ; ----------------------------------------------------------------------
111 ; POWER ON RESET SYS config
112 ; ----------------------------------------------------------------------
113 SYSCTL .equ SYS_SFR + 00h ; System control
114 SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area
115 SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control
116 SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0
117 SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1
118 SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0
119 SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1
120 SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator
121 SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator
122 SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator
123 SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator
124 SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0
125 SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1
126 SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2
130 ; ----------------------------------------------------------------------
131 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
132 ; ----------------------------------------------------------------------
134 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
136 ; WDTCTL Control Bits
138 WDTHOLD .equ 0080h ; WDT - Timer hold
139 WDTCNTCL .equ 0008h ; WDT timer counter clear
142 ; ----------------------------------------------------------------------
143 ; POWER ON RESET AND INITIALIZATION : PORT1/2
144 ; ----------------------------------------------------------------------
146 PAIN .equ PA_SFR + 00h ; Port A Input
147 PAOUT .equ PA_SFR + 02h ; Port A Output
148 PADIR .equ PA_SFR + 04h ; Port A Direction
149 PAREN .equ PA_SFR + 06h ; Port A Resistor Enable
150 PASEL0 .equ PA_SFR + 0Ah ; Port A Selection 0
151 PASEL1 .equ PA_SFR + 0Ch ; Port A Selection 1
152 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
153 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
154 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt Flag
156 P1IN .equ PA_SFR + 00h ; Port 1 Input
157 P1OUT .equ PA_SFR + 02h ; Port 1 Output
158 P1DIR .equ PA_SFR + 04h ; Port 1 Direction
159 P1REN .equ PA_SFR + 06h ; Port 1 Resistor Enable
160 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 Selection 0
161 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 Selection 1
162 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
163 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
164 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
165 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt Flag
167 P2IN .equ PA_SFR + 01h ; Port 2 Input
168 P2OUT .equ PA_SFR + 03h ; Port 2 Output
169 P2DIR .equ PA_SFR + 05h ; Port 2 Direction
170 P2REN .equ PA_SFR + 07h ; Port 2 Resistor Enable
171 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 Selection 0
172 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 Selection 1
173 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
174 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
175 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag
176 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
178 ; ----------------------------------------------------------------------
179 ; POWER ON RESET AND INITIALIZATION : PORT3/4
180 ; ----------------------------------------------------------------------
183 PBIN .set PB_SFR + 00h ; Port B Input
184 PBOUT .set PB_SFR + 02h ; Port B Output 1/0 or pullup/pulldown resistor
185 PBDIR .set PB_SFR + 04h ; Port B Direction
186 PBREN .set PB_SFR + 06h ; Port B Resistor Enable
187 PBSEL0 .set PB_SFR + 0Ah ; Port B Selection 0
188 PBSEL1 .set PB_SFR + 0Ch ; Port B Selection 1
190 P3IN .set PB_SFR + 00h ; Port 3 Input */
191 P3OUT .set PB_SFR + 02h ; Port 3 Output
192 P3DIR .set PB_SFR + 04h ; Port 3 Direction
193 P3REN .set PB_SFR + 06h ; Port 3 Resistor Enable
194 P3SEL0 .set PB_SFR + 0Ah ; Port 3 Selection 0
195 P3SEL1 .set PB_SFR + 0Ch ; Port 3 Selection 1
197 P4IN .set PB_SFR + 01h ; Port 4 Input */
198 P4OUT .set PB_SFR + 03h ; Port 4 Output
199 P4DIR .set PB_SFR + 05h ; Port 4 Direction
200 P4REN .set PB_SFR + 07h ; Port 4 Resistor Enable
201 P4SEL0 .set PB_SFR + 0Bh ; Port 4 Selection 0
202 P4SEL1 .set PB_SFR + 0Dh ; Port 4 Selection 1
205 ; ----------------------------------------------------------------------
206 ; POWER ON RESET AND INITIALIZATION : PORT5/6
207 ; ----------------------------------------------------------------------
210 PCIN .set PC_SFR + 00h ; Port C Input
211 PCOUT .set PC_SFR + 02h ; Port C Output 1/0 or pullup/pulldown resistor
212 PCDIR .set PC_SFR + 04h ; Port C Direction
213 PCREN .set PC_SFR + 06h ; Port C Resistor Enable
214 PCSEL0 .set PC_SFR + 0Ah ; Port C Selection 0
215 PCSEL1 .set PC_SFR + 0Ch ; Port C Selection 1
217 P5IN .set PC_SFR + 00h ; Port 5 Input */
218 P5OUT .set PC_SFR + 02h ; Port 5 Output
219 P5DIR .set PC_SFR + 04h ; Port 5 Direction
220 P5REN .set PC_SFR + 06h ; Port 5 Resistor Enable
221 P5SEL0 .set PC_SFR + 0Ah ; Port 5 Selection 0
222 P5SEL1 .set PC_SFR + 0Ch ; Port 5 Selection 1
224 P6IN .set PC_SFR + 01h ; Port 6 Input */
225 P6OUT .set PC_SFR + 03h ; Port 6 Output
226 P6DIR .set PC_SFR + 05h ; Port 6 Direction
227 P6REN .set PC_SFR + 07h ; Port 6 Resistor Enable
228 P6SEL0 .set PC_SFR + 0Bh ; Port 6 Selection 0
229 P6SEL1 .set PC_SFR + 0Dh ; Port 6 Selection 1
231 ; ----------------------------------------------------------------------
232 ; POWER ON RESET AND INITIALIZATION : PORT7/8
233 ; ----------------------------------------------------------------------
236 PDIN .set PD_SFR + 00h ; Port D Input
237 PDOUT .set PD_SFR + 02h ; Port D Output 1/0 or pullup/pulldown resistor
238 PDDIR .set PD_SFR + 04h ; Port D Direction
239 PDREN .set PD_SFR + 06h ; Port D Resistor Enable
240 PDSEL0 .set PD_SFR + 0Ah ; Port D Selection 0
241 PDSEL1 .set PD_SFR + 0Ch ; Port D Selection 1
243 P7IN .set PD_SFR + 00h ; Port 7 Input */
244 P7OUT .set PD_SFR + 02h ; Port 7 Output
245 P7DIR .set PD_SFR + 04h ; Port 7 Direction
246 P7REN .set PD_SFR + 06h ; Port 7 Resistor Enable
247 P7SEL0 .set PD_SFR + 0Ah ; Port 7 Selection 0
248 P7SEL1 .set PD_SFR + 0Ch ; Port 7 Selection 1
250 P8IN .set PD_SFR + 01h ; Port 8 Input */
251 P8OUT .set PD_SFR + 03h ; Port 8 Output
252 P8DIR .set PD_SFR + 05h ; Port 8 Direction
253 P8REN .set PD_SFR + 07h ; Port 8 Resistor Enable
254 P8SEL0 .set PD_SFR + 0Bh ; Port 8 Selection 0
255 P8SEL1 .set PD_SFR + 0Dh ; Port 8 Selection 1
257 ; ----------------------------------------------------------------------
259 ; ----------------------------------------------------------------------
261 FRCTL0 .equ FRAM_SFR + 00h ; FRAM Controller Control 0
262 FRCTL0_H .equ FRAM_SFR + 01h ; FRAM Controller Control 0 high byte
264 ; ----------------------------------------------------------------------
265 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
266 ; ----------------------------------------------------------------------
268 CSCTL0 .equ CS_SFR + 00h ; Clock System Control Register 0
269 CSCTL1 .equ CS_SFR + 02h ; Clock System Control Register 1
270 CSCTL2 .equ CS_SFR + 04h ; Clock System Control Register 2
271 CSCTL3 .equ CS_SFR + 06h ; Clock System Control Register 3
272 CSCTL4 .equ CS_SFR + 08h ; Clock System Control Register 4
273 CSCTL5 .equ CS_SFR + 0Ah ; Clock System Control Register 5
274 CSCTL6 .equ CS_SFR + 0Ch ; Clock System Control Register 6
275 CSCTL7 .equ CS_SFR + 0Eh ; Clock System Control Register 7
276 CSCTL8 .equ CS_SFR + 10h ; Clock System Control Register 8
280 ; ----------------------------------------------------------------------
282 ; ----------------------------------------------------------------------
283 RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control
284 RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector
285 RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo
286 RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter
290 UCSWRST .equ 1 ; eUSCI Software Reset
291 UCTXIE .equ 2 ; eUSCI Transmit Interrupt Enable
292 UCRXIE .equ 1 ; eUSCI Receive Interrupt Enable
293 UCTXIFG .equ 2 ; eUSCI Transmit Interrupt Flag
294 UCRXIFG .equ 1 ; eUSCI Receive Interrupt Flag
296 ; ----------------------------------------------------------------------
298 ; ----------------------------------------------------------------------
301 TERM_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
302 TERM_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
303 TERM_MCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
304 TERM_STATW .equ eUSCI_A0_SFR + 0Ah ; eUSCI_A0 status Word Register
305 TERM_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
306 TERM_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
307 TERM_IE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
308 TERM_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
309 TERM_VEC .equ 0FFECh ; interrupt vector for eUSCI_A0
312 ; ----------------------------------------------------------------------
314 ; ----------------------------------------------------------------------
317 SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
318 SD_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
319 SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
320 SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
321 SD_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register