2 ; MSP430FR5739 minimal declarations for FastForth usage
3 DEVICE = "MSP430FR5739"
6 ; ----------------------------------------------
7 ; MSP430FR5739 MEMORY MAP
8 ; ----------------------------------------------
9 ; 0000-0FFF = peripherals (4 KB)
10 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
11 ; 1800-187F = info B (FRAM 128 B)
12 ; 1880-18FF = info A (FRAM 128 B)
13 ; 1900-19FF = N/A (mirrored into info A/B)
14 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
15 ; 1A80-1BFF = unused (385 B)
16 ; 1C00-1FFF = RAM (1 KB)
17 ; 2000-C1FF = unused (41472 B)
18 ; C200-FF7F = code memory (FRAM 15743 B)
19 ; FF80-FFFF = interrupt vectors (FRAM 127 B)
20 ; ----------------------------------------------
21 PAGESIZE .equ 512 ; MPU unit
22 ; ----------------------------------------------
23 ; FRAM ; INFO B, A, TLV
24 ; ----------------------------------------------
31 ; ----------------------------------------------
32 TLV_ORG .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
34 ; ----------------------------------------------
36 ; ----------------------------------------------
39 ; ----------------------------------------------
41 ; ----------------------------------------------
42 MAIN_ORG .equ 0C200h ; Code space start
43 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
44 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
45 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
46 BSL_SIG1 .equ 0FF84h ;
47 BSL_SIG2 .equ 0FF86h ;
48 I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address
49 I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address
50 I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address
51 I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address
52 JTAG_PASSWORD .equ 0FF88h ; 256 bits
53 VECT_ORG .equ 0FFCEh ; FFCE-FFFF
55 BSL_PASSWORD .equ 0FFE0h ; 256 bits
56 ; ----------------------------------------------
60 ; ----------------------------------------------
61 ; Interrupt Vectors and signatures - MSP430FR57xx
62 ; ----------------------------------------------
65 ;;Start of JTAG and BSL signatures
66 ; .word 0 ; JTAG signature 1
67 ; .word 0 ; JTAG signature 2
68 ; .word 0 ; 5555h ; BSL signature 1 ; disable BSL
69 ; .word 0 ; BSL signature 2
71 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
73 ; .org INTVECT ; FFCE-FFFF 24 vectors + reset
74 ; .word reset ; 0FFCEh - RTC_B
75 ; .word reset ; 0FFD0h - I/O Port 4
76 ; .word reset ; 0FFD2h - I/O Port 3
77 ; .word reset ; 0FFD4h - TB2_1
78 ; .word reset ; 0FFD6h - TB2_0
79 ; .word reset ; 0FFD8h - I/O Port 2
80 ; .word reset ; 0FFDAh - TB1_1
81 ; .word reset ; 0FFDCh - TB1_0
82 ; .word reset ; 0FFDEh - I/O Port 1
83 ;; .org BSL_PASSWORD ;Start of BSL PASSWORD
84 ; .word reset ; 0FFE0h - TA1_1
85 ; .word reset ; 0FFE2h - TA1_0
86 ; .word reset ; 0FFE4h - DMA
87 ; .word reset ; 0FFE6h - eUSCI_A1
88 ; .word reset ; 0FFE8h - TA0_1
89 ; .word reset ; 0FFEAh - TA0_0
90 ; .word reset ; 0FFECh - ADC10_B
91 ; .word reset ; 0FFEEh - eUSCI_B0
92 ; .word reset ; 0FFF0h - eUSCI_A0
93 ; .word reset ; 0FFF2h - Watchdog
94 ; .word reset ; 0FFF4h - TB0_1
95 ; .word reset ; 0FFF6h - TB0_0
96 ; .word reset ; 0FFF8h - COMP_D
97 ; .word reset ; 0FFFAh - userNMI
98 ; .word reset ; 0FFFCh - sysNMI
99 ; .word reset ; 0FFFEh - reset
103 ; ----------------------------------------------------------------------
104 ; MSP430FR5739 Peripheral File Map
105 ; ----------------------------------------------------------------------
106 SFR_SFR .equ 0100h ; Special function
107 PMM_SFR .equ 0120h ; PMM
108 FRAM_SFR .equ 0140h ; FRAM control
110 WDT_A_SFR .equ 015Ch ; Watchdog
112 SYS_SFR .equ 0180h ; SYS
113 REF_SFR .equ 01B0h ; REF
114 PA_SFR .equ 0200h ; PORT1/2
115 PB_SFR .equ 0220h ; PORT3/4
116 PJ_SFR .equ 0320h ; PORTJ
124 DMA_CTRL_SFR .equ 0500h
125 DMA_CHN0_SFR .equ 0510h
126 DMA_CHN1_SFR .equ 0520h
127 DMA_CHN2_SFR .equ 0530h
128 MPU_SFR .equ 05A0h ; memory protect unit
129 eUSCI_A0_SFR .equ 05C0h ; eUSCI_A0
130 eUSCI_A1_SFR .equ 05E0h ; eUSCI_A1
131 eUSCI_B0_SFR .equ 0640h ; eUSCI_B0
132 ADC10_B_SFR .equ 0700h
133 COMP_D_SFR .equ 08C0h
135 ; ----------------------------------------------------------------------
136 ; POWER ON RESET AND INITIALIZATION : LOCK I/O as high impedance state
137 ; ----------------------------------------------------------------------
139 SFRIFG1 .equ SFR_SFR + 2
140 SFRRPCR .equ SFR_SFR + 4
145 PM5CTL0 .equ PMM_SFR + 10h ; Power mode 5 control register 0
148 ; ----------------------------------------------------------------------
149 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
150 ; ----------------------------------------------------------------------
152 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
154 ; WDTCTL Control Bits
156 WDTHOLD .equ 0080h ; WDT - Timer hold
157 WDTCNTCL .equ 0008h ; WDT timer counter clear
159 ; ----------------------------------------------------------------------
160 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
161 ; ----------------------------------------------------------------------
163 CSCTL0 .equ CS_SFR + 00h ; CS Control Register 0
164 CSCTL0_H .equ CS_SFR + 01h ; CS Control Register 0 high byte
165 CSCTL1 .equ CS_SFR + 02h ; CS Control Register 1
166 CSCTL2 .equ CS_SFR + 04h ; CS Control Register 2
167 CSCTL3 .equ CS_SFR + 06h ; CS Control Register 3
169 ; CSCTL0 Control Bits
170 CSKEY .equ 0A5h ; CS Password
171 ; CSCTL1 Control Bits
173 DCOFSEL0 .equ 0002h ; DCO frequency select Bit: 0
174 DCOFSEL1 .equ 0004h ; DCO frequency select Bit: 1
175 ; CSCTL2 Control Bits
176 ; SELA_LFXCLK .equ 0000h ; 0 : ACLK Source Select LFXCLK
177 SELA_LFXCLK .equ 0000h ; 0 : ACLK Source Select LFXCLK
178 SELA_VLOCLK .equ 0100h ; 1 ACLK Source Select VLOCLK 10kHz
179 SELS_DCOCLK .equ 0030h ; 3 SMCLK Source Select DCOCLK
180 SELM_DCOCLK .equ 0003h ; 3 MCLK Source Select DCOCLK
181 ; CSCTL3 Control Bits
182 DIVA_0 .equ 0000h ; ACLK Source Divider 0
183 DIVS_0 .equ 0000h ; SMCLK Source Divider 0
184 DIVM_0 .equ 0000h ; MCLK Source Divider 0
185 DIVA_2 .equ 0100h ; ACLK Source Divider 0
186 DIVS_2 .equ 0010h ; SMCLK Source Divider 0
187 DIVM_2 .equ 0001h ; MCLK Source Divider 0
188 DIVA_4 .equ 0200h ; ACLK Source Divider 0
189 DIVS_4 .equ 0020h ; SMCLK Source Divider 0
190 DIVM_4 .equ 0002h ; MCLK Source Divider 0
191 DIVA_8 .equ 0300h ; ACLK Source Divider 0
192 DIVS_8 .equ 0030h ; SMCLK Source Divider 0
193 DIVM_8 .equ 0003h ; MCLK Source Divider 0
194 DIVA_16 .equ 0400h ; ACLK Source Divider 0
195 DIVS_16 .equ 0040h ; SMCLK Source Divider 0
196 DIVM_16 .equ 0004h ; MCLK Source Divider 0
197 DIVA_32 .equ 0500h ; ACLK Source Divider 0
198 DIVS_32 .equ 0050h ; SMCLK Source Divider 0
199 DIVM_32 .equ 0005h ; MCLK Source Divider 0
201 ; ----------------------------------------------------------------------
202 ; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
203 ; ----------------------------------------------------------------------
205 SYSRSTIV .equ SYS_SFR + 001Eh
208 ; ----------------------------------------------------------------------
209 ; POWER ON RESET AND INITIALIZATION : REF
210 ; ----------------------------------------------------------------------
212 REFCTL .equ REF_SFR + 00h ; REF Shared Reference control register 0
214 ; REFCTL0 Control Bits
215 REFON .equ 0001h ; REF Reference On
216 REFTCOFF .equ 0008h ; REF Temp.Sensor off
218 ; ----------------------------------------------------------------------
219 ; POWER ON RESET AND INITIALIZATION PAIN=PORT2:PORT1
220 ; ----------------------------------------------------------------------
222 PAIN .equ PA_SFR + 00h ; Port A INput
223 PAOUT .equ PA_SFR + 02h ; Port A OUTput
224 PADIR .equ PA_SFR + 04h ; Port A DIRection
225 PAREN .equ PA_SFR + 06h ; Port A Resistor ENable
226 PASEL0 .equ PA_SFR + 0Ah ; Port A SELection 0
227 PASEL1 .equ PA_SFR + 0Ch ; Port A SELection 1
228 PASELC .equ PA_SFR + 16h ; Port A SELection Complement
229 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
230 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
231 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt FlaG
233 P1IN .equ PA_SFR + 00h ; Port 1 INput
234 P1OUT .equ PA_SFR + 02h ; Port 1 OUTput
235 P1DIR .equ PA_SFR + 04h ; Port 1 DIRection
236 P1REN .equ PA_SFR + 06h ; Port 1 Resistor ENable
237 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 SELection 0
238 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 SELection 1
239 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
240 P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement
241 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
242 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
243 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt FlaG
245 P2IN .equ PA_SFR + 01h ; Port 2 INput
246 P2OUT .equ PA_SFR + 03h ; Port 2 OUTput
247 P2DIR .equ PA_SFR + 05h ; Port 2 DIRection
248 P2REN .equ PA_SFR + 07h ; Port 2 Resistor ENable
249 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 SELection 0
250 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 SELection 1
251 P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement
252 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
253 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
254 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag
255 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
257 ; ----------------------------------------------------------------------
258 ; POWER ON RESET AND INITIALIZATION : PORT3/4
259 ; ----------------------------------------------------------------------
262 PBIN .set PB_SFR + 00h ; Port B Input
263 PBOUT .set PB_SFR + 02h ; Port B Output 1/0 or pullup/pulldown resistor
264 PBDIR .set PB_SFR + 04h ; Port B Direction
265 PBREN .set PB_SFR + 06h ; Port B Resistor Enable
266 PBSEL0 .set PB_SFR + 0Ah ; Port B Selection 0
267 PBSEL1 .set PB_SFR + 0Ch ; Port B Selection 1
268 PBSELC .set PB_SFR + 16h ; Port B Complement Selection
269 PBIES .set PB_SFR + 18h ; Port B Interrupt Edge Select
270 PBIE .set PB_SFR + 1Ah ; Port B Interrupt Enable
271 PBIFG .set PB_SFR + 1Ch ; Port B Interrupt Flag
273 P3IN .set PB_SFR + 00h ; Port 3 Input */
274 P3OUT .set PB_SFR + 02h ; Port 3 Output
275 P3DIR .set PB_SFR + 04h ; Port 3 Direction
276 P3REN .set PB_SFR + 06h ; Port 3 Resistor Enable
277 P3SEL0 .set PB_SFR + 0Ah ; Port 3 Selection 0
278 P3SEL1 .set PB_SFR + 0Ch ; Port 3 Selection 1
279 P3SELC .set PB_SFR + 16h ; Port 3 Complement Selection
280 P3IES .set PB_SFR + 18h ; Port 3 Interrupt Edge Select
281 P3IE .set PB_SFR + 1Ah ; Port 3 Interrupt Enable
282 P3IFG .set PB_SFR + 1Ch ; Port 3 Interrupt Flag
284 P4IN .set PB_SFR + 01h ; Port 4 Input */
285 P4OUT .set PB_SFR + 03h ; Port 4 Output
286 P4DIR .set PB_SFR + 05h ; Port 4 Direction
287 P4REN .set PB_SFR + 07h ; Port 4 Resistor Enable
288 P4SEL0 .set PB_SFR + 0Bh ; Port 4 Selection 0
289 P4SEL1 .set PB_SFR + 0Dh ; Port 4 Selection 1
290 P4SELC .set PB_SFR + 17h ; Port 4 Complement Selection
291 P4IES .set PB_SFR + 19h ; Port 4 Interrupt Edge Select
292 P4IE .set PB_SFR + 1Bh ; Port 4 Interrupt Enable
293 P4IFG .set PB_SFR + 1Dh ; Port 4 Interrupt Flag
295 ; ----------------------------------------------------------------------
296 ; POWER ON RESET AND INITIALIZATION : PORTJ
297 ; ----------------------------------------------------------------------
299 PJIN .set PJ_SFR + 00h ; Port B Input
300 PJOUT .set PJ_SFR + 02h ; Port B Output
301 PJDIR .set PJ_SFR + 04h ; Port B Direction
302 PJREN .set PJ_SFR + 06h ; Port B Resistor Enable
303 PJSEL0 .set PJ_SFR + 0Ah ; Port B Selection 0
304 PJSEL1 .set PJ_SFR + 0Ch ; Port B Selection 1
305 PJSELC .set PJ_SFR + 16h ; Port B Complement Selection
308 ; ----------------------------------------------------------------------
310 ; ----------------------------------------------------------------------
311 RTCCTL01 .equ RTC_B_SFR + 00h
312 RTCCTL0 .equ RTC_B_SFR + 00h
313 RTCCTL1 .equ RTC_B_SFR + 01h
314 RTCCTL23 .equ RTC_B_SFR + 02h
315 RTCPS0CTL .equ RTC_B_SFR + 08h
316 RTCPS1CTL .equ RTC_B_SFR + 0Ah
317 RTCPS .equ RTC_B_SFR + 0Ch
318 RTCIV .equ RTC_B_SFR + 0Eh
319 RTCSEC .equ RTC_B_SFR + 10h
320 RTCMIN .equ RTC_B_SFR + 11h
321 RTCHOUR .equ RTC_B_SFR + 12h
322 RTCDOW .equ RTC_B_SFR + 13h
323 RTCDAY .equ RTC_B_SFR + 14h
324 RTCMON .equ RTC_B_SFR + 15h
325 RTCYEAR .equ RTC_B_SFR + 16h
331 ; ----------------------------------------------------------------------
333 ; ----------------------------------------------------------------------
335 MPY .equ MPY_SFR + 00h ; Multiply16 Unsigned/Operand 1 */
336 MPYS .equ MPY_SFR + 02h ; Multiply16 signed/Operand 1
337 MAC .equ MPY_SFR + 04h ; MultiplyAccumulate16 Unsigned/Operand 1 */
338 MACS .equ MPY_SFR + 06h ; MultiplyAccumulate16 signed/Operand 1
339 OP2 .equ MPY_SFR + 08h ; Operand2_16 */
340 RESLO .equ MPY_SFR + 0Ah ; 16x16-bit result low - least significant word */
341 RESHI .equ MPY_SFR + 0Ch ; 16x16-bit result high */
342 SUMEXT .equ MPY_SFR + 0Eh ; 16x16-bit sum extension register
343 MPY32L .equ MPY_SFR + 10h ; Multiply32 Unsigned/Operand 1
344 MPY32H .equ MPY_SFR + 12h ; Multiply32 Unsigned/Operand 1
345 MPYS32L .equ MPY_SFR + 14h ; Multiply32 signed/Operand 1
346 MPYS32H .equ MPY_SFR + 16h ; Multiply32 signed/Operand 1
347 MAC32L .equ MPY_SFR + 18h ; MultiplyAccumulate32 Unsigned/Operand 1
348 MAC32H .equ MPY_SFR + 1Ah ; MultiplyAccumulate32 Unsigned/Operand 1
349 MACS32L .equ MPY_SFR + 1Ch ; MultiplyAccumulate32 signed/Operand 1
350 MACS32H .equ MPY_SFR + 1Eh ; MultiplyAccumulate32 signed/Operand 1
351 OP2L .equ MPY_SFR + 20h ; Multiply32 Operand 2
352 OP2H .equ MPY_SFR + 22h ; Multiply32 Operand 2
353 RES0 .equ MPY_SFR + 24h ; 32x32-bit result 0 - least significant word */
354 RES1 .equ MPY_SFR + 26h ; 32x32-bit result 1 */
355 RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */
356 RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
357 MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
360 MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0
361 MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1
362 MPUSEG .equ MPU_SFR + 04h ; MPU Segmentation Register
363 MPUSAM .equ MPU_SFR + 06h ; MPU access management
367 ; ----------------------------------------------------------------------
369 ; ----------------------------------------------------------------------
370 TERM_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
371 TERM_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
372 TERM_MCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
373 TERM_STATW .equ eUSCI_A0_SFR + 0Ah ; eUSCI_A0 status Word Register
374 TERM_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
375 TERM_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
376 TERM_IE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
377 TERM_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
379 TERM_VEC .equ 0FFF0h ; interrupt vector for eUSCI_A0
380 WAKE_UP .equ 1 ; UART RX interrupt
387 ; ----------------------------------------------------------------------
389 ; ----------------------------------------------------------------------
390 SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
391 SD_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
392 SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer 8
393 SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer 8
394 SD_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
400 ; ----------------------------------------------------------------------
401 ; eUSCI_B0 as TERMINAL I2C input
402 ; ----------------------------------------------------------------------
403 TERM_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
404 TERM_CTLW1 .equ eUSCI_B0_SFR + 02h ; USCI_B0 Control Word Register 1
405 TERM_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
406 TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word
407 TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
408 TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
409 TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0
410 TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register
411 TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address
412 TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable
413 TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
415 TERM_VEC .equ 0FFEEh ; interrupt vector for eUSCI_B0
416 WAKE_UP .equ 4 ; START interrupt
423 ; ----------------------------------------------------------------------
425 ; ----------------------------------------------------------------------
426 SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
427 SD_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
428 SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
429 SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
430 SD_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register