1 ; -*- coding: utf-8 -*-
3 ; ======================================================================
4 ; INIT MSP-EXP430FR2355 board
5 ; ======================================================================
10 ; "TXD" <--- P4.3 == UCA0TXD <-- UCA0TXDBUf
11 ; "RXD" ---> P4.2 == UCA0RXD --> UCA0RXDBUF
38 ; J3.23 - P1.4 A4 SEED
43 ; J3.28 - P1.1 A1 SEED
75 ; ======================================================================
76 ; MSP-EXP430FR2355 LAUNCHPAD <--> OUTPUT WORLD
77 ; ======================================================================
79 ; +--4k7-< DeepRST switch <-- GND
81 ; P4.3 - UCA1 TXD J101.6 - <-+-> RX UARTtoUSB bridge
82 ; P4.2 - UCA1 RXD J101.8 - <---- TX UARTtoUSB bridge
83 ; P2.0 - RTS J2.19 - ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
84 ; P2.1 - CTS J4.40 - <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
86 ; P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Master_Slave
87 ; P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Master_Slave
89 ; P2.2 - J2.18 - <---- TSSOP32236 (IR RC5)
91 ; P2.5 - J2.13 - <---- SD_CD (Card Detect)
92 ; P4.4 - J2.12 - ----> SD_CS (Card Select)
93 ; P4.5 - UCB1 CLK J1.7 - ----> SD_CLK
94 ; P4.6 - UCB1 SIMO J2.15 - ----> SD_SDI
95 ; P4.7 - UCB1 SOMI J2.14 - <---- SD_SDO
97 ; P6.0 - J4.39 - ----> SCL I2C Soft_Master
98 ; P6.1 - J4.38 - <---> SDA I2C Soft_Master
100 ; ----------------------------------------------------------------------
101 ; POWER ON RESET AND INITIALIZATION : I/O
102 ; ----------------------------------------------------------------------
104 ; ----------------------------------------------------------------------
105 ; POWER ON RESET AND INITIALIZATION : PORT1/2
106 ; ----------------------------------------------------------------------
108 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
114 LED1 .equ 1 ; P1.0 LED1 red
120 BUS_TERM .equ 0Ch ; P1.2=SDA, P1.3=SCL
124 ; UART RTS P2.0 - J2.19 ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
125 ; UART CTS P2.1 - J4.40 <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
127 ; P2.5 - J2.10 <---- SD_CD (Card Detect)
129 BIS #-1,&PAREN ; all inputs with pull up/down resistors
130 MOV #0FFFEh,&PAOUT ; all pins with pullup resistors else LED1
132 .IFDEF TERMINAL4WIRES
133 ; RTS output is wired to the CTS input of UART2USB bridge
134 ; configure RTS as output high (false) to disable RX TERM during start FORTH
135 HANDSHAKOUT .equ P2OUT
138 BIS.B #RTS,&P2DIR ; RTS as output high
139 .IFDEF TERMINAL5WIRES
140 ; CTS input must be wired to the RTS output of UART2USB bridge
141 ; configure CTS as input low (true) to avoid lock when CTS is not wired
143 BIC.B #CTS,&P2OUT ; CTS input resistor is pulled down
144 .ENDIF ; TERMINAL5WIRES
145 .ENDIF ; TERMINAL4WIRES
149 SW2 .equ 8 ; P2.3 = S2
152 CD_SD .equ 20h ; P2.5
154 ; ----------------------------------------------------------------------
155 ; POWER ON RESET AND INITIALIZATION : PORT3-4
156 ; ----------------------------------------------------------------------
158 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
163 ; UCA1 RXD P4.2 - J101.8 <---- TX UARTtoUSB bridge
164 ; UCA1 TXD P4.3 - J101.6 ----> RX UARTtoUSB bridge
165 ; P4.4 - J2.9 ----> SD_CS(Card Select)
166 ; UCB1 CLK P4.5 - J1.7 ----> SD_CLK
167 ; UCB1 SIMO P4.6 - J2.15 ----> SD_SDI
168 ; UCB1 SOMI P4.7 - J2.14 <---- SD_SDO
170 BIS #-1,&PBREN ; all pins with pull resistors
171 MOV #-1,&PBOUT ; pullup resistors for all pins
174 SW1 .equ 2 ; P4.1 = S1
177 IO_WIPE .equ 2 ; P4.1 = S1 = FORTH Deep_RST pin
180 ; UCA1 RXD P4.2 - J101.8 <---- TX UARTtoUSB bridge
181 ; UCA1 TXD P4.3 - J101.6 ----> RX UARTtoUSB bridge
185 RXD .equ 4 ; P4.2 = RXD
186 TXD .equ 8 ; P4.3 = TXD
193 CS_SD .equ 10h ; P4.4
195 SD_SEL .equ PBSEL0 ; to configure UCB1
196 SD_REN .equ PBREN ; to configure pullup resistors
197 BUS_SD .equ 0E000h ; pins P4.5 as UCA1CLK, P4.6 as UCA1SIMO & P4.7 as UCA1SOMI
199 ; ----------------------------------------------------------------------
200 ; POWER ON RESET AND INITIALIZATION : PORT5-6
201 ; ----------------------------------------------------------------------
203 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
208 LED2 .equ 40h ; P6.6 LED2 green
210 BIS.B #-1,&P6REN ; all pins with pull up/down resistors
211 MOV.B #0BFh,&P6OUT ; all pins with pull up resistors else P6.6
213 ; ----------------------------------------------------------------------
215 ; ----------------------------------------------------------------------
217 .IF (FREQUENCY >8 ) && ( FREQUENCY <= 16)
218 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
219 MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
220 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
221 .ELSEIF FREQUENCY > 16
222 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
223 MOV.B #20h, &FRCTL0 ; 2 waitstate @ 24 MHz
224 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
227 ; ----------------------------------------------------------------------
228 ; POWER ON RESET SYS config
229 ; ----------------------------------------------------------------------
231 MOV #0A500h,&SYSCFG0 ; enable write MAIN + INFO
233 ; ----------------------------------------------------------------------
234 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
235 ; ----------------------------------------------------------------------
237 ; CS code for MSP430FR2355
239 ; to measure SMCLK frequency, wires SMCLK on P1.0:
243 ; to measure REFO frequency, wires ACLK on P1.1:
249 MOV #1ED1h,&CSCTL0 ; preset MOD=31, DCO = measured value @ 0x180 (209)
250 MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
251 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
252 ; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh
253 ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz
254 MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh
255 ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz
256 ; MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
257 ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
258 ; =====================================
261 .ELSEIF FREQUENCY = 1
263 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
264 MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
265 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
266 ; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh
267 ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz
268 MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh
269 ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz
270 ; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
271 ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
272 ; =====================================
275 .ELSEIF FREQUENCY = 2
277 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
278 MOV #00B2h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
279 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
280 ; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh
281 ; fCOCLKDIV = 32768 x (59+1) = 1.966 MHz ; measured : MHz
282 MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch
283 ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz
284 ; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
285 ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz
286 ; =====================================
289 .ELSEIF FREQUENCY = 4
291 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
292 MOV #00B4h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
293 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
294 ; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h
295 ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz
297 MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h
298 ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz
300 ; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
301 ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
302 ; =====================================
305 .ELSEIF FREQUENCY = 8
307 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
308 MOV #00B6h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
309 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
310 MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h
311 ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz
312 ; MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h
313 ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz
315 ; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h
316 ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz
317 ; =====================================
320 .ELSEIF FREQUENCY = 12
322 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
323 MOV #00B8h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
324 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
325 MOV #016Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h
326 ; fCOCLKDIV = 32768 x 365+1) = 11.993 MHz ; measured : 11.xxxMHz
327 ; MOV #016Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h
328 ; fCOCLKDIV = 32768 x 366+1) = 12.025 MHz ; measured : 12.xxxMHz
329 ; MOV #016Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
330 ; fCOCLKDIV = 32768 x 367+1) = 12.058 MHz ; measured : 12.xxxMHz
331 ; =====================================
334 .ELSEIF FREQUENCY = 16
336 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
337 MOV #00BAh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
338 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
339 ; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h
340 ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz
341 MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h
342 ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz
343 ; MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
344 ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
345 ; =====================================
348 .ELSEIF FREQUENCY = 20
350 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
351 MOV #00BCh,&CSCTL1 ; Set 20MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
352 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
353 ; MOV #0261h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=261h
354 ; fCOCLKDIV = 32768 x 609+1) = 19.988 MHz ; measured : 19.xxxMHz
355 MOV #0262h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=262h
356 ; fCOCLKDIV = 32768 x 610+1) = 20.021 MHz ; measured : 20.xxxMHz
357 ; MOV #0263h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=263h
358 ; fCOCLKDIV = 32768 x 611+1) = 20.054 MHz ; measured : 20.xxxMHz
359 ; =====================================
362 .ELSEIF FREQUENCY = 24
364 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
365 MOV #00BEh,&CSCTL1 ; Set 24MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
366 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
367 ; MOV #02DBh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DBh
368 ; fCOCLKDIV = 32768 x 731+1) = 23.986 MHz ; measured : 23.xxxMHz
369 MOV #02DCh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DCh
370 ; fCOCLKDIV = 32768 x 732+1) = 24.019 MHz ; measured : 23.xxxMHz
371 ; MOV #02DDh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DDh
372 ; fCOCLKDIV = 32768 x 733+1) = 24.051 MHz ; measured : 24.xxxMHz
373 ; =====================================
377 .error "bad frequency setting, only 0.5,1,2,4,8,12,16,20,24 MHz"
382 ; because LOCKLPM5 is ON, XT1 is replaced by REFO automaticaly until WARM clears LOCKLPM5
383 ; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value)
384 MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
385 BIS.B #0C0h,&P2SEL1 ; P2.6 as XOUT, P2.7 as XIN
387 BIS #0010h,&CSCTL3 ; FLL select REFCLOCK
388 ; MOV #0100h,&CSCTL4 ; ACLOCK select REFOCLK, MCLK & SMCLK select DCOCLKDIV (default value)
392 BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
393 ; MOV &SAVE_SYSRSTIV,TOS ;
394 ; CMP #2,TOS ; POWER ON ?
395 ; JZ ClockWaitX ; yes
396 ; RRUM #1,X ; wait only 250 ms
397 ClockWaitX MOV #5209,Y ; wait 0.5s before starting after POR
398 ; ...because FLL lock time = 280 ms
399 ClockWaitY SUB #1,Y ;1
400 JNZ ClockWaitY ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
401 SUB #1,X ; x 32 @ 1 MHZ = 500ms
402 JNZ ClockWaitX ; time to stabilize power source ( 500ms )
404 ;WAITFLL BIT #300h,&CSCTL7 ; wait FLL lock