1 ; -*- coding: utf-8 -*-
3 ; Fast Forth For Texas Instrument MSP430FR5739
4 ; Tested on MSP-EXP430FR2355 launchpad
6 ; Copyright (C) <2018> <J.M. THOORENS>
8 ; This program is free software: you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
21 ; ======================================================================
22 ; INIT MSP-EXP430FR2355 board
23 ; ======================================================================
28 ; "TXD" <--- P4.3 == UCA0TXD <-- UCA0TXDBUf
29 ; "RXD" ---> P4.2 == UCA0RXD --> UCA0RXDBUF
56 ; J3.23 - P1.4 A4 SEED
61 ; J3.28 - P1.1 A1 SEED
93 ; ======================================================================
94 ; MSP-EXP430FR2355 LAUNCHPAD <--> OUTPUT WORLD
95 ; ======================================================================
97 ; +--4k7-< DeepRST switch <-- GND
99 ; P4.3 - UCA1 TXD J101.6 - <-+-> RX UARTtoUSB bridge
100 ; P4.2 - UCA1 RXD J101.8 - <---- TX UARTtoUSB bridge
101 ; P2.0 - RTS J2.19 - ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
102 ; P2.1 - CTS J4.40 - <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
104 ; P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Master_Slave
105 ; P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Master_Slave
107 ; P2.2 - J2.18 - <---- TSSOP32236 (IR RC5)
109 ; P2.5 - J2.13 - <---- SD_CD (Card Detect)
110 ; P4.4 - J2.12 - ----> SD_CS (Card Select)
111 ; P4.5 - UCB1 CLK J1.7 - ----> SD_CLK
112 ; P4.6 - UCB1 SIMO J2.15 - ----> SD_SDI
113 ; P4.7 - UCB1 SOMI J2.14 - <---- SD_SDO
115 ; P6.0 - J4.39 - ----> SCL I2C Soft_Master
116 ; P6.1 - J4.38 - <---> SDA I2C Soft_Master
118 ; ----------------------------------------------------------------------
119 ; INIT order : WDT, GPIOs, FRAM, Clock, UARTs...
120 ; ----------------------------------------------------------------------
122 ; ----------------------------------------------------------------------
123 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
124 ; ----------------------------------------------------------------------
126 ; BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
128 ; ----------------------------------------------------------------------
129 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
130 ; ----------------------------------------------------------------------
133 MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
135 ; ----------------------------------------------------------------------
136 ; POWER ON RESET AND INITIALIZATION : I/O
137 ; ----------------------------------------------------------------------
139 ; ----------------------------------------------------------------------
140 ; POWER ON RESET AND INITIALIZATION : PORT1/2
141 ; ----------------------------------------------------------------------
143 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
148 ; UART RTS P2.0 - J2.19 ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
149 ; UART CTS P2.1 - J4.40 <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
151 ; P2.5 - J2.10 <---- SD_CD (Card Detect)
153 MOV #-1,&PAREN ; all inputs with pull up/down resistors
154 MOV #0FFFEh,&PAOUT ; all pins with pullup resistors else LED1
157 ; UCA0_RXD - P1.6 - J1.3 <---- TX UARTtoUSB bridge
158 ; UCA0_TXD - P1.7 - J1.4 ----> RX UARTtoUSB bridge
159 RXD .equ 40h ; P1.6 = RXD
160 TXD .equ 80h ; P1.7 = TXD + FORTH Deep_RST pin
167 .IFDEF TERMINAL4WIRES
168 ; RTS output is wired to the CTS input of UART2USB bridge
169 ; configure RTS as output high (false) to disable RX TERM during start FORTH
170 HANDSHAKOUT .equ P2OUT
173 BIS.B #RTS,&P2DIR ; RTS as output high
174 .IFDEF TERMINAL5WIRES
175 ; CTS input must be wired to the RTS output of UART2USB bridge
176 ; configure CTS as input low (true) to avoid lock when CTS is not wired
178 BIC.B #CTS,&P2OUT ; CTS input pulled down
179 .ENDIF ; TERMINAL5WIRES
180 .ENDIF ; TERMINAL4WIRES
183 SD_CD .equ 20h ; P2.5
186 ; ----------------------------------------------------------------------
187 ; POWER ON RESET AND INITIALIZATION : PORT3-4
188 ; ----------------------------------------------------------------------
190 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
195 ; UCA1 RXD P4.2 - J101.8 <---- TX UARTtoUSB bridge
196 ; UCA1 TXD P4.3 - J101.6 ----> RX UARTtoUSB bridge
197 ; P4.4 - J2.9 ----> SD_CS(Card Select)
198 ; UCB1 CLK P4.5 - J1.7 ----> SD_CLK
199 ; UCB1 SIMO P4.6 - J2.15 ----> SD_SDI
200 ; UCB1 SOMI P4.7 - J2.14 <---- SD_SDO
202 BIS.B #-1,&PBREN ; all pins with pull resistors
203 MOV.B #-1,&PBOUT ; pullup resistors for all pins
206 ; UCA1 RXD P4.2 - J101.8 <---- TX UARTtoUSB bridge
207 ; UCA1 TXD P4.3 - J101.6 ----> RX UARTtoUSB bridge
208 RXD .equ 4 ; P4.2 = RXD
209 TXD .equ 8 ; P4.3 = TXD + FORTH Deep_RST pin
217 SD_CS .equ 10h ; P4.4
221 SD_SEL .equ PBSEL0 ; to configure UCB1
222 SD_REN .equ PBREN ; to configure pullup resistors
223 SD_BUS .equ 0E000h ; pins P4.5 as UCA1CLK, P4.6 as UCA1SIMO & P4.7 as UCA1SOMI
225 ; ----------------------------------------------------------------------
226 ; POWER ON RESET AND INITIALIZATION : PORT5-6
227 ; ----------------------------------------------------------------------
229 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
235 BIS.B #-1,&P6REN ; all pins with pull up/down resistors
236 MOV.B #0BFh,&P6OUT ; all pins with pull up resistors else P6.6
238 ; ----------------------------------------------------------------------
240 ; ----------------------------------------------------------------------
242 .IF (FREQUENCY >8 ) && ( FREQUENCY <= 16)
243 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
244 MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
245 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
246 .ELSEIF FREQUENCY > 16
247 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
248 MOV.B #20h, &FRCTL0 ; 2 waitstate @ 24 MHz
249 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
252 ; ----------------------------------------------------------------------
253 ; POWER ON RESET SYS config
254 ; ----------------------------------------------------------------------
256 MOV #0A500h,&SYSCFG0 ; enable write MAIN + INFO
258 ; ----------------------------------------------------------------------
259 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
260 ; ----------------------------------------------------------------------
262 ; CS code for MSP430FR2355
264 ; to measure SMCLK frequency, wires SMCLK on P1.0:
268 ; to measure REFO frequency, wires ACLK on P1.1:
274 ; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value)
275 MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
277 BIS #0010h,&CSCTL3 ; FLL select REFCLOCK
278 ; MOV #0100h,&CSCTL4 ; ACLOCK select REFO, MCLK & SMCLK select DCOCLKDIV (default value)
283 ; MOV #058h,&CSCTL0 ; preset DCO = measured value @ 0x180 (88)
284 ; MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation
285 MOV #1ED1h,&CSCTL0 ; preset MOD=31, DCO = measured value @ 0x180 (209)
286 MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
287 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
288 ; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh
289 ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz
290 ; MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh
291 ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz
292 MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
293 ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
294 ; =====================================
297 .ELSEIF FREQUENCY = 1
299 ; MOV #100h,&CSCTL0 ; preset DCO = 256
300 ; MOV #00B1h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
301 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
302 MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
303 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
304 ; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh
305 ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz
306 MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh
307 ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz
308 ; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
309 ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
310 ; =====================================
313 .ELSEIF FREQUENCY = 2
315 ; MOV #100h,&CSCTL0 ; preset DCO = 256
316 ; MOV #00B3h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
317 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
318 MOV #00B2h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
319 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
320 ; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh
321 ; fCOCLKDIV = 32768 x (59+1) = 1.996 MHz ; measured : MHz
322 MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch
323 ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz
324 ; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
325 ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz
326 ; =====================================
329 .ELSEIF FREQUENCY = 4
331 ; MOV #100h,&CSCTL0 ; preset DCO = 256
332 ; MOV #00B5h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
333 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
334 MOV #00B4h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
335 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
336 ; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h
337 ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz
339 MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h
340 ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz
342 ; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
343 ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
344 ; =====================================
347 .ELSEIF FREQUENCY = 8
349 ; MOV #100h,&CSCTL0 ; preset DCO = 256
350 ; MOV #00B7h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
351 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
352 MOV #00B6h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
353 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
354 ; MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h
355 ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz
356 MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h
357 ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz
359 ; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h
360 ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz
361 ; =====================================
364 .ELSEIF FREQUENCY = 12
366 ; MOV #100h,&CSCTL0 ; preset DCO = 256
367 ; MOV #00B9h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
368 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
369 MOV #00B8h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
370 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
371 ; MOV #016Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h
372 ; fCOCLKDIV = 32768 x 365+1) = 11.993 MHz ; measured : 11.xxxMHz
373 MOV #016Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h
374 ; fCOCLKDIV = 32768 x 366+1) = 12.025 MHz ; measured : 12.xxxMHz
375 ; MOV #016Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
376 ; fCOCLKDIV = 32768 x 367+1) = 12.058 MHz ; measured : 12.xxxMHz
377 ; =====================================
380 .ELSEIF FREQUENCY = 16
382 ; MOV #100h,&CSCTL0 ; preset DCO = 256
383 ; MOV #00BBh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
384 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
385 MOV #00BAh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
386 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
387 ; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h
388 ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz
389 MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h
390 ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz
391 ; MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
392 ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
393 ; =====================================
396 .ELSEIF FREQUENCY = 20
398 ; MOV #100h,&CSCTL0 ; preset DCO = 256
399 ; MOV #00BDh,&CSCTL1 ; Set 20MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
400 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
401 MOV #00BCh,&CSCTL1 ; Set 20MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
402 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
403 ; MOV #0261h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=261h
404 ; fCOCLKDIV = 32768 x 609+1) = 19.988 MHz ; measured : 19.xxxMHz
405 MOV #0262h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=262h
406 ; fCOCLKDIV = 32768 x 610+1) = 20.021 MHz ; measured : 20.xxxMHz
407 ; MOV #0263h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=263h
408 ; fCOCLKDIV = 32768 x 611+1) = 20.054 MHz ; measured : 20.xxxMHz
409 ; =====================================
412 .ELSEIF FREQUENCY = 24
414 ; MOV #100h,&CSCTL0 ; preset DCO = 256
415 ; MOV #00BFh,&CSCTL1 ; Set 24MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
416 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
417 MOV #00BEh,&CSCTL1 ; Set 24MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
418 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
419 ; MOV #02DBh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DBh
420 ; fCOCLKDIV = 32768 x 731+1) = 23.986 MHz ; measured : 23.xxxMHz
421 MOV #02DCh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DCh
422 ; fCOCLKDIV = 32768 x 732+1) = 24.019 MHz ; measured : 23.xxxMHz
423 ; MOV #02DDh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DDh
424 ; fCOCLKDIV = 32768 x 733+1) = 24.051 MHz ; measured : 24.xxxMHz
425 ; =====================================
429 .error "bad frequency setting, only 0.5,1,2,4,8,12,16,20,24 MHz"
432 BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
433 ; MOV &SAVE_SYSRSTIV,TOS ;
434 ; CMP #2,TOS ; POWER ON ?
435 ; JZ ClockWaitX ; yes
436 ; RRUM #1,X ; wait only 250 ms
437 ClockWaitX MOV #5209,Y ; wait 0.5s before starting after POR
439 ClockWaitY SUB #1,Y ;1
440 JNZ ClockWaitY ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
441 SUB #1,X ; x 32 @ 1 MHZ = 500ms
442 JNZ ClockWaitX ; time to stabilize power source ( 500ms )
444 ;WAITFLL BIT #300h,&CSCTL7 ; wait FLL lock