1 /****************************************
3 *Vane Operating System Common Header
5 ****************************************/
11 void vane_io_cli(void);
12 void vane_io_sti(void);
13 void write_mem_8(int,int);
20 void io_out8(int port, int data);
21 int io_load_eflags(void);
22 void io_store_eflags(int eflags);
25 void ScreenVGA_Graphic(void);
27 extern int vram_start_address;
29 extern short scrnX,scrnY;
42 #define COL8_008400 10
43 #define COL8_848400 11
44 #define COL8_000084 12
45 #define COL8_840084 13
46 #define COL8_008484 14
47 #define COL8_848484 15
50 typedef unsigned char BYTE;
51 typedef unsigned short WORD;
52 typedef unsigned long DWORD;
54 typedef unsigned long long u_int8_t;
55 typedef unsigned int u_int4_t;
56 typedef unsigned short u_int2_t;
57 typedef unsigned short u_int1_t;
59 #define ADR_BOOTINFO 0x00000ff0
60 #define ADR_DISKIMG 0x00100000
61 #define FAT_DISK_PLASE 0x00020000
63 #define SECTOR_SIZE 512
65 #define EX_CHAR_SHORT(source) (unsigned short)(*source++ <<8) | *source++
69 char bootstrap_code[3];
71 unsigned short sector_byte;
72 unsigned char clust_sector;
73 unsigned short reserved_sector;
75 unsigned short root_dir_entry;
76 unsigned short sector;
77 unsigned char media_code;
78 unsigned short fat_sector;
79 unsigned short track_sector;
80 unsigned short drive_head;
81 unsigned int un_known_sector;
82 unsigned int all_sector;
83 unsigned int one_fat_sector;
85 unsigned short fs_ver;
86 unsigned int root_dir_start_clust_no;
87 unsigned short fs_sys_info;
88 unsigned short back_up_sector;
90 unsigned char physical_drive_no;
93 unsigned int volume_s_ID;
94 char volume_label[11];
101 unsigned char drive_number;
102 unsigned char drive_mode;
103 unsigned short drive_cylinders;
104 unsigned char drive_head;
105 unsigned char drive_sectors;
111 int p, q, size, free, flags;
115 int backlink, esp0, ss0, esp1, ss1, esp2, ss2, cr3;
116 int eip, eflags, eax, ecx, edx, ebx, esp, ebp, esi, edi;
117 int es, cs, ss, ds, fs, gs;
121 int sel, flags; /* sel
\82ÍGDT
\82Ì
\94Ô
\8d\86\82Ì
\82±
\82Æ */
127 void fifo32_init(struct FIFO32 *fifo, int size, int *buf, struct TASK *task);
128 int fifo32_put(struct FIFO32 *fifo, int data);
129 int fifo32_get(struct FIFO32 *fifo);
130 int fifo32_status(struct FIFO32 *fifo);
134 /*GDT Segment Descriptor*/
137 unsigned short limitLo;
138 unsigned short baseLo;
139 unsigned char baseMid;
140 unsigned short flags;
141 unsigned char baseHi;
142 } __attribute__ ((packed)) SEGMENT_DESCRIPTOR;
148 SEGMENT_DESCRIPTOR* base;
149 } __attribute__ ((packed)) GDTR;
154 unsigned short baseLo;
155 unsigned short selector;
156 unsigned char reserved;
158 unsigned short baseHi;
159 } __attribute__ ((packed)) GATE_DESCRIPTOR;
164 GATE_DESCRIPTOR* base;
165 } __attribute__ ((packed)) IDTR;
172 #define DEF_IDT_FLAGS_INTGATE_16BIT 0x06
173 #define DEF_IDT_FLAGS_TSKGATE 0x05
174 #define DEF_IDT_FLAGS_CALL_GATE 0x0C
175 #define DEF_IDT_FLAGS_INTGATE_32BIT 0x0E
176 #define DEF_IDT_FLAGS_TRPGATE 0x0F
177 #define DEF_IDT_FLAGS_DPL_LV0 0x00
178 #define DEF_IDT_FLAGS_DPL_LV1 0x20
179 #define DEF_IDT_FLAGS_DPL_LV2 0x40
180 #define DEF_IDT_FLAGS_DPL_LV3 0x60
181 #define DEF_IDT_FLAGS_PRESENT 0x80
183 #define DEF_IDT_INT_NUM_IRQ1 33
184 #define DEF_IDT_INT_NUM_IRQ0 32
185 #define DEF_IDT_INT_NUM_SYSC 0x30
186 #define DEF_IDT_INT_NUM_V86I 0x31
187 #define DEF_IDT_INT_NUM_V86O 0x32
189 #define DEF_IDT_INT_SELECTOR 0x08
194 #define NULL_DESCRIPTOR 0
195 #define CODE_DESCRIPTOR 1
196 #define DATA_DESCRIPTOR 2
197 #define TEMP_DESCRIPTOR 3
198 #define TASK_CODE_DESCRIPTOR 3
199 #define TASK_DATA_DESCRIPTOR 4
200 #define KTSS_DESCRIPTOR 5
202 /* Null Descriptor */
203 #define DEF_GDT_NULL_LIMIT 0x0000
204 #define DEF_GDT_NULL_BASELO 0x0000
205 #define DEF_GDT_NULL_BASEMID 0x00
206 #define DEF_GDT_NULL_FLAGS 0x0000
207 #define DEF_GDT_NULL_BASEHI 0x00
209 /* Code Descriptor */
210 #define DEF_GDT_CODE_LIMIT 0xFFFF
211 #define DEF_GDT_CODE_BASELO 0x0000
212 #define DEF_GDT_CODE_BASEMID 0x00
213 #define DEF_GDT_CODE_FLAGS_BL 0x9A
214 #define DEF_GDT_CODE_FLAGS_BH 0xCF
215 #define DEF_GDT_CODE_FLAGS 0xCF9A
216 #define DEF_GDT_CODE_BASEHI 0x00
218 /* Data Descriptor */
219 #define DEF_GDT_DATA_LIMIT 0xFFFF
220 #define DEF_GDT_DATA_BASELO 0x0000
221 #define DEF_GDT_DATA_BASEMID 0x00
222 #define DEF_GDT_DATA_FLAGS 0xCF92
223 #define DEF_GDT_DATA_FLAGS_BL 0x92
224 #define DEF_GDT_DATA_FLAGS_BH 0xCF
225 #define DEF_GDT_DATA_BASEHI 0x00
228 #define PORT_MASTER_PIC_COMMAND 0x0020
229 #define PORT_MASTER_PIC_STATUS 0x0020
230 #define PORT_MASTER_PIC_DATA 0x0021
231 #define PORT_MASTER_PIC_IMR 0x0021
232 #define PORT_SLAVE_PIC_COMMAND 0x00A0
233 #define PORT_SLAVE_PIC_STATUS 0x00A0
234 #define PORT_SLAVE_PIC_DATA 0x00A1
235 #define PORT_SLAVE_PIC_IMR 0x00A1
236 #define PIC_ICW1 0x11
237 #define PIC_MASTER_ICW2 0x20
238 #define PIC_SLAVE_ICW2 0x28
239 #define PIC_MASTER_ICW3 0x04
240 #define PIC_SLAVE_ICW3 0x02
241 #define PIC_MASTER_ICW4 0x01
242 #define PIC_SLAVE_ICW4 0x01
244 #define PIC_IMR_MASK_IRQ0 0x01
245 #define PIC_IMR_MASK_IRQ1 0x02
246 #define PIC_IMR_MASK_IRQ2 0x04
247 #define PIC_IMR_MASK_IRQ3 0x08
248 #define PIC_IMR_MASK_IRQ4 0x10
249 #define PIC_IMR_MASK_IRQ5 0x20
250 #define PIC_IMR_MASK_IRQ6 0x40
251 #define PIC_IMR_MASK_IRQ7 0x80
252 #define PIC_IMR_MASK_IRQ_ALL 0xFF
255 #define PIT_REG_COUNTER0 0x0040
256 #define PIT_REG_COUNTER1 0x0041
257 #define PIT_REG_COUNTER2 0x0042
258 #define PIT_REG_CONTROL 0x0043
259 #define DEF_PIT_CLOCK 1193181.67
260 #define DEF_PIT_COM_MASK_BINCOUNT 0x01
261 #define DEF_PIT_COM_MASK_MODE 0x0E
262 #define DEF_PIT_COM_MASK_RL 0x30
263 #define DEF_PIT_COM_MASK_COUNTER 0xC0
264 #define DEF_PIT_COM_BINCOUNT_BIN 0x00
265 #define DEF_PIT_COM_BINCOUNT_BCD 0x01
266 #define DEF_PIT_COM_MODE_TERMINAL 0x00
267 #define DEF_PIT_COM_MODE_PROGONE 0x02
268 #define DEF_PIT_COM_MODE_RATEGEN 0x04
269 #define DEF_PIT_COM_MODE_SQUAREWAVE 0x06
270 #define DEF_PIT_COM_MODE_SOFTTRIG 0x08
271 #define DEF_PIT_COM_MODE_HARDTRIG 0x0A
272 #define DEF_PIT_COM_RL_LATCH 0x00
273 #define DEF_PIT_COM_RL_LSBONLY 0x10
274 #define DEF_PIT_COM_RL_MSBONLY 0x20
275 #define DEF_PIT_COM_RL_DATA 0x30
276 #define DEF_PIT_COM_COUNTER0 0x00
277 #define DEF_PIT_COM_COUNTER1 0x40
278 #define DEF_PIT_COM_COUNTER2 0x80