4 * Copyright (c) 2020 Intel
6 * This work is licensed under the terms of the GNU GPL, version 2. See the
7 * COPYING file in the top-level directory.
13 #include "hw/register.h"
16 * The following is how a CXL device's Memory Device registers are laid out.
17 * The only requirement from the spec is that the capabilities array and the
18 * capability headers start at offset 0 and are contiguously packed. The headers
19 * themselves provide offsets to the register fields. For this emulation, the
20 * actual registers * will start at offset 0x80 (m == 0x80). No secondary
21 * mailbox is implemented which means that the offset of the start of the
22 * mailbox payload (n) is given by
23 * n = m + sizeof(mailbox registers) + sizeof(device registers).
25 * +---------------------------------+
27 * | Memory Device Registers |
29 * n + PAYLOAD_SIZE_MAX -----------------------------------
35 * | | Mailbox Payload |
39 * n -----------------------------------
40 * ^ | Mailbox Registers |
42 * | -----------------------------------
44 * | | Device Registers |
46 * m ---------------------------------->
47 * ^ | Memory Device Capability Header|
48 * | -----------------------------------
49 * | | Mailbox Capability Header |
50 * | -----------------------------------
51 * | | Device Capability Header |
52 * | -----------------------------------
53 * | | Device Cap Array Register |
54 * 0 +---------------------------------+
58 #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */
59 #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */
60 #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */
61 #define CXL_CAPS_SIZE \
62 (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */
64 #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */
65 #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */
67 #define CXL_MAILBOX_REGISTERS_OFFSET \
68 (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH)
69 #define CXL_MAILBOX_REGISTERS_SIZE 0x20 /* 8.2.8.4, Figure 139 */
70 #define CXL_MAILBOX_PAYLOAD_SHIFT 11
71 #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT)
72 #define CXL_MAILBOX_REGISTERS_LENGTH \
73 (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE)
75 #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \
76 (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH)
77 #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8
79 #define CXL_MMIO_SIZE \
80 (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \
81 CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH)
83 typedef struct cxl_device_state {
84 MemoryRegion device_registers;
86 /* mmio for device capabilities array - 8.2.8.2 */
88 MemoryRegion memory_device;
92 uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4];
93 uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8];
97 /* mmio for the mailbox registers 8.2.8.4 */
100 uint16_t payload_size;
102 uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH];
103 uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2];
104 uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4];
105 uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8];
120 /* memory region for persistent memory, HDM */
124 /* Initialize the register block for a device */
125 void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev);
127 /* Set up default values for the register block */
128 void cxl_device_register_init_common(CXLDeviceState *dev);
131 * CXL 2.0 - 8.2.8.1 including errata F4
132 * Documented as a 128 bit register, but 64 bit accesses and the second
133 * 64 bits are currently reserved.
135 REG64(CXL_DEV_CAP_ARRAY, 0) /* Documented as 128 bit register but 64 byte accesses */
136 FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16)
137 FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8)
138 FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16)
141 * Helper macro to initialize capability headers for CXL devices.
143 * In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it says:
144 * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
145 * > is the maximum access size allowed for these registers. If this rule is not
146 * > followed, the behavior is undefined
148 * CXL 2.0 Errata F4 states futher that the layouts in the specification are
149 * shown as greater than 128 bits, but implementations are expected to
150 * use any size of access up to 64 bits.
152 * Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple
153 * access to be used for a register up to 64 bits.
155 #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \
156 REG32(CXL_DEV_##n##_CAP_HDR0, offset) \
157 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \
158 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \
159 REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \
160 FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \
161 REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \
162 FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32)
164 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET)
165 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
166 CXL_DEVICE_CAP_REG_SIZE)
167 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE,
168 CXL_DEVICE_CAP_HDR1_OFFSET +
169 CXL_DEVICE_CAP_REG_SIZE * 2)
171 int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate);
172 void cxl_process_mailbox(CXLDeviceState *cxl_dstate);
174 #define cxl_device_cap_init(dstate, reg, cap_id) \
176 uint32_t *cap_hdrs = dstate->caps_reg_state32; \
177 int which = R_CXL_DEV_##reg##_CAP_HDR0; \
179 FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, \
181 cap_hdrs[which] = FIELD_DP32( \
182 cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); \
183 cap_hdrs[which + 1] = \
184 FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \
185 CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \
186 cap_hdrs[which + 2] = \
187 FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \
188 CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \
191 /* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register */
192 REG32(CXL_DEV_MAILBOX_CAP, 0)
193 FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5)
194 FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
195 FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1)
196 FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4)
198 /* CXL 2.0 8.2.8.4.4 Mailbox Control Register */
199 REG32(CXL_DEV_MAILBOX_CTRL, 4)
200 FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1)
201 FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1)
202 FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1)
204 /* CXL 2.0 8.2.8.4.5 Command Register */
205 REG64(CXL_DEV_MAILBOX_CMD, 8)
206 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8)
207 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8)
208 FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20)
210 /* CXL 2.0 8.2.8.4.6 Mailbox Status Register */
211 REG64(CXL_DEV_MAILBOX_STS, 0x10)
212 FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1)
213 FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16)
214 FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16)
216 /* CXL 2.0 8.2.8.4.7 Background Command Status Register */
217 REG64(CXL_DEV_BG_CMD_STS, 0x18)
218 FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16)
219 FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7)
220 FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16)
221 FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16)
223 /* CXL 2.0 8.2.8.4.8 Command Payload Registers */
224 REG32(CXL_DEV_CMD_PAYLOAD, 0x20)
226 REG64(CXL_MEM_DEV_STS, 0)
227 FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1)
228 FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1)
229 FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2)
230 FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
231 FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
235 PCIDevice parent_obj;
238 HostMemoryBackend *hostmem;
239 HostMemoryBackend *lsa;
242 CXLComponentState cxl_cstate;
243 CXLDeviceState cxl_dstate;
246 #define TYPE_CXL_TYPE3 "cxl-type3"
247 OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3)
249 struct CXLType3Class {
251 PCIDeviceClass parent_class;
254 uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
256 uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size,
258 void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,